CN110995390B - Method for transparent transmission of SDH bus data based on FPGA - Google Patents

Abstract

The invention discloses a method for transparently transmitting SDH bus data based on FPGA, which utilizes 2 pairs of differential IO pins of FPGA, adopts SDR technology to realize bidirectional transmission of 1-path bus data or adopts DDR technology to realize bidirectional transmission of 2-path bus data, is connected with a Telecombus interface and a 200MHz clock through a programmable device FPGA, and the differential IO of the FPGA is connected with the differential IO of another FPGA through a connector or directly.

Description

Method for transparent transmission of SDH bus data based on FPGA

Technical Field

The invention relates to the technical field of internal signal processing in SDH, in particular to a method for transparently transmitting SDH bus data based on an FPGA.

Background

The Synchronous Digital Hierarchy (SDH) is a mature technology, supports high-speed remote transmission of large-capacity data, can access various types of rate services such as ethernet, voice, image and the like, and adopts a standard international unified technical standard, so that equipment of different manufacturers can access the network, and the SDH is very beneficial to networking. Therefore, SDH has a lot of applications in the backbone network and the access network, and is still very important in the whole transmission network.

The SDH system is composed of a plurality of SDH network elements. The network element device needs to complete the functions of service access mapping, multiplexing/demultiplexing, interleaving, overhead processing and pointer processing. The traditional network element equipment adopts a special chip to complete the functions. The chip is limited by the chip process level, the increment requirement on the service bandwidth and quantity, the service expansibility, the heat dissipation and other requirements, so that no chip can simultaneously process the functions in most occasions. That is, the SDH network element device needs to use different dedicated chips to process the corresponding functions, respectively. For interconnection between different chips, there are two conventional methods, one is to use a dedicated serial/parallel conversion chip for interconnection, as shown in fig. 1. The other is to use parallel TelecomBus buses (at least 22 lines per bus in both directions, with two clock lines) to connect directly, as shown in FIG. 2. Because the SDH network element devices all use the FPGA to process a logic function, if a plurality of serial/parallel conversion chips are additionally added, the integration level of the devices is reduced, and power consumption is increased. Whereas for the second approach, as the number of services increases (e.g. every 1 way of STM-1/4 rate light increases), at least 22 lines are added, and correspondingly at least 82 lines are added for every 1 way of STM-16 rate light increase. The dramatic increase in the interconnections between boards has a significant adverse effect on signal integrity, PCB routing difficulty/cost, and circuit board size, especially when the bus needs to communicate with 1 other circuit board through a connector and backplane.

The US6820159B2 patent mentions that a LVDS interface can be used to transport SDH network element bus data by using a predefined code table to correspondingly 8B/10B encode the data or status of the bus. According to the method, the state analysis of the bus needs to be added for coding, so that internal resources of a chip are additionally occupied, and meanwhile, the clock extraction technology is adopted, so that the design difficulty is increased.

Disclosure of Invention

The invention aims to solve the problems that the internal part of a circuit board of the existing SDH network element equipment or buses among different circuit boards are interconnected with too many signal lines among chips, which is not beneficial to signal integrity, PCB wiring, service expansion and the like, and provides a method for transparently transmitting SDH bus data based on an FPGA.

The technical scheme for realizing the purpose of the invention is as follows:

a method for transmitting SDH bus data transparently based on FPGA is characterized in that 2 pairs of FPGA differential IO pins are utilized, SDR technology is adopted to realize bidirectional transmission of 1-path bus data or DDR technology is adopted to realize bidirectional transmission of 2-path bus data, the FPGA is connected with a TelecomBus bus interface and a 200MHz clock through a programmable device FPGA, and the differential IO of the FPGA is connected with the differential IO of another FPGA through a connector or directly, and the method comprises the following steps:

1) TelecomBus bus- > differential IO direction processing, comprising the following steps:

1-1) firstly, combining 8-bit data, 1-bit J0J1 signals and 1-bit PL signals of a TelecomBus bus into 10-bit data by using a channel associated 19.44MHz clock of the bus, and carrying out 5b/6b coding;

1-2) sending the coded data into a sending buffer;

1-3) reading 6bit data from the cache, performing parallel/serial conversion by using OSERDES, if 2 paths of buses need to be output through 1 pair of differential pins, adopting DDR in the ODDR data format, otherwise adopting SDR;

1-4) outputting 223.28Mbit/s serial bit stream to a differential pin through OBUFDS, and outputting a differential signal;

2) and (3) processing the difference IO- > TelecomBus bus direction, comprising the following steps:

2-1) receiving data from a differential IO interface of the FPGA, and converting the received data into a single-ended signal;

2-2) carrying out serial/parallel conversion on the single-ended signal to obtain 6-bit parallel data;

2-3) designing a shift register, circularly shifting the 6-bit parallel data obtained in the step 2-2) into the shift register, intercepting 6 bits from the shift register, sending the 6 bits into a 6b/5b decoding module for 6b/5b decoding, and obtaining 5-bit parallel data after decoding;

2-4) recovering the decoded 5-bit parallel data into a 10-bit TelecomBus bus, and performing synchronous detection;

2-5) utilizing the periodic characteristics of A1A2 bytes and J0 pulses of a TelecomBus bus to carry out adjustment control on 6-bit interception of a shift register and input sampling delay, and when the A1A2 bytes and the J0 pulses of the TelecomBus bus meet the requirements under certain 6-bit interception control and sampling delay adjustment setting combination, locking current control parameters, and sending data decoded by 6b5b into a receiving buffer;

2-6) reading out data from the receiving cache and restoring the data into a TelecomBus bus;

the synchronous detection is that the periodic characteristics of A1A2 bytes and J0 pulses embedded in a TelecomBus bus are utilized, and when 3 continuous frames can position the specified A1A2 bytes or J0 pulse signals at the specified positions, the synchronization is considered to be real synchronization; when the specified A1A2 byte or J0 pulse signal cannot be located in the specified position of the continuous 3 frames, the actual step loss is considered;

the 6bit interception of the shift register and the adjustment control of the input sampling delay are controlled by utilizing the characteristics of a TelecomBus bus frame structure and 125us frame frequency, and the specific steps are as follows:

(1) firstly, a 500us time window is opened to ensure that the detection of the synchronous state can be completed in the window;

(2) if the synchronization is carried out in the time window, the sampling parameter 1 and the shift control parameter are considered to be credible, and the step (3) is carried out, otherwise, the step (5) is carried out;

(3) continuously and gradually adjusting sampling delay parameters of serial/parallel conversion, detecting the out-of-step state of the sampling delay parameters in a 500us time window, and recording a sampling parameter 2 entering the out-of-step state;

(4) taking the intermediate value of the sampling parameter 1 and the sampling parameter 2 as the optimal sampling parameter, latching the parameter, and unlocking the parameter only when the sampling parameter is out of step or reset;

(5) when the time window in the step (2) is not synchronous, adjusting an interception bit of the shift register, and then detecting the synchronization again in the time window of 500 us;

(6) if no synchronization is detected after 6 shifts, adjusting sampling delay control parameters of serial/parallel conversion, repeating the steps (2) to (5) until synchronization, latching the sampling parameter 1 and the shift control parameters at the moment, then repeating the steps (3) and (4), and finally completing the acquisition of the optimal sampling parameters.

The sampling parameter 1 and the sampling parameter 2 are input sampling delay parameters.

The invention provides a method for transparently transmitting SDH bus data based on FPGA, which has the following advantages:

1. the common differential IO of the FPGA is utilized to solve the transparent transmission interconnection of the buses among the chips or the buses among the boards;

2. realizing automatic sampling adjustment control on received signals;

3. the method of 5b6b coding and decoding is used for avoiding the length of the signal being 0 or 1;

4. performing serial/parallel and parallel/serial conversion by using ISERDES/OSERDES of the FPGA;

5. the sampling delay is automatically adjusted by utilizing the characteristics of a TelecomBus bus of SDH network element equipment in combination with idelay;

6. the delay output of the TelecomBus bus is adjusted by utilizing the input reference signal, so that the TelecomBus bus is conveniently butted with a rear-stage module (such as cross connection);

7. the RAM resource of FPGA is used for realizing the sending/receiving cache;

8. a signal source is embedded in the FPGA to detect a channel;

9. and loopback in different directions is set, so that debugging is facilitated.

Drawings

FIG. 1 is a conventional inter-chip interconnection scheme 1;

FIG. 2 is a conventional inter-chip interconnection scheme 2;

FIG. 3 is a diagram of the FPGA external hardware connection of the present invention;

FIG. 4 is a block diagram of the FPGA internal processing of the present invention;

FIG. 5 is a sample/shift control flow diagram;

FIG. 6 is a timing diagram of the TelecomBus bus;

fig. 7 is a synchronization detection flow chart.

Detailed Description

The invention will be further elucidated with reference to the drawings and examples, without however being limited thereto.

Example (b):

a method for transmitting SDH bus data transparently based on FPGA, the method utilizes 2 pairs of FPGA differential IO pins, as shown in figure 3, adopts SDR technology to realize bidirectional transmission of bus data for 1 path or DDR technology to 2 paths, and is connected with TelecomBus bus interface and 200MHz clock through programmable device FPGA, the differential IO of FPGA is connected with the differential IO of another FPGA through connector or directly, including the following steps, as shown in figure 4:

1) TelecomBus bus- > differential IO direction processing, comprising the following steps:

1-1) firstly, combining 8-bit data, 1-bit J0J1 signals and 1-bit PL signals of a TelecomBus bus into 10-bit data by using a channel associated 19.44MHz clock of the bus, and carrying out 5b/6b coding;

1-2) sending the coded data into a sending buffer;

1-3) reading 6bit data from the cache, performing parallel/serial conversion by using OSERDES, if 2 paths of buses need to be output through 1 pair of differential pins, adopting DDR in the ODDR data format, otherwise adopting SDR;

1-4) outputting 223.28Mbit/s serial bit stream to a differential pin through OBUFDS, and outputting a differential signal;

2) and (3) processing the difference IO- > TelecomBus bus direction, comprising the following steps:

2-1) converting the differential data into an 223.28Mbit/s serial bit stream using IBUFDS;

2-2) loading a default sampling delay parameter, and performing serial/parallel conversion by using IDELAY and ISERDES to obtain 6-bit parallel data;

2-3) generating a 12-bit shift register, and shifting the 6-bit parallel data obtained in the step 2-22) into the register;

2-4) intercepting 6 bits (intercepting the 6 th bit in the initial state) from the register, sending the intercepted 6 bits into a 6b/5b decoding module, and obtaining 5-bit parallel data after decoding;

2-5) recovering 5-bit parallel data into a 10-bit TelecomBus bus, and performing synchronous detection;

2-6) the sampling/shifting control module samples and shifts the serial/parallel conversion module and the shifting register according to the detection result of the synchronous detection;

2-7) after the sampling/shifting parameters are locked, 5-bit parallel data are sent into a receiving buffer and output to a TelecomBus bus.

The synchronous detection, as shown in fig. 6, uses the characteristics of the telecommus bus, in order to distinguish the pseudo A1a2 bytes from the pseudo J0 pulses, when the specified A1a2 bytes or the J0 pulse signals can be located at the specified positions in consecutive 3 frames, the true synchronization is considered; the actual loss of synchronization is considered when none of the 3 consecutive frames at the specified location locates the specified A1a2 byte or the J0 pulse signal, as shown in fig. 7.

The 6-bit interception of the shift register and the adjustment and control of the input sampling delay are controlled by using the characteristics of a TelecomBus bus frame structure and a 125us frame frequency, as shown in FIG. 5, the specific steps are as follows:

(1) firstly, a 500us time window is opened to ensure that the detection of the synchronous state can be completed in the window;

(2) if the synchronization is carried out in the time window, the sampling parameter 1 and the shift control parameter are considered to be credible, and the step (3) is carried out, otherwise, the step (5) is carried out;

(3) continuously and gradually adjusting the sampling parameters of serial/parallel conversion, detecting the out-of-step state within a time window of 500us, and recording the sampling parameter 2 entering the out-of-step state;

(4) taking the intermediate value of the sampling parameter 1 and the sampling parameter 2 as the optimal sampling parameter, latching the parameter, and unlocking the parameter only when the sampling parameter is out of step or reset;

(5) when the time window in the step (2) is not synchronous, adjusting an interception bit of the shift register, and then detecting the synchronization again in the time window of 500 us;

(6) if no synchronization is detected after 6 shifts, adjusting sampling delay control parameters of serial/parallel conversion, repeating the steps (2) to (5) until synchronization, latching the sampling parameter 1 and the shift control parameters at the moment, then repeating the steps (3) and (4), and finally completing the acquisition of the optimal sampling parameters.

Claims (1)

1. A method for transmitting SDH bus data transparently based on FPGA is characterized in that 2 pairs of FPGA differential IO pins are utilized, SDR technology is adopted to realize bidirectional transmission of 1-path bus data or DDR technology is adopted to realize bidirectional transmission of 2-path bus data, the FPGA is connected with a TelecomBus bus interface and a 200MHz clock through a programmable device FPGA, and the differential IO of the FPGA is connected with the differential IO of another FPGA through a connector or directly, and the method comprises the following steps:

1) TelecomBus bus- > differential IO direction processing, comprising the following steps:

1-1) firstly, combining 8-bit data, 1-bit J0J1 signals and 1-bit PL signals of a TelecomBus bus into 10-bit data by using a channel associated 19.44MHz clock of the bus, and carrying out 5b/6b coding;

1-2) sending the coded data into a sending buffer;

1-3) reading 6bit data from the cache, performing parallel/serial conversion by using OSERDES, if 2 paths of buses need to be output through 1 pair of differential pins, adopting DDR in the ODDR data format, otherwise adopting SDR;

1-4) outputting 223.28Mbit/s serial bit stream to a differential pin through OBUFDS, and outputting a differential signal;

2) and (3) processing the difference IO- > TelecomBus bus direction, comprising the following steps:

2-1) receiving data from a differential IO interface of the FPGA, and converting the received data into a single-ended signal;

2-2) carrying out serial/parallel conversion on the single-ended signal to obtain 6-bit parallel data;

2-3) designing a shift register, circularly shifting the 6-bit parallel data obtained in the step 2-2) into the shift register, intercepting 6 bits from the shift register, sending the 6 bits into a 6b/5b decoding module for 6b/5b decoding, and obtaining 5-bit parallel data after decoding;

2-4) recovering the decoded 5-bit parallel data into a 10-bit TelecomBus bus, and performing synchronous detection;

2-5) utilizing the periodic characteristics of A1A2 bytes and J0 pulses of a TelecomBus bus to carry out adjustment control on 6-bit interception of a shift register and input sampling delay, and when the A1A2 bytes and the J0 pulses of the TelecomBus bus meet the requirements under certain 6-bit interception control and sampling delay adjustment setting combination, locking current control parameters, and sending data decoded by 6b5b into a receiving buffer;

2-6) reading out data from the receiving cache and restoring the data into a TelecomBus bus;

the synchronous detection is that the periodic characteristics of A1A2 bytes and J0 pulses embedded in a TelecomBus bus are utilized, and when 3 continuous frames can position the specified A1A2 bytes or J0 pulse signals at the specified positions, the synchronization is considered to be real synchronization; when the specified A1A2 byte or J0 pulse signal cannot be located in the specified position of the continuous 3 frames, the actual step loss is considered;

the 6bit interception of the shift register and the adjustment control of the input sampling delay are controlled by utilizing the characteristics of a TelecomBus bus frame structure and 125us frame frequency, and the specific steps are as follows:

(1) firstly, a 500us time window is opened to ensure that the detection of the synchronous state can be completed in the window;

(2) if the synchronization is carried out in the time window, the sampling parameter 1 and the shift control parameter are considered to be credible, and the step (3) is carried out, otherwise, the step (5) is carried out;

(3) continuously and gradually adjusting sampling delay parameters, detecting the out-of-step state within a 500us time window, and recording a sampling parameter 2 entering the out-of-step state;

(4) taking the intermediate value of the sampling parameter 1 and the sampling parameter 2 as the optimal sampling parameter, latching the parameter, and unlocking the parameter only when the sampling parameter is out of step or reset;

(5) when the time window in the step (2) is not synchronous, adjusting an interception bit of the shift register, and then detecting the synchronization again in the time window of 500 us;

(6) if no synchronization is detected after 6 times of shifting, adjusting sampling delay control parameters of serial/parallel conversion, repeating the steps (2) to (5) until synchronization, latching the sampling parameter 1 and the shifting control parameters at the moment, then repeating the steps (3) and (4), and finally completing the acquisition of the optimal sampling parameters;

the sampling parameter 1 and the sampling parameter 2 are input sampling delay parameters.

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