CN104993982A

CN104993982A - Ethernet realization system of FPGA chip internally provided with PHY transceiver function

Info

Publication number: CN104993982A
Application number: CN201510257301.7A
Authority: CN
Inventors: 叶品勇; 陈庆旭; 陈新之
Original assignee: Nanjing SAC Automation Co Ltd
Current assignee: Nanjing SAC Automation Co Ltd
Priority date: 2015-05-19
Filing date: 2015-05-19
Publication date: 2015-10-21

Abstract

The invention discloses an Ethernet realization system of an FPGA chip internally provided with a PHY transceiver function. The Ethernet realization system comprises the FPGA chip and an FPGA external transceiver. The FPGA chip comprises an MAC module and a PHY module. In a data transmitting process, data of the MAC module is cached to a memory, Ethernet frame head frame tail insertion and encoding are performed, parallel-serial conversion and encoding are performed, and difference signals are sent to the external transceiver through an internal transceiver; and in a data receiving process, the difference signals are converted into sing-end signals, serial asynchronous data signal clock data recovery is performed, encoding is carried out on recovered data, frame head frame tail identification and decoding are performed, the data is arranged as byte aligned data after serial-parallel conversion, the byte aligned data is stored into the memory, and finally the data is transmitted to the MAC module for processing. According to the invention, the FPGA chip is internally provided with the PHY transceiver and MAC controller functions, and in this way, the Ethernet is realized, so that the integration and the reliability are improved.

Description

The Ethernet of the built-in PHY transceiver function of a kind of fpga chip realizes system

Technical field

The Ethernet that the present invention relates to the built-in PHY transceiver function of a kind of fpga chip realizes system, belongs to ethernet technology field.

Background technology

Connect according to OSI (Open System Interconnect open systems interconnection reference model) reference model Ethernet and comprise physical layer (PHY) and data link layer (MAC).Physical layer defines data and transmits and the electricity required for reception and light signal, line status, clock reference, data encoding and circuit etc., and provides standard interface to data link layer device, and the chip of physical layer is referred to as PHY transceiver.Data link layer then provides the functions such as the structure of addressing mechanism, Frame, data error inspection, transfer control, the data-interface providing standard to network layer, and the chip of data link layer is referred to as mac controller.

Due to the only embedded mac controller and do not comprise PHY transceiver of optional CPU (processor) chip or FPGA (field programmable gate array) chip in the market, therefore, external PHY transponder chip (or PHY+MAC chip) is needed when realizing ethernet communication, ethernet physical layer function is realized by independently PHY transponder chip, by MII or RMII interface inter-link between PHY transponder chip and controller chip, by MDIO Interface realization processor chips to the management of PHY transponder chip.

Above scheme, must external PHY transponder chip (or PHY+MAC chip) in order to realize 100,000,000 optical Ethernet communications.First kind and the cost of device is added; Secondly because PHY transponder chip needs corresponding peripheral circuit support, the complexity of pcb board design is added; Again pass through MII or RMII interface inter-link between PHY transponder chip and processor chips, belong to the interconnected of chip-scale, holding wire is more, there is certain error code hidden danger.

Summary of the invention

For the deficiency that prior art exists, the Ethernet that the object of the invention is to provide the built-in PHY transceiver function of a kind of fpga chip realizes system, PHY transceiver and mac controller function is achieved respectively in fpga chip inside, the Ethernet realized thus, both improve integrated level and reliability, turn reduce pcb board design complexities; Both decrease part category, in turn save cost.

To achieve these goals, the present invention realizes by the following technical solutions:

The Ethernet of the built-in PHY transceiver function of a kind of fpga chip of the present invention realizes system, comprises fpga chip and FPGA external transceiver, fpga chip comprises MAC module and PHY module, the FPGA internal transceiver that PHY module comprises FIFO memory, codec, data clock recovery module, single-ended-differential converter, differential to single-ended transducer and is connected with FPGA external transceiver, described FIFO memory is connected with MAC module by MII interface, when sending data, first by described MII interface by the data buffer storage to be sent of MAC module to FIFO memory, secondly carry out Ethernet frame head by described codec, postamble inserts and 4B5B encodes, and carry out parallel-serial conversion and nrzi encoding, finally by described single-ended-single-ended signal is converted to differential signal, and differential signal is sent to FPGA external transceiver by described FPGA internal transceiver by differential converter, when receiving data, first by described external transceiver, differential signal is sent to FPGA internal transceiver, and by described differential to single-ended transducer, differential signal is converted to single-ended signal, secondly recover module by described data clock and carry out asynchronous serial data signal clock date restoring, then the data after recovery are carried out NRZI decoding by described codec, and carry out the frame head of frame data, postamble identification and 4B5B decoding, be that byte-aligned data are stored in described FIFO memory finally by serioparallel exchange Final finishing, by described MII interface, data are passed to MAC module again to process.

Also phase-locked loop is provided with in above-mentioned fpga chip, described phase-locked loop exports multiple sampled clock signal and recovers module to data clock, multiple sampling clock phase is evenly distributed in the clock cycle, multiple sampling clock is sampled to asynchronous serial data-signal successively, again by the sampled result of multiple sampling clock stored in FIFO memory, clock and the data message of asynchronous serial data-signal can be recovered according to 0,1 saltus step information of bit stream.

Above-mentioned FPGA external transceiver is connected with FPGA internal transceiver by LVDS differential signal.

The present invention is inner to fpga chip by PHY transponder chip function transplanting, not only PHY transceiver function is comprised but also comprise mac controller function in FPGA single-chip inside, interconnected by internal chip enable signal between PHY transceiver module and mac controller module, namely ensure that high reliability signal is interconnected, also facilitate simultaneously and PHY transceiver module is managed; Owing to decreasing PHY transponder chip, therefore greatly can simplify pcb board design, improve integrated level, reduce part category, reduce costs; Due to FPGA design flexibility, can as required flexible expansion network interface number and increase other additional function (as support IEEE1588 couple time etc. customize function).

Accompanying drawing explanation

Fig. 1 is the system block diagram that the Ethernet of the built-in PHY transceiver function of a kind of fpga chip of the present invention realizes system;

Fig. 2 is the transmission data flowchart of ethernet PHY transceiver function of the present invention;

Fig. 3 is the receiving data stream journey figure of ethernet PHY transceiver function of the present invention;

Fig. 4 is multiphase clock sampling schematic diagram.

Embodiment

The technological means realized for making the present invention, creation characteristic, reaching object and effect is easy to understand, below in conjunction with embodiment, setting forth the present invention further.

See Fig. 1, the 100000000 optical Ethernet implementations that the present invention proposes, by realizing PHY transponder chip function in fpga chip inside to substitute independently PHY transponder chip, then FPGA and exterior light transceiver are connected by LVDS differential signal and realize (carrying out differential signal conversion as required).

According to the functional requirement of 100Base-FX 100,000,000 optical Ethernet physical layer PHY transponder chip, its transceiving data flow process as shown in Figures 2 and 3.

Transmission flow: first by MII interface by the data buffer storage to be sent of mac controller module to sending FIFO, next carries out Ethernet frame head, postamble inserts and 4B5B coding, again carry out parallel-serial conversion and nrzi encoding, finally by lvds driver, single-ended signal is converted to differential signal again and exports optical transceiver to.

Receive flow process: first the differential signal that optical transceiver inputs is converted to single-ended signal by LVDS receiver, next carries out asynchronous serial data signal clock date restoring, and the data after recovering are carried out NRZI decoding, again carry out the frame head of frame data, postamble identification and 4B5B decoding, be byte-aligned data stored in reception FIFO finally by serioparallel exchange Final finishing, then by MII interface, data passed to mac controller module and carry out the process such as abnormal judgement, CRC check, address filtering.

In PHY transceivers data flow, asynchronous serial data-signal time data Recovery processing is one of difficult point of the present invention, serial data rate due to 100,000,000 optical Ethernets is 125Mbps, more than 2 times must be greater than according to that Qwest's Sampling Theorem sample rate and just can recover initial data, according to reality test experience, consider the impacts such as signal edge trembling, sample rate clock and data recovery more than 4 times is more satisfactory.But main flow fpga chip dominant frequency, at about 400MHz, is difficult to be realized by the sampling of single clock high magnification in the market.

See Fig. 4, the mode that the present invention adopts multiphase clock to sample, 8 125MHz sampled clock signals are exported by the built-in PLL phase-locked loop of FPGA, and 8 sampling clock phases are evenly distributed in the clock cycle, i.e. neighbouring sample clock skew 45 degree, successively asynchronous serial data-signal is sampled by 8 sampling clocks, again by the sampled result of 8 sampling clocks stored in bit stream FIFO, clock and the data message of asynchronous serial data-signal can be recovered according to 0,1 saltus step information of bit stream.

System of the present invention is not limited only to 100 m ethernet and optical Ethernet, for ten mbit ethernets and electric Ethernet applicable equally.

PHY transceiver and mac controller function are all transplanted to fpga chip inside by the present invention program, interconnected by internal chip enable signal between PHY transceiver module and mac controller module, ensure that high reliability signal is interconnected, simultaneously the also convenient management to PHY transceiver module.Owing to decreasing PHY transponder chip, therefore greatly can simplify pcb board design, improve integrated level, reduce material variety, reduce costs.In addition, due to FPGA design flexibility, can as required flexible expansion network interface number and increase other additional function, as support IEEE1588 couple time etc. customize function.

More than show and describe general principle of the present invention and principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; what describe in above-described embodiment and specification just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.Application claims protection range is defined by appending claims and equivalent thereof.

Claims

1. the Ethernet of the built-in PHY transceiver function of fpga chip realizes a system, it is characterized in that, comprises fpga chip and FPGA external transceiver;

Described fpga chip comprises MAC module and PHY module;

The FPGA internal transceiver that described PHY module comprises FIFO memory, codec, data clock recovery module, single-ended-differential converter, differential to single-ended transducer and is connected with FPGA external transceiver, described FIFO memory is connected with MAC module by MII interface;

When sending data, first by described MII interface by the data buffer storage to be sent of MAC module to FIFO memory, secondly carry out Ethernet frame head by described codec, postamble inserts and 4B5B encodes, and carry out parallel-serial conversion and nrzi encoding, finally by described single-ended-single-ended signal is converted to differential signal, and differential signal is sent to FPGA external transceiver by described FPGA internal transceiver by differential converter;

When receiving data, first by described external transceiver, differential signal is sent to FPGA internal transceiver, and by described differential to single-ended transducer, differential signal is converted to single-ended signal, secondly recover module by described data clock and carry out asynchronous serial data signal clock date restoring, then the data after recovery are carried out NRZI decoding by described codec, and carry out the frame head of frame data, postamble identification and 4B5B decoding, be that byte-aligned data are stored in described FIFO memory finally by serioparallel exchange Final finishing, by described MII interface, data are passed to MAC module again to process.

2. the Ethernet of the built-in PHY transceiver function of fpga chip according to claim 1 realizes system, it is characterized in that,

Also phase-locked loop is provided with in described fpga chip, described phase-locked loop exports multiple sampled clock signal and recovers module to data clock, multiple sampling clock phase is evenly distributed in the clock cycle, multiple sampling clock is sampled to asynchronous serial data-signal successively, again by the sampled result of multiple sampling clock stored in FIFO memory, clock and the data message of asynchronous serial data-signal can be recovered according to 0,1 saltus step information of bit stream.

3. the Ethernet of the built-in PHY transceiver function of fpga chip according to claim 1 realizes system, it is characterized in that,

Described FPGA external transceiver is connected with FPGA internal transceiver by LVDS differential signal.