CN117120856A

CN117120856A - Chip test circuit and method

Info

Publication number: CN117120856A
Application number: CN202180095927.6A
Authority: CN
Inventors: 付海涛; 黄俊林; 邓斌; 崔昌明
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-06-24
Filing date: 2021-06-24
Publication date: 2023-11-24
Also published as: WO2022266959A1

Abstract

A chip test circuit and method relates to the chip technical field, which can utilize a high-speed serial test interface to receive high-speed test data of a test machine and convert the high-speed test data into multi-channel input data, liberate the test data transmission bandwidth limitation of a single channel and improve the chip test efficiency. The chip test circuit comprises a high-speed serial test interface, a first transmission and a second transmission, wherein the high-speed serial test interface is used for receiving high-speed serial input data sent by a test machine station, converting the high-speed serial input data into multi-channel input data and sending the multi-channel input data to the first transmission; the first speed changer is used for normalizing the multi-channel input data into single-channel input data and testing the circuit to be tested; the second transmission is used for receiving single-channel output data from the circuit to be tested, converting the single-channel output data into multi-channel output data and outputting the multi-channel output data to the high-speed serial test interface; the high-speed serial test interface is also used for converting the multi-channel output data into high-speed serial output data and sending the high-speed serial output data to the test machine.

Description

Chip test circuit and method

Technical Field

The present application relates to the field of chip technologies, and in particular, to a chip test circuit and a method.

Background

Based on mass production of chips, logic testing of chips requires a large number of multiplexed digital input/output (I/O) resources to generate Test vectors (Test vectors) required for chip testing. With the development of moore's law, the logic module growth trend of the logic mode is very asynchronous with the I/O resource growth of the chip, namely in the Scan test technology for chip test, although the scale of the logic module is increased, the parallel test rate of the logic module is reduced due to the limitation of the I/O resource, so that the Scan test is serialized, and when the same I/O resource is distributed to more logic modules for use, the compression ratio of the I/O resource and the Scan chain (chain) is increased, so that the Scan test efficiency is reduced.

In order to improve the test efficiency of Scan, how to obtain the I/O resources that can be reused by Scan becomes the current bottleneck problem. In the past, the SerDes I/O resources are directly multiplexed into low-speed (25-100 Mhz) digital I/O resources in Scan test, and the transmission bandwidth of test data which can be promoted by multiplexing into the low-speed digital I/O resources is very limited, and can not continuously obtain larger Scan test data transmission bandwidth, can not meet the actual mass production requirement of chips, and has lower Scan test efficiency. In the current international standard test protocol, how to use the serial-parallel conversion function of a Serializer and a deserializer (Serializer and DeSerializar, serDes) to realize high-speed transmission of Scan data, and the parallel is used as Scan I/O of a chip test, so that the problem of limitation of I/O transmission bandwidth can be solved. Scan I/O is a typical form of it, and the test loading of the chip also needs to take into account other large bandwidth test data streams.

Disclosure of Invention

The embodiment of the application provides a chip test circuit and a method, which are based on the fact that a serializer and a deserializer are utilized to provide a test data stream or a test bus with large bandwidth, the subsequent test purpose of the bus is not restricted, a high-speed serial test interface can be utilized to receive high-speed test data of a test machine and convert the high-speed test data into multi-channel input data, the limit of the test data transmission bandwidth of a single channel is released, and the chip test efficiency is improved.

In order to achieve the above purpose, the embodiment of the application adopts the following technical scheme:

in a first aspect, a chip test circuit is provided, the chip test circuit includes a high-speed serial test interface, a first transmission and a second transmission, the high-speed serial test interface is interconnected with a test machine based on a capacitive coupling mode, and a differential transmission mode is adopted to receive data transmitted by the test machine; the high-speed serial test interface is used for receiving high-speed serial input data sent by the test machine station, converting the high-speed serial input data into multi-channel input data and sending the multi-channel input data to the first transmission; the rate of high-speed serial input data is greater than or equal to 1.25Gbps; the first transmission is used for normalizing the multi-channel input data into single-channel input data, wherein the single-channel input data is used for testing a circuit to be tested, and the circuit to be tested is coupled with the chip test circuit; the second transmission is used for receiving single-channel output data from the circuit to be tested, converting the single-channel output data into multi-channel output data and transmitting the multi-channel output data to the high-speed serial test interface; wherein the single-channel output data corresponds to the single-channel input data; the high-speed serial test interface is also used for converting the multi-channel output data into high-speed serial output data and sending the high-speed serial output data to the test machine.

In this way, under the condition that the high-speed serial test interface receives the high-speed serial data and converts the high-speed serial data into the multi-channel input data, the transmission rate of the test data can be greatly improved through the transmission of the high-speed serial input data and the converted multi-channel input data. In addition, under the condition that the high-speed serial test interface is utilized to receive the high-speed serial input data and output the multi-channel input data, even if logic resources to be tested in the chip are continuously increased, the I/O resources for testing data transmission occupy fewer I/O pins of the chip (pins of the high-speed serial input data, pins of the high-speed serial output data, pins of the multi-channel input data and pins of the multi-channel output data). In addition, the bit width and frequency of the input end and the output end of the Gecarbox can be changed through the uplink and downlink speed changer (Gecarbox), so that the bit width normalization integration of the multi-channel input data can be realized, and the wiring frequency of a test Bus (Bus) can be improved.

In one possible design, the multi-channel input data is transmitted on M channels, M being an integer greater than 1; the first transmission is used for receiving multi-channel input data under the 1-frequency multiplication clock domain, and performing bit width conversion on the multi-channel input data to obtain single-channel input data; outputting single-channel input data under an M frequency multiplication clock domain; the second transmission is used for receiving the single-channel output data under the M frequency multiplication clock domain, and performing bit width conversion on the single-channel output data to obtain multi-channel output data; outputting multichannel output data under a 1-frequency multiplication clock; the bit width occupied by the single-channel input data and the bit width occupied by the single-channel output data are fixed.

For example, the multi-channel input data is transmitted on 4 channels, the input of the first transmission receives the 4-channel input data in the 1-multiple clock domain, and the output of the first transmission outputs the single-channel input data in the 4-multiple clock domain. Therefore, the wiring frequency of the test data on the test bus can be improved by integrating and normalizing the bit width of the multichannel input data and using 4 times of frequency multiplication input data. Similarly, when the second transmission receives single-channel output data in 4 times frequency, the speed of feeding the single-channel output data back to the test machine is also improved, and therefore the chip test efficiency is improved overall.

In one possible design, the first transmission includes a first buffer and a first bit width conversion circuit; a first buffer for buffering multichannel input data received from the high-speed serial test interface under the 1-frequency multiplication clock domain; the first bit width conversion circuit is used for reading the multi-channel input data from the first buffer according to the channel bit width of the single-channel input data to obtain the single-channel input data and outputting the single-channel input data under the M frequency multiplication clock domain; the second transmission comprises a second buffer and a second bit width conversion circuit; the second buffer is used for buffering the single-channel output data received under the M frequency multiplication clock domain; and the second bit width conversion circuit is used for reading the single-channel output data from the second buffer according to the bit width of each channel for outputting the multi-channel output data to obtain the multi-channel output data, and outputting the multi-channel output data under the 1-frequency multiplication clock domain.

Therefore, the first transmission can integrate and normalize the bit width by the bit width conversion part after caching the multichannel input data, and input the normalized single-channel input data under the M frequency multiplication clock domain, so that the wiring frequency of the test data on the test bus can be improved. Similarly, when the second transmission receives single-channel output data in M frequency multiplication, the speed of feeding the single-channel output data back to the test machine is also improved, and therefore the chip test efficiency is improved overall.

In one possible design, the test circuit further includes a decoder, an encoder, a finite state machine FSM, a first flow conduit, and a second flow conduit; the first flow conduit and the second flow conduit each comprise a multi-stage storage unit; an output of the first transmission is coupled to an input of the decoder, and an output of the decoder is coupled to an input of the first flow conduit; the output end of the first flow pipeline is coupled with a test bus of the test circuit; the input end of the second speed changer is coupled with the output end of the encoder, the input end of the encoder is coupled with the output end of the second flow pipeline, and the input end of the second flow pipeline is coupled with the test bus; the FSM is coupled to the decoder, the encoder, the first stream pipe, and the second stream pipe.

In one possible design, a decoder is configured to decode single channel input data, send decoded test data to a first flow pipe, and send decoded instructions to the FSM; an FSM for determining the operating states of the encoder, the first stream pipe, and the second stream pipe according to the decoded instructions; a first flow conduit for transmitting test data to the test bus in accordance with the operating state of the first flow conduit determined by the FSM; the second flow pipeline is used for receiving a test result returned through the test bus according to the operation state of the second flow pipeline determined by the FSM and sending the test result to the encoder; and the encoder is used for encoding the test result according to the operation state of the encoder determined by the FSM to obtain single-channel output data and transmitting the single-channel output data to the second transmission.

In the existing chip test, the test data input to the chip is not decoded and encoded, the application can decode the received input data to obtain the test data through the decoder, and the test data is output to the test bus after being cached in a hierarchical manner through the first flow pipeline. And the fed-back test result can be output to the encoder for encoding after being cached in a grading way through the second stream pipeline, so that single-channel output data is obtained. Wherein the FSM can determine the operational status of the encoder, the first stream pipe, and the second stream pipe based on the decoded instructions. In this way, the application provides a standard chip test architecture which can be suitable for the transmission of test data with various rates.

The test circuit further includes a gate circuit coupled to each of the plurality of levels of memory cells; the first flow pipeline comprises a first-stage storage unit and a second-stage storage unit; a first level storage unit for buffering test data received from the decoder; the first-stage storage unit is also used for sending the test data stored in the first-stage storage unit to the second-stage storage unit when receiving the clock signal sent by the gate control circuit coupled with the first-stage storage unit; and the second-level storage unit is used for caching the test data received from the first-level storage unit. Therefore, the first stream pipeline and the second stream pipeline provided by the application output the input data in the hierarchical cache way, and the problem of increased chip cost caused by data caching by using the FIFO in the prior art can be avoided.

In one possible design, the test circuit further includes a plurality of frame header aligners and channel aligners; the input end of each frame head aligner is coupled with one output port of the high-speed serial test interface, the output end of each frame head aligner is coupled with one input end of the channel alignment circuit, and a plurality of output ends of the channel aligner are coupled with a plurality of input ports of the first transmission; each frame head aligner is used for receiving one channel input data in the multi-channel input data from one output port of the high-speed serial test interface, aligning the frame head of the input data of one channel and outputting the aligned data to the channel aligner; and the channel aligner is used for aligning the data among the channels of the multi-channel input data received from the frame header aligners and outputting the data to the first transmission.

This is because when the multi-channel input data output from the high-speed serial test interface is input to the first transmission, the input data packets may be out of order, and thus the frame header aligner may perform frame header alignment on the multi-channel input data received from the high-speed serial test interface, so as to send the input data of each channel in the multi-channel input data to the channel aligner in the order after the frame header alignment.

The channel aligner performs inter-channel data alignment, which is understood that, because there may be inconsistency in the speed of transmitting data in each channel, when one data packet is split into multiple packets to be transmitted in multiple channels, each packet may not reach the first transmission at the same time when transmitting data in different channels, and thus, the channel aligner may reach the first transmission at the same time when transmitting small data packets after splitting the same data packet in different channels.

Illustratively, each frame header aligner includes a third buffer and a frame header alignment circuit; a third buffer for buffering one of the multi-channel input data received from one output port of the high-speed serial test interface; the frame head alignment circuit is used for reading one channel input data from the third buffer, sequencing the one channel input data according to the frame heads and outputting the one channel input data to the channel alignment circuit;

The channel aligner includes a fourth buffer and a channel alignment circuit; a fourth buffer for buffering the plurality of channel input data transmitted from the plurality of channel alignment circuits; and the channel alignment circuit is used for reading the plurality of channel input data from the fourth buffer, aligning the plurality of channel input data among channels and outputting the aligned data to the first transmission.

In one possible design, the test circuit may further include a descrambler, a scrambler, a demultiplexer, and a combiner. The descrambler is used for descrambling single-channel output data output by the first transmission; the scrambler is used for scrambling the single-channel output data output by the encoder and then sending the single-channel output data to the second transmission; a demultiplexer for transmitting the single channel input data received from the first stream pipe to a combinational logic circuit of a designated output terminal; and the combiner is used for feeding back test results transmitted from the test bus ports with different bit widths to the second flow pipeline through the combiner.

Thus, the data is transmitted in the chip test circuit through the scrambler and the descrambler, and the code stream after scrambling can be sufficiently random as long as the number of stages of the scrambler is properly selected, so that the transmission quality of the signal in an off-chip transmission channel and the like are improved.

The demultiplexer may be understood as transmitting single-channel input data to a test bus port with a width of 32 bits to be output to a circuit to be tested, or transmitting single-channel input data to a test bus port with a width of 64 bits to be output to a circuit to be tested, or transmitting single-channel input data to a test bus port with a width of 128 bits to be output to a circuit to be tested, etc. The realization mode of the demultiplexer and the combiner can meet the requirement that test data is transmitted in test buses with various bit widths so as to realize the test of the circuit to be tested.

In a second aspect, a method for testing a chip is provided, the chip including a high-speed serial test interface, the high-speed serial test interface being interconnected with a test machine based on a capacitive coupling manner, and receiving data transmitted by the test machine using a differential transmission manner, the method comprising: the chip receives high-speed serial input data sent by the test machine through the high-speed serial test interface and converts the high-speed serial input data into multi-channel input data; the rate of high-speed serial input data is greater than or equal to 1.25Gbps; the chip normalizes the multi-channel input data into single-channel input data, wherein the single-channel input data is used for testing a circuit to be tested in the chip; the chip converts single-channel output data received from the circuit to be tested into multi-channel output data, wherein the single-channel output data corresponds to the single-channel input data; the chip converts the multichannel output data into high-speed serial output data through the high-speed serial test interface and sends the high-speed serial output data to the test machine.

The advantages of the second aspect may be seen from the description of the first aspect, and will not be repeated here.

In one possible design, the multi-channel input data is transmitted on M channels, M being an integer greater than 1; the chip normalizing the multi-channel input data into single-channel input data comprises: the chip performs bit width conversion on the multichannel input data transmitted under the 1 frequency multiplication clock domain to obtain single-channel input data transmitted under the M frequency multiplication clock domain; the chip converting the single channel output data received from the circuit to be tested into multi-channel output data includes: the chip performs bit width conversion on the single-channel output data received under the M frequency multiplication clock domain to obtain multi-channel output data transmitted under the 1 frequency multiplication clock domain; the bit width occupied by the single-channel input data and the bit width occupied by the single-channel output data are fixed.

Illustratively, the chip normalizing the multi-channel input data to single-channel input data includes: the chip caches multichannel input data received from the high-speed serial test interface under the 1-frequency multiplication clock domain; the chip reads the multi-channel input data from the first buffer according to the channel bit width of the output single-channel input data to obtain the single-channel input data, and outputs the single-channel input data in the M frequency multiplication clock domain;

The chip converting the single channel output data received from the circuit to be tested into multi-channel output data includes: the chip caches single-channel output data received under the M frequency multiplication clock domain; and the chip reads the single-channel output data from the second buffer according to the bit width of each channel of the output multi-channel output data to obtain the multi-channel output data, and outputs the multi-channel output data under the 1-frequency multiplication clock domain.

In one possible design, the method further includes, before the chip converts the single channel output data received from the circuit to be tested into the multi-channel output data: the chip decodes the single-channel input data to obtain decoded instructions and test data; the chip caches the test data through the multi-stage storage units and outputs the cached test data to a test bus in the chip, and the test data is transmitted to a circuit to be tested through the test bus; and the chip caches the test result returned from the circuit to be tested through the multi-stage storage unit according to the decoded instruction, and encodes the cached and output test result to obtain single-channel output data.

Illustratively, the multi-level memory cell includes a first-level memory cell and a second-level memory cell; the chip outputs test data to a test bus in the chip after the test data is cached by the multi-stage memory unit comprises: controlling the first-level storage unit to buffer test data received from the decoder; controlling the first-stage storage unit to send test data stored in the first-stage storage unit to the second-stage storage unit when receiving a clock signal sent by a gating circuit coupled with the first-stage storage unit; and controlling the second-level storage list to cache the test data received from the first-level storage unit.

In one possible design, the method further includes, prior to the chip normalizing the multi-channel input data to single-channel input data: the chip performs frame header alignment of data on the input data of each channel in the multi-channel input data; and the chip performs inter-channel data alignment on the multi-channel input data with the frame heads aligned.

Illustratively, the chip performing frame header alignment of data for each channel of input data in the multi-channel input data includes: the chip controls the third buffer to buffer one channel input data in the multi-channel input data received from one output port of the high-speed serial test interface; the chip controls the frame head alignment circuit to read one channel input data from the third buffer, and outputs the channel input data to the channel alignment circuit after sequencing the channel input data according to the frame heads;

the chip performs inter-channel data alignment on the multi-channel input data with the frame heads aligned, and the method comprises the following steps: the chip controls the fourth buffer to buffer the plurality of channel input data sent from the plurality of channel alignment circuits; the chip control channel alignment circuit reads a plurality of channel input data from the fourth buffer, performs inter-channel alignment on the plurality of channel input data, and outputs the data to the first transmission.

In a third aspect, there is provided a communication device comprising at least one processor coupled to a memory, the at least one processor being configured to read and execute a program stored in the memory to cause the communication device to perform a method as described in the second aspect and any one of the possible designs of the second aspect.

In a fourth aspect, there is provided a computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the method of any one of the above second aspect and any one of the possible designs of the second aspect.

Drawings

FIG. 1 is a schematic diagram of the logic scale of a chip and the trend of the I/O bandwidth available for Scan multiplexing according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a chip test design architecture according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a chip test circuit according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a chip test circuit according to an embodiment of the present application;

FIG. 5 is a schematic flow chart of a method for testing a chip according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a chip test circuit with multiple channels of 4 32-bit wide channels according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a first transmission and a second transmission according to an embodiment of the present application;

FIG. 8 is a schematic diagram of an implementation manner of a 1-frequency-doubling clock domain and an M-frequency-doubling clock domain according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a chip test circuit for generating a 1-frequency-multiplied clock domain and a 4-frequency-multiplied clock domain using a PLL according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a FSM according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a test data input to a first flow channel according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a chip test circuit according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of a frame header alignment circuit and a channel alignment circuit according to an embodiment of the present application;

fig. 14 is a schematic structural diagram of a chip according to an embodiment of the present application.

Detailed Description

For ease of understanding, a description of some of the concepts related to the embodiments of the application are given by way of example for reference. The following is shown:

design for testability (design for testability, DFT): an integrated circuit design technique that allows specific structures to be implanted into a circuit during the design phase to test the circuit after the design is completed.

Scan test: one of the important methods for testing digital integrated circuits can effectively screen out bad chips and improve the product quality.

SerDes: the system comprises a high-speed serial-parallel conversion circuit, a clock data recovery circuit, a data encoding and decoding circuit, a clock correction and channel binding circuit and the like, and provides a physical layer foundation for various high-speed serial data transmission protocols. The TX transmit and RX receive ends of SerDes are functionally independent and are composed of two sublayers, a physical medium adaptation layer (physical media attachment, PMA) and a physical coding sublayer (physical coding sublayer, PCS).

Automated test equipment (Automotive Tester Equipment, ATE): in the semiconductor industry, it is intended to mean an integrated circuit (integrated circuit, IC) automatic tester for testing the integrity of integrated circuit functions, the final flow of integrated circuit manufacturing, to ensure the quality of integrated circuit manufacturing.

High speed test interface (High Speed Serial Test Interface, HSSTI): it is understood as a high-speed serial test tool for loading test data inside a chip.

Finite synchronous state machine (Finite state machine, FSM): the control center is composed of a state register and a combinational logic circuit, can perform state transition according to a preset state according to a control signal, and is a control center for coordinating related signal actions and completing specific operations.

CMD: the Windows command prompt is a shell program for running Windows control panel program or a DOS program under Windows NT; or a shell program for running a control panel program under Windows CE.

End of packet (EOP): an instruction for the last packet in the data stream.

With the increase of the number of the test modules of the chip, the same I/O resource can be allocated to more logic resources for use, namely, although the logic modules in the chip are increased, the I/O resource is not increased, and the test efficiency of the chip is lower. Fig. 1 is a schematic diagram showing the trend of the digital logic scale of the chip and the transmission bandwidth available for the Scan test vector to multiplex, wherein the horizontal axis represents year, and the two vertical axes represent the digital logic scale and the transmission bandwidth of the Scan test vector, respectively. It can be seen that with time, two curves representing the logic scale of the chip: the logical scale of the network project (X-network project) shown in curve 1 and the logical scale of the Terminal project (Terminal project) shown in curve 2 are rapidly increasing; however, of the 2 curves of the total bandwidth of the digital pin, curve 3 and curve 4 show: with the increase of 8Gbps to 10Gbps of the access frequency of the I/O resources in the X-network project and the increase of 6.4Gbps to 8Gbps of the access frequency of the I/O resources in the Terminal project, the pin total bandwidth (I/O number X access frequency) of the I/O resources is slowly increased.

Currently, based on the international standard test protocol of the institute of electrical and electronics engineers (Institute of Electrical and Electronics Engineers, IEEE) 1149.10, how to use serial-parallel conversion functional channels of SerDes to realize high-speed transmission of Scan data, and can be used as Scan I/O for chip testing after parallel, so as to solve the problem of limitation of digital I/O transmission bandwidth. For example, serDes I/O, which may use a single channel (single lane), may be multiplexed as a basic functional channel, providing as much Scan test bandwidth as possible. However, the 1149.10 standard does not specify or limit the specific architecture and design of a specific user manufacturer, and the technology is directly related to SerDes used by each manufacturer, and the design architecture for high-speed transmission of the premature Scan data, that is, the technology maturity is low, only relevant packet (Packets) protocol parts, and the circuit architecture and implementation of the relevant packet (Packets) protocol parts are not standardized, so that a series of ecosystem support from design, verification, test vector, diagnosis and the like is needed. Moreover, each manufacturer chooses to construct two complex first-in first-out (First In First Output, FIFO) circuits inside the serial-to-parallel converted codec circuit to realize Scan test bandwidth, and there is a large overhead inside.

In summary, scan testing of chips requires multiplexing of I/O resources to complete the logic module (or pattern graph) expansion. However, as the process goes deep, the logic scale increases, the amount of I/O resources required does not increase in proportion to the I/O bandwidth resources of the actual chip, and expansion of the I/O bandwidth resources that can be multiplexed is highly desirable.

In this regard, the present application provides a chip test circuit for loading and transmitting test data, which can utilize a high-speed serial test interface, such as HSSTI, to convert high-speed serial input data received from a test machine station into input data transmitted in a plurality of channels, perform a chip test by converting the input data of the plurality of channels into input data of a single channel through a first transmission, convert the output data of the single channel obtained after the test into output data of the plurality of channels through a second transmission, and convert the output data of the plurality of channels into high-speed serial output data through the high-speed serial test interface to be fed back to the test machine station. In this way, under the condition that the high-speed serial test interface receives the high-speed serial input data and converts the high-speed serial input data into the multi-channel input data, the transmission rate of the test data can be greatly improved through the transmission of the high-speed serial input data and the converted multi-channel input data. In addition, under the condition that the high-speed serial test interface is utilized to receive the high-speed serial input data and output the multi-channel input data, even if logic resources to be tested in the chip are continuously increased, the I/O resources for testing data transmission occupy fewer I/O pins of the chip (pins of the high-speed serial input data, pins of the high-speed serial output data, pins of the multi-channel input data and pins of the multi-channel output data). In addition, the bit width and frequency of the input end and the output end of the Gecarbox can be changed through the uplink and downlink speed changer (Gecarbox), so that the bit width normalization integration of the multi-channel input data can be realized, and the wiring frequency of a test Bus (Bus) can be improved.

The high-speed serial input data in the present application can be understood as serial input data having a rate of 1.25Gbps or more.

As shown in fig. 2, the chip test design architecture of the present application can be applied in a docking scenario of an automated test equipment (automotive tester equipment, ATE) and a device under test (device under test, DUT). The DUT here may be, for example, a chip.

By way of example, ATE can realize high-speed code stream of a single channel of 5-10 Gbps, and can realize test data transmission with extremely large bandwidth when matching with the design framework provided by the application, thereby meeting the test I/O requirement of a very large scale chip and being similar to multiplexing resources of 100-400 common low-speed 100Mhz digital I/O.

For example, as shown in fig. 3, in a chip, the chip test circuit provided by the present application may include a high-speed serial test interface, a first transmission, and a second transmission. The high-speed serial test interface is interconnected with the test machine based on a capacitive coupling mode, and data transmitted by the test machine is received by adopting a differential transmission mode. The coupling mode and the data transmission mode are used for matching the high-speed serial test interface to receive the high-speed serial input data from the test machine.

The output end a of the test machine is coupled with the input end b of the high-speed serial test interface, a plurality of RX ports of the high-speed serial test interface are coupled with a plurality of input ends (c, d and …) of the first transmission, and the output end e of the first transmission is coupled with the test bus; the input f of the second transmission is coupled to the test bus, the outputs (g, h, …) of the second transmission are coupled to the TX ends of the high speed serial test interface, and the output i of the high speed serial test interface is coupled to the input j of the test bench.

The high-speed serial test interface can be used for receiving high-speed serial input data sent by the test machine station, converting the high-speed serial input data into multi-channel input data and sending the multi-channel input data to the first transmission; for example, the high-speed serial data is 5Gbps, the high-speed serial test interface receives the serial input data of 5Gbps through a single channel (b port), converts the serial input data into the multi-channel input data, and outputs the multi-channel input data through a plurality of RX ports of the high-speed serial test interface. The multi-channel input data here includes test data to be tested for a circuit to be tested of the chip.

The first transmission is used for normalizing the multi-channel input data into single-channel input data, wherein the single-channel input data is used for testing a circuit to be tested, and the circuit to be tested is coupled with the chip test circuit. The normalization here can be realized, for example, by means of bit-width conversion. For example, 4 channels, each channel transmits 32-bit multi-channel input data, and the multi-channel input data is subjected to bit width conversion to obtain single-channel 32-bit input data, wherein the transmission frequency of the single-channel 32-bit input data is 4 times that of each channel in the 4 channels.

The second transmission is used for receiving single-channel output data from the circuit to be tested, converting the single-channel output data into multi-channel output data and transmitting the multi-channel output data to the high-speed serial test interface; wherein the single channel output data corresponds to the single channel input data. For example, the single-channel output data may be input to the second transmission at a frequency that is a multiple of 4, and when the second transmission performs bit-width conversion on the single-channel output data to obtain the 4-channel output data, the 4-channel output data is output at a frequency that is a multiple of 1.

The high-speed serial test interface is also used for converting the multi-channel output data into high-speed serial output data and transmitting the serial output data to the test machine. For example, the 4-channel output data may be received from the second transmission through a plurality of TX ports of the high-speed serial test interface, which reconverts the 4-channel output data into high-speed serial output data for output to the test station.

Therefore, the application can improve the receiving rate of the test data under the condition that the high-speed serial test interface is used for receiving the high-speed serial data from the test machine and converting the high-speed serial data into multi-channel input data transmission; the high-speed serial test interface may provide a feedback rate of test results in the event that the high-speed serial test interface receives channel output data from the second transmission and converts the channel output data to high-speed serial output data. Moreover, less I/O resources of the high-speed serial test interface can be occupied for transmitting test data. And the wiring frequency of test data on the test bus can be improved through the bit width conversion and the frequency conversion of the uplink and downlink speed changer for input data and output data.

Using the chip test circuit shown in fig. 3, the present application provides a chip test circuit as shown in fig. 4. The chip test circuit also includes a decoder, an encoder, an FSM, a first flow channel, and a second flow channel. The first flow conduit and the second flow conduit comprise a multi-level memory unit. The first stream pipe and the second stream pipe here can be understood as streaming pipe.

The output end e of the first speed changer is coupled with the input end k of the decoder, and the output end l of the decoder is coupled with the input end m of the first flow pipeline; the output end n of the first flow pipeline is coupled with a test bus of the test circuit;

The input end f of the second speed changer is coupled with the output end o of the encoder, the input end p of the encoder is coupled with the output end q of the second flow pipeline, and the input end r of the second flow pipeline is coupled with the test bus;

the FSMs are each coupled to a third terminal s of the decoder, a third terminal t of the encoder, a third terminal u of the first stream pipe, and a third terminal v of the second stream pipe.

Applying the chip test circuit shown in fig. 4, the decoder may be used to decode single channel input data, send the decoded test data to the first flow pipe, and send the decoded instructions to the FSM;

an FSM for determining the operating states of the encoder, the first stream pipe, and the second stream pipe according to the decoded instructions;

a first flow conduit for transmitting test data to the test bus in accordance with the operating state of the first flow conduit determined by the FSM;

the second flow pipeline is used for receiving a test result returned through the test bus according to the operation state of the second flow pipeline determined by the FSM and sending the test result to the encoder;

and the encoder is used for encoding the test result according to the operation state of the encoder determined by the FSM to obtain single-channel output data and transmitting the single-channel output data to the second transmission.

Using the chip test circuit shown in fig. 4, the present application provides a method for testing a chip, as shown in fig. 5, the method comprising:

501. the chip receives high-speed serial input data sent by the test machine through the high-speed serial test interface and converts the high-speed serial input data into multi-channel input data.

The serial input data is understood to mean, among other things, the transmission of symbols, which constitute data and characters, in a time-series, bit-by-bit manner. High-speed serial input data can be understood as serial input data with a transmission rate higher than 100Mhz and a transmission bandwidth of 5 to 10Gbps on a single channel, for example. Multi-channel input data may be understood as data transmitted over multiple channels, e.g. one packet transmitted over a single channel is split into 4 shares, and input data is transmitted over 4 channels.

For example, when the test board is ATE and the high-speed serial test interface is HSSTI, as shown in fig. 6, the HSSTI may receive high-speed serial input data sent by the ATE, and convert the high-speed serial input data into 4-channel input data for transmission on 4 channels. The transmission rate of the high-speed serial input data is 5Gbps, the bit width is 128 bits, the 128-bit wide high-speed serial input data is switched to 4 copies of the data input to the first transmission in 4 channels, and the bit width of each channel is 32 bits.

502. The chip normalizes the multi-channel input data into single-channel input data, and the single-channel input data is used for testing a circuit to be tested in the chip.

In some embodiments, the multi-channel input data is assumed to be transmitted on M channels, M being an integer greater than 1. The first transmission can be used for receiving multi-channel input data under a 1-frequency multiplication clock domain, and performing bit width conversion on the multi-channel input data to obtain single-channel input data; and outputting single-channel input data under the M frequency multiplication clock domain. The bit width occupied by the single-channel input data is fixed.

The bit width of each of the M channels of the HSSTI output is generally related to the traffic pattern, and may be 16 bits, 32 bits, 40 bits, or the like. Shown in fig. 6 is a 32-bit width.

In some embodiments, as shown in fig. 7 (illustrated with 4 32-bit wide lanes), the first transmission includes a first buffer and a first bit wide conversion circuit;

a first buffer for buffering multichannel input data received from the high-speed serial test interface under the 1-frequency multiplication clock domain; the first bit width conversion circuit is used for reading the multi-channel input data from the first buffer according to the channel bit width of the single-channel input data to obtain the single-channel input data and outputting the single-channel input data under the M frequency multiplication clock domain;

For example, when the first transmission receives input data of 4 32-bit wide channels in the 1-multiple clock domain, the input data of the 4 32-bit wide channels may be buffered in the first buffer, and then the first bit wide conversion circuit may read the input data with 32-bit wide from the first buffer, and output the 32-bit wide input data of a single channel in the M-multiple clock domain, so as to implement the multi-channel data normalization process.

There are many implementations of the 1-and M-multiplied clock domains. For example, as shown in fig. 8, assuming that M is 4, there are homologous clock sources without frequency offset on both sides of the first transmission in HSSTI, the first transmission may receive 4 32-bit wide channels of input data through the first clock Zhong Guanjiao (rxoclk) in the clock domain divided by 4 (CLK divided by 4), and output a single channel of 32-bit wide input data through the second clock pin (rxeuxclk) in the clock domain divided by 1. In other words, the first transmission receives 4 32-bit wide lanes of input data through rxoclk in the 1-frequency clock domain, and outputs normalized single lane 32-bit wide input data through rxaxclk in the 4-frequency clock domain. The implementation of the second transmission is similar to that of the first transmission, the second transmission receives single-channel 32-bit-wide output data through rxocuclk in the 4-frequency multiplication clock domain, and outputs 4 32-bit-wide-channel output data through rxoculk in the 1-frequency multiplication clock domain. In other embodiments, the clock domains with homology and no frequency offset may be set in the ATE to ensure that the clock domains on both sides of the first transmission are homologous.

For another example, as shown in fig. 9, if HSSTI is unable to internally divide to generate divided-by-1 and divided-by-4 clock domains, or the divided-by-HSSTI-4 clock is not output to the pin of the module, it is contemplated that, outside HSSTI, a divided-by-1 second clock pin may be used to instantiate a CLK divided-by-4 clock, which may be used by the first transmission to receive 4 32-bit wide channels of input data. Note that the input data at this time originates from the original first clock domain Zhong Guanjiao inside the HSSTI, where it is necessary to ensure that the corresponding synchronization process is performed between the received input data clock domain and CLK 4.

In some embodiments, the bit width of the single channel input data output by the first transmission is fixed, as is the bit width of the single channel output data input to the second transmission, i.e., the bit width of the single channel output data input to the second transmission is also fixed. For example, in the example of fig. 6, the bit width after normalization of the first transmission is defined as 32 bits by default, and the bit width input to the second transmission is also defined as 32 bits by default. That is, when the bit width of each channel in the multi-channel input data inputted to the first transmission is 16, 32 or 40, the multi-channel input data is normalized to a fixed frame format of 32 bits, and then the processing is continued. This processing of packets per frame based on a fixed frame format may result in a simple and efficient manner of transmission. The bit width of each channel in the HSSTI multi-channel input data is generally related to the traffic pattern.

503. The chip decodes the single-channel input data to obtain decoded instructions and test data.

Illustratively, when the first transmission outputs 32-bit wide single-channel input data to the decoder using the bit-width normalization of the above-described transmission, the decoder may decode the single-channel input data to identify the header, trailer, instructions, content, etc. of the input data stream. Wherein a single channel input data can be understood as a frame of data. The FSM may determine the operational state of the encoder, the first stream pipe, and the second stream pipe from the decoded instructions, i.e., perform step 504. The content here is to be understood as test data, for example Scan test data.

504. The chip determines the operating states of the encoder, the first stream pipe, and the second stream pipe based on the decoded instructions.

It will also be appreciated that the decoder may send the decoded instructions to the FSM, which may customize the corresponding state machine sequences of the encoder, the first stream pipe, and the second stream pipe based on the decoded instructions. For example, the encoder enters a sequence of encoded states, a sequence in which the first stream pipe buffers test data in the multi-level memory cells, and a sequence in which the second stream pipe buffers feedback test data in the multi-level memory cells.

As already described above, the bit width of the single channel input data output by the first transmission is fixed, and the bit width of the single channel output data input to the second transmission is also fixed, and then the FSM may be understood as an FSM based on a fixed bit width of one state, and each data frame may be defined as one state.

Illustratively, according to the definition requirements of the IEEE 1149.10 protocol, in the data stream of the single channel input data:

the format of the frame header may be: frame header 8 bits+CMD8 bits+16 bits Payload (content), collectively referred to as "CMD";

the format of cyclic redundancy check (Cyclic Redundancy Check, CRC) occupies 32 bits, collectively referred to as "CRC"; the single-channel input data verification device is used for verifying single-channel input data;

the format of the end of frame occupies 32 bits and the unified command is "EOP".

When the decoder recognizes the frame head and the frame tail according to the definition requirement, and single channel input data between the frame head and the frame tail is a frame of complete data.

The types of CMDs may include a normal CMD, a CHCMD (CHselect CMD), and a test CMD (ScanCMD), among others. When the decoder recognizes these 3 CMD and sends them to the FSM, the FSM can enter 3 states according to these 3 CMD.

A state diagram of the FSM is shown in fig. 10. When the FSM receives a common CMD in the decoded instruction, the FSM may jump to the CMD state, i.e., enter a state in which the test circuitry is configured. During configuration, the state of the FSM is idle-CMD-CRC-EOP. This configuration process can be understood, for example, as a process of resetting the test circuit. Namely, firstly unlocking the test circuit, performing circuit configuration, such as selecting some variables in a decoder, performing series configuration on storage units of the first flow pipeline and the second flow pipeline, and configuring a test bus, bit width and speed;

When the FSM receives the CHCMD in the decoded instruction, the FSM may jump to the state of the CHCMD, i.e., enter a channel select operating state, to determine the test bus on which to transmit test data. The state of the FSM in this process may be idle-CHCMD-CH content-CRC-EOP. For example, the test bus includes buses with bit widths of 32, 64 and 128 bits, and when the CHCMD instruction (Chselect content, CH content) indicates that the test bus with the bit width of 32 bits is selected, the FSM instructs the test data transmitted by the first flow pipe to enter the chip on the test bus with the bit width of 32 bits.

When the FSM receives the decoded command and the test CMD in the content, the FSM may jump to the state of the test CMD, i.e., enter a transmission state of the test data, to transmit the test data on the test bus. The state of the FSM in this process may be idle-test CDM-test content-CRC-EOP. When the FSM identifies a test CDM, the decoder and the first stream pipe may be instructed to transmit test data to the bus.

505. The chip outputs the test data to the test bus in the chip after the test data is cached by the multi-stage storage unit, and the test data is transmitted to the circuit to be tested through the test bus.

That is, when the first stream pipe receives test data from the decoder, the first stream pipe may perform multi-level buffering on the test data through the multi-level storage unit and output the test data to the test bus.

In some embodiments, the test circuit further includes a gating circuit coupled to each of the plurality of levels of memory cells; the first flow pipeline comprises a first-stage storage unit and a second-stage storage unit;

a first level storage unit for buffering test data received from the decoder;

the first-stage storage unit is also used for sending the test data stored in the first-stage storage unit to the second-stage storage unit when receiving the clock signal sent by the gate control circuit coupled with the first-stage storage unit;

and the second-level storage unit is used for caching the test data received from the first-level storage unit.

Illustratively, fig. 11 is a schematic diagram of test data input to a first stream pipe, which is when the decoder decodes single channel input data to obtain test data. Wherein the first flow conduit is a 3-stage storage unit: a level 1 memory cell, a level 2 memory cell, and a level 3 memory cell, each including a plurality of memory cells (the memory cells may be registers, for example, fig. 11 shows 32 registers). Each stage of memory cells is coupled with a gating circuit for beating test data. For example, when the gating circuit a receives a write_enable signal 1, the gating circuit a may send a clock signal (WCLK) 1 to the level 1 memory unit, and the level 1 sends test data in the memory unit to the level 2; after a period of time, when the gating circuit B receives the write enable signal 2, the gating circuit B can send a clock signal 2 to the 2 level, and the 2 level sends test data in the storage unit to the 3 level; after a period of time, when the gating circuit C receives the write enable signal 3, the gating circuit C may send a clock signal 3 to the 3 stages, and the 3 stages send the test data in the memory cell to the test bus. The write enable signal may be triggered by a counter (counter generator) in the FSM.

It should be noted that the clock signals of the gating circuit and the decoder and the FSM may be homologous, i.e. all come from the same main clock (main clock). The first flow conduit may transmit test data to the test bus based on the operating state of the first flow conduit (the plurality of enable signals received) as determined by the FSM.

506. And the chip caches the test result returned from the circuit to be tested through the multi-stage storage unit according to the decoded instruction, and encodes the cached and output test result to obtain single-channel output data.

When the test data is transmitted through various time sequence conversion and various interfaces inside the chip to obtain a test result, the test result is returned to the second flow pipeline, the internal structure of the second flow pipeline is similar to that of the first flow pipeline shown in fig. 11, namely, when the test result is returned to the second flow pipeline, the second flow pipeline receives the test result returned through the test bus according to the operation state of the second flow pipeline determined by the FSM, and the test result is returned to the encoder through the multi-stage storage unit in the second flow pipeline. And the encoder encodes the test result to obtain single-channel output data.

It will be appreciated that in the present application, the operating states of the encoder, the first stream pipe, and the second stream pipe determined by the FSM should coincide with the timing of the data processing by the encoder, the first stream pipe, and the second stream pipe to achieve seamless joining of states and data.

In the embodiment of the application, the seamless connection of the state and the data can be realized by determining the number of stages of the storage units of the first stream pipeline and the second stream pipeline for caching the data through the FSM, namely, the seamless connection of the state and the data is realized through the number of stages of the storage units of the streaming pipe. That is, the number of stages of the memory cells of the first stream pipe and the second stream pipe conform to: the FSM triggers the encoder to enter a state encoding the single channel response data consistent with the time at which the single channel response data is returned to the encoder.

That is, the number of stages of memory cells in the first stream pipe and the number of stages of memory cells in the second stream pipe may be used to determine the latency of the encoder to enter encoding of the test results. After the test data is sent out and the test result reaches the coding state of the coder after passing through the series of the storage units of the first flow pipeline and the series of the storage units of the second flow pipeline, the FSM just triggers the coder to enter the coding state and matches with the time when the test result returns to the coder, and therefore the delay-free flow test data transmission can be realized. The implementation mode does not need any FIFO buffer memory for test data and test results, and realizes complete pipeline processing of test data input and test result output through a fixed frame FSM, so that the implementation difficulty and cost are low, and the implementation method is friendly to physical implementation and time sequence.

507. The chip converts single-channel output data received from the circuit to be tested into multi-channel output data, and the single-channel output data corresponds to the single-channel input data.

The encoder can send the obtained single-channel output data to a second transmission, and the second transmission is used for receiving the single-channel output data under the M frequency multiplication clock domain, and performing bit width conversion on the single-channel output data to obtain multi-channel output data; and outputting the multi-channel output data under the 1-frequency multiplication clock.

In some embodiments, the second transmission includes a second buffer and a second bit width conversion circuit;

the second buffer is used for buffering the single-channel output data received under the M frequency multiplication clock domain; and the second bit width conversion circuit is used for reading the single-channel output data from the second buffer according to the bit width of each channel for outputting the multi-channel output data to obtain the multi-channel output data, and outputting the multi-channel output data under the 1-frequency multiplication clock domain.

It will be appreciated that, when the implementation of the second transmission is similar to the first transmission and the multi-channel output data is 4 output data with 32 bit width, the single-channel 32 bit wide output data may be received under the frequency-multiplied clock domain by the circuit similar to that shown in fig. 8 or fig. 9, and after being buffered in the second buffer of the second transmission, the single-channel 32 bit wide output data is converted into 4 output data with 32 bit wide channels by the second bit wide conversion circuit, and the 4 output data with 32 bit wide channels are output to the high-speed serial test interface under the frequency-multiplied clock domain of 1, for example, to the multiple TX ports of the HSSTI.

508. The chip converts the multichannel output data into high-speed serial output data through the high-speed serial test interface and sends the serial output data to the test machine.

For example, when the plurality of TX ends of the HSSTI receive the 4-channel output data, the 4-channel output data may be converted into high-speed serial output data, and the high-speed serial output data may be sent to the test station through a single channel, so that the test station may determine whether the circuit to be tested of the chip is normal through the received high-speed serial output data.

It can be understood that the application can improve the receiving rate of the test data under the condition that the high-speed serial test interface is utilized to receive the high-speed serial data from the test machine and convert the high-speed serial data into the multi-channel input data for transmission; under the condition that the high-speed serial test interface receives channel output data from the second transmission and converts the channel output data into high-speed serial output data, the feedback rate of test results can be provided, and overall, the chip test efficiency is improved. Moreover, less I/O resources of the high-speed serial test interface can be occupied for transmitting test data. And the wiring frequency of test data on the test bus can be improved through the bit width conversion and the frequency conversion of the uplink and downlink speed changer for input data and output data.

In addition, the application can normalize the bit width based on the first speed changer and the second speed changer, and finish chip test based on the fixed frame state machine, the encoder, the decoder and the streaming pipe with the normalized fixed bit width, the encoding and decoding circuit framework at the periphery of the HSSTI is simple, and buffer structures such as FIFO are not needed, so that the occupied area of the chip is reduced.

Based on the method for testing the chip corresponding to fig. 5, the application also provides a chip testing circuit. The chip test circuit includes, in addition to the circuit configuration shown in fig. 4, a plurality of frame header aligners (frame), pass-to-alignment (Bonding) routers, descramblers, scramblers, demultiplexers (DEMUX), and combiners (MUX) as shown in fig. 12. In fig. 12, the multi-channel input data is exemplified by 4 32-bit channel input data. The high-speed serial test interface is exemplified by HSSTI and the test machine is exemplified by ATE.

Wherein a plurality of inputs (s, t, …) of a plurality of frame header aligners are coupled to a plurality of output ports of the high-speed serial test interface, and a plurality of outputs of the plurality of frame header aligners are coupled to a plurality of inputs (v, w, …) of the channel alignment circuit. I.e. the input of each frame header aligner is coupled to one output port of the high-speed serial test interface and the output of each frame header aligner is coupled to one input of the channel aligner. The plurality of outputs of the lane aligner are coupled to the plurality of inputs (c, d, …) of the first transmission. The input end of the descrambler is coupled with the output end e of the first speed changer, and the output end x of the descrambler is coupled with the input end k of the decoder; the output end n of the first flow pipeline is coupled with the input end y of the demultiplexer, and the output end of the demultiplexer is coupled with the test bus; the input end of the combiner is coupled with the test bus, and the output end of the combiner is coupled with the input end r of the second flow pipeline; the input of the scrambler is coupled to the output o of the encoder, and the output a of the scrambler is coupled to the input f of the second transmission.

In some embodiments, each frame header aligner is configured to input data from one channel of the multi-channel input data from one output port of the high-speed serial test interface, and perform frame header alignment on the input data of the one channel and output the aligned data to the channel aligner. As shown in fig. 13, the frame header aligner corresponding to each channel may include a third buffer and a frame header alignment circuit, where the third buffer may be used to buffer one channel input data of the multi-channel input data received from one output RX of the high-speed serial test interface, and the frame header alignment circuit may read a plurality of input data transmitted by the channel from the third buffer, and sequence the plurality of input data according to the sequence of the frame header, and output the sequence.

And the channel aligner is used for aligning the data among the channels of the multi-channel input data received from the frame header alignment circuits and outputting the data to the first transmission. As shown in fig. 13, the lane aligner may include a fourth buffer and a lane alignment circuit, where the fourth buffer may be used to buffer the input data sent by the received lane alignment circuits, and the lane alignment circuit may read the input data corresponding to the lane alignment circuits from the fourth buffer, and perform lane alignment on the input data according to multiple data of a same data packet, so that multiple data transmission rates of the same data packet are consistent, and the input data may arrive at the first transmission at the same time.

It will be appreciated that when the input data of the 4 32-bit wide channels output from the HSSTI is input to the first transmission, the input data packets may be out of order, and thus, the frame may header align the input data of the 4 32-bit wide channels received from the HSSTI to transmit the input data of each of the 4 channels to the channel aligner in the order after the header alignment. The channel aligner performs inter-channel data alignment, which is understood that, because there may be an inconsistency in the speed of transmitting data in each channel, when one packet is split into 4 parts and transmitted in 4 channels, each part of data may not reach the first transmission at the same time when transmitted in different channels, and thus, the channel aligner may reach the first transmission at the same time when small packets after the same packet is split are transmitted in different channels.

The descrambler is used to descramble single channel input data, that is, the input data sent by the ATE is scrambled. Similarly, when single-channel output data is to be output, it is also necessary to scramble the single-channel output data by a scrambler.

A demultiplexer may understand the combinational logic circuit that delivers single channel input data to a designated output. For example, the demultiplexer transmits single-channel input data to a test bus port with a width of 32 bits to be output to a circuit to be tested, or transmits single-channel input data to a test bus port with a width of 64 bits to be output to a circuit to be tested, or transmits single-channel input data to a test bus port with a width of 128 bits to be output to a circuit to be tested, and the like.

The combiner can be understood as feeding back test results transmitted from test bus ports with different bit widths to the second flow pipeline through the combiner.

When the encoder encodes the test result to obtain single-channel output data, the scrambler is used for scrambling the single-channel output data and outputting the single-channel output data to the second transmission.

In addition, when the first transmission receives multi-channel input data transmitted by the frame, the first transmission may transmit a read initiate trigger signal (trigger the read operation) to the second transmission for instructing the second transmission to begin operation. At this point, the HSSTI, header aligner, first transmission and second transmission of fig. 12 form a closed loop system, similar to the far-end parallel loop-back mode of SerDes, becoming a Deterministic system. The remote parallel loop back mode of the SerDes can be understood as a path that parallel data after serial-to-parallel conversion by the SerDes is directly looped back to the TX port of the SerDes without unpacking. A Deterministic system is understood to be a Deterministic system for delaying the input data sent by the RX of a SerDes by a Deterministic overall Deterministic system, the presence of a Deterministic expected data being observable on the TX side of the SerDes. In the closed loop system, RX and TX form a relatively stable phase relation, and an internal self-driving synchronous response mode is formed by an uplink first speed changer (a writing side) and a downlink second speed changer (a reading side), so that the certainty and the uniqueness of a chip test circuit are maintained.

It can be appreciated that the Deterministic system is beneficial to interfacing with the waveform generation language (waveform generation language, WGL/standard test interface language (Standard for extensions to Standard Test Interface Language, STIL) format vector of the conventional test machine, completing the corresponding chip test, reducing the standard requirements on hardware and software of the test machine, and facilitating the large-scale implementation of mass production of the test machine.

The embodiment of the application also provides a chip 14, and the chip 14 can be any chip to be tested.

In some embodiments, as shown in FIG. 14, the chip 14 may include chip test circuitry, circuits to be tested, a test bus, and the like. The chip test circuit is coupled to the test station. The chip test circuit and the internal structure in the chip may be any circuit structure as shown in fig. 3 to 13 of the present application. The circuit to be tested can be a logic module in a chip, the test bus is used for receiving test data from the chip test circuit, the test data is processed by the circuit to be tested and then feeds back a test result, and the test result is returned to the chip test circuit through the test bus.

It should be noted that, the test machine of the present application may be a system level test (System Level Test, SLT) or even other test machines or lead-in boards, besides ATE.

Therefore, the chip provided by the application can multiplex less RX and TX I/O resources of the high-speed serial test interface as test data loading channels, transmit high-speed serial input data, perform serial-parallel conversion and then send the data to the first transmission, and perform multi-channel output on the feedback test result to the high-speed serial test interface through the second transmission, thereby solving the limitation of I/O transmission bandwidth for chip test and avoiding the problem of low test efficiency of chip mass production caused by the increase of logic resources in the chip. In addition, the application does not need to use FIFO to buffer test data, but uses streaming pipe to buffer test data, and compared with FIFO, the application occupies smaller chip area.

It will be appreciated by those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to perform all or part of the functions described above.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another apparatus, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and the parts displayed as units may be one physical unit or a plurality of physical units, may be located in one place, or may be distributed in a plurality of different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be essentially or a part contributing to the prior art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions for causing a device (may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

The chip test circuit is characterized by comprising a high-speed serial test interface, a first transmission and a second transmission, wherein the high-speed serial test interface is interconnected with a test machine table based on a capacitive coupling mode, and data transmitted by the test machine table is received by adopting a differential transmission mode;

the high-speed serial test interface is used for receiving high-speed serial input data sent by the test machine, converting the high-speed serial input data into multi-channel input data and sending the multi-channel input data to the first transmission;

the first transmission is used for normalizing the multi-channel input data into single-channel input data, the single-channel input data is used for testing a circuit to be tested, and the circuit to be tested is coupled with the chip test circuit;

the second transmission is configured to receive single-channel output data from the circuit to be tested, convert the single-channel output data into multi-channel output data, and send the multi-channel output data to the high-speed serial test interface, where the single-channel output data corresponds to the single-channel input data;

the high-speed serial test interface is further configured to convert the multi-channel output data into high-speed serial output data, and send the high-speed serial output data to the test machine.
The test circuit of claim 1, wherein the multi-channel input data is transmitted on M channels, M being an integer greater than 1;

the first transmission is used for receiving the multichannel input data under the 1-frequency multiplication clock domain, and performing bit width conversion on the multichannel input data to obtain the single-channel input data; outputting the single-channel input data under an M frequency multiplication clock domain;

the second transmission is used for receiving the single-channel output data under the M frequency multiplication clock domain, and performing bit width conversion on the single-channel output data to obtain the multi-channel output data; outputting the multichannel output data under a 1-frequency multiplication clock;

the bit width occupied by the single-channel input data and the bit width occupied by the single-channel output data are fixed.
The test circuit of claim 2, wherein the test circuit comprises a plurality of test circuits,

the first transmission comprises a first buffer and a first bit width conversion circuit;

the first buffer is configured to buffer the multi-channel input data received from the high-speed serial test interface in the 1-frequency multiplication clock domain; the first bit width conversion circuit is used for reading the multi-channel input data from the first buffer according to the channel bit width of the single-channel input data to obtain the single-channel input data, and outputting the single-channel input data under the M frequency multiplication clock domain;

The second transmission comprises a second buffer and a second bit width conversion circuit;

the second buffer is configured to buffer the single-channel output data received in the M frequency multiplication clock domain; the second bit width conversion circuit is configured to read the single-channel output data from the second buffer according to a bit width of each channel outputting the multi-channel output data, obtain the multi-channel output data, and output the multi-channel output data in the 1-frequency multiplication clock domain.
A test circuit according to any of claims 1-3, further comprising a decoder, an encoder, a finite state machine FSM, a first stream pipe and a second stream pipe; the first flow conduit and the second flow conduit each comprise a multi-stage storage unit;

an output of the first transmission is coupled to an input of the decoder, the output of the decoder being coupled to an input of the first flow conduit; the output end of the first flow pipeline is coupled with a test bus of the test circuit;

the input end of the second speed changer is coupled with the output end of the encoder, the input end of the encoder is coupled with the output end of the second flow pipeline, and the input end of the second flow pipeline is coupled with the test bus;

The FSM is coupled to the decoder, the encoder, the first flow conduit, and the second flow conduit.
The test circuit of claim 4, wherein the test circuit comprises a plurality of test circuits,

the decoder is used for decoding the single-channel input data, sending decoded test data to the first flow pipeline and sending decoded instructions to the FSM;

the FSM to determine an operating state of the encoder, the first flow pipe, and the second flow pipe according to the decoded instructions;

the first flow conduit for transmitting the test data to the test bus in accordance with the operating state of the first flow conduit determined by the FSM;

the second flow pipeline is used for receiving a test result returned through the test bus according to the operation state of the second flow pipeline determined by the FSM and sending the test result to the encoder;

and the encoder is used for encoding the test result according to the operation state of the encoder determined by the FSM to obtain the single-channel output data and transmitting the single-channel output data to the second transmission.
The test circuit of claim 5, further comprising a gating circuit coupled to each of the plurality of levels of memory cells; the first flow pipeline comprises a first-stage storage unit and a second-stage storage unit;

the first-stage storage unit is used for caching the test data received from the decoder;

the first-stage storage unit is further configured to send the test data stored in the first-stage storage unit to the second-stage storage unit when receiving a clock signal sent by a gate control circuit coupled to the first-stage storage unit;

the second-level storage unit is used for caching the test data received from the first-level storage unit.
The test circuit of any one of claims 1-6, wherein the test circuit further comprises a plurality of frame header aligners and channel aligners; an input of each frame header aligner is coupled to one output port of the high-speed serial test interface, an output of each frame header aligner is coupled to one input of the lane aligner, and a plurality of outputs of the lane aligner are coupled to a plurality of input ports of the first transmission;

Each frame head aligner is configured to receive one channel input data of the multi-channel input data from one output port of the high-speed serial test interface, perform frame head alignment on the input data of the one channel, and output the aligned data to the channel aligner;

the channel aligner is configured to perform inter-channel data alignment on the multi-channel input data received from the plurality of frame header aligners, and output the multi-channel input data to the first transmission.
The test circuit of claim 7, wherein the test circuit comprises a plurality of test circuits,

each frame head alignment device comprises a third buffer and a frame head alignment circuit;

the third buffer is configured to buffer one channel input data of the multi-channel input data received from one output port of the high-speed serial test interface; the frame head alignment circuit is used for reading the one channel input data from the third buffer, sequencing the one channel input data according to frame heads and outputting the one channel input data to the channel alignment circuit;

the channel aligner comprises a fourth buffer and a channel alignment circuit;

the fourth buffer is configured to buffer a plurality of channel input data sent from the plurality of channel alignment circuits; the channel alignment circuit is configured to read the plurality of channel input data from the fourth buffer, perform inter-channel alignment on the plurality of channel input data, and output the aligned data to the first transmission.
A method of testing a chip, the chip including a high-speed serial test interface, the high-speed serial test interface being interconnected with a test station based on a capacitive coupling manner and receiving data transmitted by the test station using a differential transmission manner, the method comprising:

the chip receives high-speed serial input data sent by the test machine through the high-speed serial test interface and converts the high-speed serial input data into multi-channel input data;

the chip normalizes the multi-channel input data into single-channel input data, wherein the single-channel input data is used for testing a circuit to be tested in the chip;

the chip converts single-channel output data received from the circuit to be tested into multi-channel output data, wherein the single-channel output data corresponds to the single-channel input data;

the chip converts the multichannel output data into high-speed serial output data through the high-speed serial test interface and sends the high-speed serial output data to the test machine.
The method of claim 9, wherein the multi-channel input data is transmitted on M channels, M being an integer greater than 1;

The chip normalizing the multi-channel input data into single-channel input data comprises: the chip performs bit width conversion on the multi-channel input data transmitted under the 1 frequency multiplication clock domain to obtain the single-channel input data transmitted under the M frequency multiplication clock domain;

the chip converting the single-channel output data received from the circuit to be tested into multi-channel output data includes: the chip performs bit width conversion on the single-channel output data received under the M frequency multiplication clock domain to obtain the multi-channel output data transmitted under the 1 frequency multiplication clock domain;

the bit width occupied by the single-channel input data and the bit width occupied by the single-channel output data are fixed.
The method of claim 10, wherein the step of determining the position of the first electrode is performed,

the chip normalizing the multi-channel input data into single-channel input data comprises:

the chip caches the multichannel input data received from the high-speed serial test interface under the 1-frequency multiplication clock domain; the chip control reads the multi-channel input data from a first buffer according to the channel bit width of the single-channel input data to obtain the single-channel input data, and outputs the single-channel input data in the M frequency multiplication clock domain;

The chip converting the single-channel output data received from the circuit to be tested into multi-channel output data includes:

the chip caches the single-channel output data received under the M frequency multiplication clock domain; and the chip reads the single-channel output data from the second buffer according to the bit width of each channel for outputting the multi-channel output data to obtain the multi-channel output data, and outputs the multi-channel output data under the 1-frequency multiplication clock domain.
The method of any of claims 9-11, wherein prior to the chip converting single channel output data received from the circuit to be tested to multi-channel output data, the method further comprises:

the chip decodes the single-channel input data to obtain decoded instructions and test data;

the chip caches the test data through a multi-stage storage unit and outputs the cached test data to a test bus in the chip, and the test data is transmitted to the circuit to be tested through the test bus;

and the chip caches the test result returned from the circuit to be tested through a multi-stage storage unit according to the decoded instruction, and encodes the cached and output test result to obtain the single-channel output data.
The method of claim 12, wherein the multi-level memory cells comprise a first level memory cell and a second level memory cell; the chip outputs the test data to the test bus in the chip after the test data is cached by the multi-stage memory unit comprises:

controlling the first-level storage unit to cache the test data received from the decoder;

controlling the first-stage storage unit to send the test data stored in the first-stage storage unit to the second-stage storage unit when receiving a clock signal sent by a gate control circuit coupled with the first-stage storage unit;

and controlling the second-level storage list to cache the test data received from the first-level storage unit.
The method of any of claims 9-13, wherein prior to the chip normalizing the multi-channel input data to single-channel input data, the method further comprises:

the chip performs frame header alignment of data on the input data of each channel in the multi-channel input data;

and the chip performs inter-channel data alignment on the multi-channel input data with the frame heads aligned.
The method of claim 14, wherein the chip performing frame header alignment of data on the input data for each channel of the multi-channel input data comprises:

the chip controls a third buffer to buffer one channel input data in the multi-channel input data received from one output port of the high-speed serial test interface; the chip controls the frame head alignment circuit to read the one channel input data from the third buffer, and outputs the one channel input data to the channel alignment circuit after sequencing the one channel input data according to frame heads;

the chip performing inter-channel data alignment on the multi-channel input data with the aligned frame heads comprises the following steps:

the chip controls a fourth buffer to buffer a plurality of channel input data sent from the plurality of channel alignment circuits; and the chip control channel alignment circuit reads the plurality of channel input data from the fourth buffer, performs inter-channel alignment on the plurality of channel input data and outputs the data to the first transmission.
A communication device comprising at least one processor coupled to a memory, the at least one processor for reading and executing a program stored in the memory to cause the communication device to perform the method of any of the preceding claims 9-15.
A computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the method of any of the preceding claims 9-15.