CN109426636B

CN109426636B - Method and device for transmitting high-bit-width data between FPGA (field programmable Gate array) chips

Info

Publication number: CN109426636B
Application number: CN201710725378.1A
Authority: CN
Inventors: 冯晓海; 盛武斌; 徐宏毅
Original assignee: Sanechips Technology Co Ltd
Current assignee: Sanechips Technology Co Ltd
Priority date: 2017-08-22
Filing date: 2017-08-22
Publication date: 2021-10-01
Anticipated expiration: 2037-08-22
Also published as: CN109426636A

Abstract

The document discloses a method and a device for transmitting high-bit-width data between FPGA (field programmable gate array) chips, which comprise the following steps: packaging parallel data to be sent in a first FPGA and control code words to form a data subframe and writing the data subframe into a TX _ RAM array, wherein the number of TX _ RAM lines in the TX _ RAM array is matched with the line rate of the current SERDES and the data bit width of a PCS interface; outputting the data subframes in the TX _ RAM array in a TDM mode in a time-sharing mode according to a row sequence in a column unit; replacing a control code word in the data output in the row sequence with a BIP check code word of a previous subframe through BIP processing; and sending the data processed by the BIP to an SERDES (serial-parallel data encryption standard), so that the data after the BIP processing is sent to a second FPGA (field programmable gate array) after the SERDES is subjected to parallel-serial conversion. The present application is capable of accommodating multiple SERDES line rates, at least, through the same set of framing devices.

Description

Method and device for transmitting high-bit-width data between FPGA (field programmable Gate array) chips

Technical Field

The invention relates to the technical Field of computers, in particular to a method and a device for transmitting high-bit-width data between FPGA (Field Programmable Gate Array) chips.

Background

In recent years, the chip industry is rapidly developed, and more manufacturers use an FPGA prototype system to verify the functions of chips in order to improve the success rate of chip one-time chip flow and accelerate the maturity of matched software. The high bit width data transmission between the FPGA chips is an important problem of a prototype system.

The transmission mode of the high-bit-width data between the FPGA chips comprises parallel transmission and serial transmission. The parallel transmission realizes the increase of data bandwidth by improving the data bit width, and cannot meet the transmission requirement of hundreds of thousands of bits of parallel data among FPGA chips in a chip prototype system. A common method in the related art is to use a SERDES (SERializer/DESerializer) to perform serialization transmission, and convert parallel data into a single-bit differential signal for transmission, which not only can provide a higher data bandwidth, but also has high transmission stability.

The existing prototype system transmits high-bit-width data between FPGA (field programmable gate array) chips through an SERDES (serial advanced encryption standard), some protocols are complex, such as an Ethernet protocol, peripheral component interconnect express (PCIe) and the like, only support an application scene with a fixed SERDES rate, and have limited use and limitation in adaptation to the scene; some of the devices have poor universality, different framing devices are needed for application scenes with different SERDES rates, and the cost is high. Therefore, in the related art, it is an urgent need to solve the technical problem that either the supported SERDES line rate is single or different framing devices are required under different SERDES rates.

Disclosure of Invention

In order to solve the above technical problem, embodiments of the present invention provide a method and an apparatus for transmitting high-bit-width data between FPGA slices, which can at least apply to multiple SERDES line rates through the same group of framing apparatuses.

The present application provides:

a method for transmitting high-bit-width data between FPGA chips comprises the following steps:

packaging parallel data to be sent in a first FPGA and control code words to form a data subframe and writing the data subframe into a TX _ RAM array of a random access memory of a transmitting terminal, wherein the number of TX _ RAM lines in the TX _ RAM array is matched with the line rate of a current SERDES and the data bit width of a PCS interface;

outputting the data subframes in the TX _ RAM array in a time-sharing and row-sequential manner in a time-division multiplexing TDM manner by using columns as a unit;

replacing the control code word in the data output in the row sequence with the BIP check code word of the previous subframe through bit interleaving parity check (BIP) processing;

and sending the data processed by the BIP to an SERDES (serial-parallel data encryption standard), so that the data after the BIP processing is sent to a second FPGA (field programmable gate array) after the SERDES is subjected to parallel-serial conversion.

And the data bit width of each TX _ RAM in the TX _ RAM array is matched with the data bit width of a physical coding sublayer PCS interface of the SERDES.

Before the parallel data to be sent in the first FPGA and the control code word are packed to form a data subframe and written into the TX _ RAM array, the method further includes: and determining the number of TX _ RAM rows in the TX _ RAM array according to the line rate of the current SERDES, the data bit width of the PCS interface and the data rate to be transmitted, and forming the TX _ RAM array according to the determined number of the TX _ RAM rows.

Before sending the data after the BIP processing to the SERDES, the method further comprises the following steps: and scrambling the data processed by the BIP.

writing data from an SERDES PCS interface into a receiving end random access memory (RX _ RAM) array of a second FPGA, wherein the number of RX _ RAM rows in the RX _ RAM array is matched with the line rate of the SERDES and the data bit width of a PCS interface;

and reading data from the RX _ RAM array of the second piece of FPGA according to columns, and deleting the control code words or check code words of the lowest bytes in the data.

Before writing the data from the SERDES PCS interface into the RX _ RAM array of the second FPGA, the method further includes: and performing descrambling processing on the data from the SERDES PCS interface.

When the data from the SERDES PCS interface is written into the RX _ RAM array of the second FPGA, the method further includes: and carrying out BIP check on the data from the SERDES PCS interface, and comparing the data with the BIP check code word sent along the channel to monitor whether errors occur in the transmission process.

Before writing the data from the SERDES PCS interface into the RX _ RAM array of the second FPGA, the method further includes: and determining the number of RX _ RAM rows in the RX _ RAM array according to the line rate of the current SERDES, the data bit width of the PCS interface and the data rate to be transmitted, and forming the RX _ RAM array according to the determined number of RX _ RAM rows.

Before writing the data from the SERDES PCS interface into the receiving random access memory RX _ RAM array of the second FPGA, the method further includes: judging whether a receiving link enters a synchronous state according to the data output by the PCS interface and a K code indicating signal, and receiving the data from the SERDES PCS interface after the receiving link enters the synchronous state; and carrying out byte alignment adjustment on the data from the SERDES PCS interface, and adjusting the K code to the lowest byte.

An FPGA supporting high-bit-width data transfers, comprising:

the data frame generating module comprises a transmitting terminal random access memory TX _ RAM array, wherein the number of TX _ RAM rows in the TX _ RAM array is matched with the line rate of the current SERDES and the data bit width of a PCS interface; the system comprises a TX _ RAM array, a time division multiplexing TDM mode, a parallel data transmission module, a time division multiplexing TDM mode and a control code word, wherein the TX _ RAM array is used for transmitting parallel data and control code words to be transmitted;

and the bit interleaving parity check BIP generation module is used for replacing a control code word in the data output by the data frame generation module according to the row sequence with a BIP check code word of the previous subframe through BIP processing, and sending the data processed by the BI P to an SERDES (serial-parallel conversion field programmable gate array) so as to be sent to other FPGAs after the SERDES is subjected to parallel-serial conversion.

Wherein, still include: and the scrambling module is used for scrambling the data processed by the BIP and sending the scrambled data to the SERDES so that the SERDES can be sent to other FPGAs after parallel-serial conversion.

An FPGA supporting high-bit-width data transfers, comprising: and the data frame analysis module comprises a receiving end random access memory (RX _ RAM) array, wherein the number of RX _ RAM rows in the RX _ RAM array is matched with the line rate of the SERDES and the data bit width of the PCS interface, and the RX _ RAM array is used for writing data from the SERDES PCS interface into the RX _ RAM array, reading the data from the RX _ RAM array of the second FPGA according to columns, deleting the control code words or check code words of the lowest bytes in the data and outputting the control code words or the check code words.

Wherein, still include: and the descrambling module is used for descrambling the data from the SERDES PCS interface and then sending the descrambled data to the data frame analysis module.

Wherein, still include: and the BIP analysis module is used for carrying out BIP check on the data from the SERDES PCS interface and comparing the data with the BIP check code word sent along the channel so as to monitor whether errors occur in the transmission process.

Wherein, still include: the K code synchronization module is used for judging whether a receiving link enters a synchronization state according to the data output by the PCS interface and a K code indication signal and receiving the data from the SERDES PCS interface after the receiving link enters the synchronization state; and the K code alignment module is used for carrying out byte alignment adjustment on the data from the SERDES PCS interface, adjusting the K code to the lowest byte, and outputting the adjusted data to the data frame analysis module or the descrambling module.

An apparatus for high bit width data transmission between FPGA chips, comprising: the device comprises a first FPGA, an SERDES and a second FPGA, wherein the first FPGA and the second FPGA are respectively connected with a physical coding sublayer PCS interface of the SERDES;

the first FPGA comprises a transmitting-end random access memory TX _ RAM array, the number of TX _ RAM rows in the TX _ RAM array is matched with the line rate of the SERDES and the data bit width of the PCS interface, and the first FPGA is configured to execute an FPGA inter-chip high-bit-width data transmission program to execute the operation of the method;

the second FPGA comprises a receiving end random access memory RX _ RAM array, wherein the number of RX _ RAM lines in the RX _ RAM array is matched with the line rate of the SERDES and the data bit width of the PCS interface, and the second FPGA is configured to execute an FPGA inter-chip high-bit-width data transmission program to execute the operation of the method;

and the SERDES is used for performing parallel-serial conversion on the data from the first FPGA and outputting the data to the second FPGA.

The application can at least obtain the following technical effects:

on one hand, a data subframe is written into a TX _ RAM array with the row number matched with the line rate of the current SERDES and the data bit width of a PCS interface, data are output from the TX _ RAM array in a time division multiplexing TDM mode in a row unit in a time division multiplexing TDM mode, automatic adjustment of a data frame structure is achieved by adjusting the row number of the TX _ RAM in the TX _ RAM array, different framing devices do not need to be configured for different SERDES line rates, cost is low, and the method and the device can be suitable for application scenarios of FPGA inter-chip data transmission under various SERDES rates.

On the other hand, the data to be sent and the control code word are adopted for framing, so that compared with the related technology, the framing difficulty is further reduced, and the method and the device are applicable to various application scenes of data transmission among FPGA chips and have higher universality.

In another aspect, the control code word in the data output in the row sequence is replaced by the BIP check code word of the previous subframe by adopting BIP processing, so that the online check function of a transmission link is provided, the reliability of data transmission is improved, the method is suitable for application scenes of data transmission among various FPGA chips, and the universality is higher.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

Fig. 1 is a schematic flowchart of a method for transmitting high-bit-width data between FPGA chips according to an embodiment;

FIG. 2 is an exemplary diagram of a data frame structure of the present application;

fig. 3 is a schematic structural diagram of an FPGA supporting high bit width data transmission according to a first embodiment;

fig. 4 is a schematic flow chart of a method for transmitting high-bit-width data between FPGA chips in the second embodiment;

fig. 5 is a schematic structural diagram of an FPGA supporting high bit width data transmission according to the second embodiment;

fig. 6 is a schematic structural diagram of a device for transmitting high-bit-width data between FPGA chips in the third embodiment;

fig. 7 is a schematic structural diagram of an apparatus for transmitting high-bit-width data between FPGA slices according to a third embodiment;

fig. 8 is a schematic diagram of an exemplary execution flow of inter-chip high-bit-width data transmission of an FPGA according to the third embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.

Aiming at the technical problems that in the related art, the supported SERDES line rate is single or different framing devices are needed under different SERDES rates, the following technical scheme is provided in the application. In the application, the high-bit-width data transmission between the FPGA chips is realized by using the RAM array (such as a TX _ RAM array and an RX _ RAM array) with the RAM row number matched with the line rate of the current SERDES and the data bit width of the PCS interface, so that the cost is low, and the method and the device are suitable for application scenes of the data transmission between the FPGA chips under various SERDES rates.

The technical solution of the present application is explained in detail below.

Example one

A method for transmitting high-bit-width data between FPGA slices, as shown in fig. 1, may include:

step 101, packing parallel data to be sent in a first FPGA and a control Code word to form a data subframe and writing the data subframe into a random access memory (TX _ RAM) array of a transmitting terminal, wherein the number of rows of the TX _ RAM in the TX _ RAM array is matched with the line rate of a current SERDES and the bit width of Physical Coding Sublayer (PCS) interface data;

step 102, outputting the data subframes in the TX _ RAM array in a Time Division Multiplexing (TDM) mode by using columns as a unit and in a row sequence;

103, replacing a control code word in the data output in the row sequence with a BIP check code word of a previous subframe through Bit Interleaved Parity (BIP) processing;

and 104, sending the data processed by the BIP to an SERDES (serial-parallel data encryption standard), so that the data after the BIP processing is sent to a second FPGA (field programmable gate array) after the SERDES is subjected to parallel-serial conversion.

In this embodiment, a data subframe is written into a TX _ RAM array in which the number of rows of the TX _ RAM is matched with the line rate of the current SERDES and the data bit width of a PCS interface, data is output from the TX _ RAM array in a time division multiplexing TDM manner by columns in a row sequence, automatic adjustment of a data frame structure and data capacity is realized by adjusting the number of rows of the TX _ RAM in the TX _ RAM array, different framing devices do not need to be configured for different line rates of the SERDES, and the method is not only low in cost, but also can be suitable for application scenarios of FPGA inter-chip data transmission at various SERDES rates.

In this embodiment, data to be transmitted and a control codeword (for example, a K28.5 codeword) are used for framing, so that compared with the related art, the framing difficulty is further reduced in this embodiment, and thus the method is applicable to various application scenarios of inter-chip data transmission of an FPGA, and has higher universality.

In this embodiment, the control codeword in the data output in the row sequence is replaced with the BIP check codeword of the previous subframe, so that the K-code subframe is converted into a non-K-code subframe, so as to perform subsequent processing. Wherein the data subframes are divided into two types: k-code subframes and non-K-code subframes.

In this embodiment, the BIP processing is further adopted to replace the control code word in the data output in the row sequence with the BIP check code word of the previous subframe, so that the online check function of the transmission link is provided, the reliability of data transmission is improved, and the method is applicable to various application scenarios of FPGA inter-chip data transmission and has higher universality.

In practical application, the faster the chip module running clock integrated in the FPGA prototype system is, the higher the platform utilization efficiency is, but the lower the bit width of data carried by the SERDES during the FPGA inter-chip transmission is, the more the number of SERDES required in the system is. The SERDES line rate in the FPGA is XGbps, an 8B/10B coding mode is used, the data bit width of a PCS interface is L bit, the data rate to be transmitted is YGbps, the number N of TX _ RAM lines of a TX _ RAM array is (X0.8/Y)/L, wherein N is an integer greater than 0, and a SERDES channel can bear the data bit width W equal to N L-8, so that the embodiment can meet the requirements of any type of data transmission such as interruption, reset and the like under the working frequency of a module to be detected.

In this embodiment, a data bit width of each TX _ RAM in the TX _ RAM array matches a data bit width of a PCS interface of a physical coding sublayer of the SERDES.

In this embodiment, the length of the data subframe is N × L bits, N is the TX _ RAM row number of the TX _ RAM array, and L is the PCS interface data bit width of the SERDES. In this way, by associating the length of the data subframe with the number of TX _ RAM rows of the TX _ RAM array, the data frame structure can be automatically adjusted as the number of TX _ RAM rows of the TX _ RAM array changes, thereby being adaptable to application scenarios of FPGA inter-chip data transmission at various SERDES rates.

To accommodate various SERDES line rates, the data frame used by the method of this embodiment includes three types of data: k code (e.g., K28.5 code word), BIP check code word, and data to be transmitted. In one implementation, as shown in fig. 2, the data frame used in the method of this embodiment may include C _ K _ DIS (the parameter is an integer greater than 0) data subframes, at least 1K-code subframe, and several BIP subframes. When C _ K _ DIS is 1, the data frame includes only one K-code subframe. Each data subframe consists of N x L bits, N is the TX _ RAM line number of the TX _ RAM array, L is the PCS interface data bit width of the SERDES, and the first byte in the data subframe is a K code or a BIP check code word.

In this embodiment, the TX _ RAM array may be implemented in various ways. In one implementation manner, before the packing the parallel data to be sent in the first FPGA and the control codeword into a data subframe and writing the data subframe into the TX _ RAM array, the method may further include: and determining the number of TX _ RAM rows in the TX _ RAM array according to the line rate of the current SERDES, the data bit width of the PCS interface and the data rate to be transmitted, and forming the TX _ RAM array according to the determined number of the TX _ RAM rows.

In this embodiment, before sending the data after the BIP processing to the SERDES, the method may further include: and scrambling the data processed by the BIP. Thus, by increasing the scrambling function of the data, the reliability of the transmission link can be improved.

Correspondingly, the present embodiment further provides an FPGA supporting high bit width data transmission, as shown in fig. 3, which may include:

a data frame generating module 31, including a TX _ RAM array of a random access memory at a transmitting end, where the number of rows of the TX _ RAM in the TX _ RAM array matches the line rate of the current SERDES and the data bit width of the PCS interface; the system comprises a TX _ RAM array, a time division multiplexing TDM mode, a parallel data transmission module, a time division multiplexing TDM mode and a control code word, wherein the TX _ RAM array is used for transmitting parallel data and control code words to be transmitted;

and the BIP generation module 32 is configured to replace a control codeword in the data output by the data frame generation module in the row sequence with a BIP check codeword of a previous subframe through BIP processing, and send the data after the BI P processing to the SERDES, so that the SERDES is sent to other FPGAs after parallel-to-serial conversion.

In one implementation, the FPGA may further include: and a scrambling module 33, configured to perform scrambling processing on the data subjected to the BIP processing, and send the data subjected to the scrambling processing to the SERDES, so that the SERDES is sent to other FPGAs after parallel-to-serial conversion.

The FPGA in this embodiment can implement all details of the method for transmitting high-bit-width data between FPGA chips in this embodiment, and reference may be made to the above description of the method, which is not described again.

In practical application, the FPGA supporting high bit width data transmission in this embodiment may be connected to a PCS logic side interface of the SERDES hard IP, and the processed data is sent to the SERDES through the PCS logic side interface.

In practical application, each module in the FPGA supporting high bit width data transmission in this embodiment may be software, hardware, or a combination of the software and the hardware, and is responsible for implementing the following functions:

the data frame generating module 31 includes the TX _ RAM array, and is mainly responsible for implementing merging of data to be transmitted and control code words, parallel-to-serial conversion of parallel data to be transmitted, and clock crossing and conversion functions, and converting parallel data with high bit width to be transmitted into a data frame matched with the data bit width of the PCS interface. By adjusting the number of TX _ RAM rows of the TX _ RAM array, a variety of SERDES line rates can be supported.

The scrambling module 33 is responsible for scrambling data according to a given seed by using the K code as a data frame header, completing pseudo-randomization of data to be transmitted, reducing occurrence of continuous '0' and '1', dispersing a power spectrum, and the like, thereby enhancing reliability of data transmission.

The BIP generation module can be responsible for generating the BIP check code words of the data subframes and selectively replacing the control code words according to the types of the data subframes, so that the on-line error monitoring function of the FPGA is realized, and the reliability of data transmission is improved.

It should be noted that, the data frame generating module 31 performs parallel-to-serial conversion and clock domain crossing conversion on the polarity of the data to be transmitted, so as to match with the PCS interface; the SERDES is responsible for parallel-to-serial conversion and clock domain crossing conversion of PCS interface data, and aims to match with a SERDES hardware transmission line.

Example two

A method for transmitting high-bit-width data between FPGA slices, as shown in fig. 4, may include:

step 401, writing data from the SERDES PCS interface into a receiving end random access memory (RX _ RAM) array of a second FPGA, where the number of RX _ RAM rows in the RX _ RAM array matches the line rate of the SERDES and the data bit width of the PCS interface;

and step 402, reading data from the RX _ RAM array of the second FPGA according to columns, deleting the control code word or check code word of the lowest byte in the data, and outputting the control code word or check code word.

In this embodiment, a data subframe is written into an RX _ RAM array in which the number of rows of the RX _ RAM is matched with the line rate of the current SERDES and the data bit width of a PCS interface, and data is output from the RX _ RAM array in units of columns, so that automatic adjustment of a data frame structure and data capacity is realized by adjusting the number of rows of the TX _ RAM in the RX _ RAM array, and different framing devices do not need to be configured for different SERDES line rates, which is not only low in cost, but also applicable to application scenarios of FPGA inter-chip data transmission at various SERDES rates.

In one implementation, before writing the data from the SERDES PCS interface into the RX _ RAM array of the second FPGA, the method may further include: and performing descrambling processing on the data from the SERDES PCS interface. Therefore, the reliability of the transmission link can be improved by increasing the descrambling function of the data.

In this embodiment, when writing the data from the SERDES PCS interface into the RX _ RAM array of the second FPGA, the method may further include: and carrying out BIP check on the data from the SERDES PCS interface, and comparing the data with the BIP check code word sent along the channel to monitor whether errors occur in the transmission process. Therefore, the BIP provides the online checking function of the transmission link, improves the reliability of data transmission, is suitable for application scenes of data transmission among various FPGA chips, and has higher universality.

In this embodiment, there may be various ways to implement the RX _ RAM array. In one implementation, before writing the data from the SERDES PCS interface into the RX _ RAM array of the second FPGA, the method may further include: and determining the number of RX _ RAM rows in the RX _ RAM array according to the line rate of the current SERDES, the data bit width of the PCS interface and the data rate to be transmitted, and forming the RX _ RAM array according to the determined number of RX _ RAM rows.

In one implementation, before writing the data from the SERDES PCS interface into the RX _ RAM array of the receiving side random access memory of the second FPGA, the method may further include: judging whether a receiving link enters a synchronous state according to the data output by the PCS interface and a K code indicating signal, and receiving the data from the SERDES PCS interface after the receiving link enters the synchronous state; and carrying out byte alignment adjustment on the data from the SERDES PCS interface, and adjusting the K code to the lowest byte.

To accommodate a variety of SERDES line rates, the data frames used in the method described in this embodiment include three types of data: k code (e.g., K28.5 codeword), BIP check codeword, data to be transmitted. In one implementation, as shown in fig. 2, each data frame may include C _ K _ DIS (the parameter is an integer greater than 0) data subframes, at least 1K-code subframe, and several BIP subframes. When C _ K _ DIS is 1, the data frame includes only one K-code subframe. Each data subframe consists of N × L bits, N is the RX _ RAM row number of the RX _ RAM array, L is the PCS interface data bit width of the SERDES, and the first byte in the data subframe is a K code or a BIP check code word.

Correspondingly, the present embodiment further provides an FPGA supporting high bit width data transmission, as shown in fig. 5, which may include:

and the data frame parsing module 51 includes a receiving end random access memory RX _ RAM array, where the number of RX _ RAM rows in the RX _ RAM array matches with the line rate of the SERDES and the data bit width of the PCS interface, and is configured to write data from the SERDES PCS interface into the RX _ RAM array, read data from the RX _ RAM array of the second FPGA according to columns, and delete a control codeword or a check codeword of a lowest byte in the data, and then output the data.

In an implementation manner, the FPGA supporting high bit width data transmission may further include: the BIP parsing module 52 is configured to perform BIP check on the data from the SERDES PCS interface, and compare the BIP check code with the BIP check code sent along the channel to monitor whether an error occurs in the transmission process.

In an implementation manner, the FPGA supporting high bit width data transmission may further include: and the descrambling module 53 is configured to descramble the data from the SERDES PCS interface and send the descrambled data to the data frame parsing module.

In an implementation manner, the FPGA supporting high bit width data transmission may further include:

a K code synchronization module 54, configured to determine whether a receiving link enters a synchronization state according to the data output by the PCS interface and a K code indication signal, and receive the data from the SERDES PCS interface after entering the synchronization state;

the K code alignment module 55 is configured to perform byte alignment adjustment on the data from the SERDES PCS interface, adjust the K code to the lowest byte, and output the adjusted data to the data frame parsing module 51 or the descrambling module 53.

In practical application, the FPGA supporting high bit width data transmission in this embodiment may be connected to a PCS logic side interface of the SERDES hard IP, and data after SERDES parallel-to-serial conversion is passed through the PCS logic side interface.

the data frame analysis module 51 includes the RX _ RAM array, and is mainly responsible for controlling read and write addresses through the RX _ RAM array, implementing a function of decoding a frame format of received data, deleting a control codeword (for example, K28.5), a BIP check codeword, and the like in a subframe, and outputting data obtained by analysis, and the data frame analysis module 51 can support different SERDES line rate application scenarios by adjusting the number of RX _ RAM lines in the RX _ RAM array.

The BIP check parsing module 52 is mainly responsible for implementing the functions of calculating a BIP check codeword of a received subframe and determining a BIP check result, so as to implement BIP check of data (e.g., descrambled data) to monitor whether an error occurs in a transmission process.

Descrambling module 53 may be responsible for parsing out the received data by de-pseudorandom processing of the received data. In practice, the descrambling module 53 is present in pairs with the scrambling module 33. Thus, the scrambling function is added, the '0' and '1' sequences which continuously appear in the transmission can be reduced, the power spectrum is dispersed, and the reliability of data transmission is enhanced.

The K code synchronization module 54 is mainly responsible for implementing a synchronization function of a receiving end link, and implements receiving link state synchronization detection through a K code detection state machine;

the K code alignment module 55 is mainly responsible for implementing the function of adjusting the K code position to the lowest byte (for example, 32 bits).

EXAMPLE III

As shown in fig. 6, an apparatus for transmitting high-bit-width data between FPGA slices is provided, which includes: the device comprises a first FPGA 61, an SERDES 62 and a second FPGA 63, wherein the first FPGA 61 and the second FPGA 63 are respectively connected with a physical coding sublayer PCS interface of the SERDES 62;

the first FPGA 61 comprises a TX _ RAM array, the number of rows of TX _ RAM in the TX _ RAM array matches with the line rate of the SERDES and the data bit width of the PCS interface, and is configured to execute an FPGA inter-chip high bit width data transmission program to execute the operations of the method of the first embodiment;

the second FPGA 63 comprises a receiving-end random access memory RX _ RAM array, wherein the number of RX _ RAM rows in the RX _ RAM array matches with the line rate of the SERDES and the data bit width of the PCS interface, and is configured to execute an FPGA inter-chip high-bit-width data transmission program to execute the operations of the method according to the second embodiment;

the SERDES 62 may be configured to perform parallel-to-serial conversion on the data from the first FPGA 61 and output the data to the second FPGA 63.

In one implementation, the first FPGA 61 is connected to a Physical Code Sublayer (PCS) logical side interface of the SERDES 62 hard IP, and data is sent to the SERDES 62 through the PCS logical side interface to perform parallel-to-serial conversion. The second FPGA 63 is connected with a PCS logic side interface of the SERDES 62 hard IP, and the PCS logic side interface of the SERDES 62 hard IP outputs data after parallel-serial conversion to the second FPGA 63.

Fig. 7 is a schematic diagram of an exemplary structure of an apparatus for transmitting high-bit-width data between FPGA slices in this embodiment. The first FPGA 61 includes a data frame generating module 31, a BIP check generating module 32 and a scrambling module 33, and the second FPGA 63 may include a data frame parsing module 51, a BIP check parsing module 52, a descrambling module 53, a K code synchronizing module 54 and a K code aligning module 55.

The data frame generating module 31 may be responsible for implementing functions of data to be transmitted and K code group frames, data cross-clock and conversion, and sub-frame time-sharing output;

the BIP check generating module 32 may be responsible for calculating a BIP check codeword according to the input data, and updating a control codeword of a subframe according to a frame structure.

The scrambling module 33 may be responsible for scrambling data according to a given seed by using the K code as a header of the data frame, so as to enhance reliability of data transmission.

The data frame parsing module 51 is mainly composed of RX _ RAM, and can be responsible for implementing data cross-clock and conversion, serial-parallel conversion, and control codeword or BIP codeword deletion functions.

The BIP check analysis module 52 may be responsible for performing BIP check on the descrambled data, comparing the BIP check code with the BIP check code sent by the first FPGA along the channel, and monitoring whether an error occurs in the transmission process.

The descrambling module 53 may be responsible for descrambling the data output by the K code alignment module.

The K code synchronization module 54 may be responsible for determining whether the receiving link enters a synchronization state according to the data output by the PCS interface and the K code indication signal, and outputting PCS output data after entering the synchronization state.

The K code alignment module 55 may be responsible for adjusting the data output from the PCS interface to the lowest byte.

Correspondingly, the embodiment also provides a method for transmitting high-bit-width data between FPGA slices, which may include:

firstly, packaging parallel data to be sent and control code words in a first FPGA to form a data subframe, and writing the data subframe into a TX _ RAM array;

secondly, outputting data in a TX _ RAM array in a first FPGA in a time-sharing and row-sequential manner in a TDM manner by taking the data as a unit;

thirdly, aiming at the data output in the line sequence, replacing the control code word in the non-K code subframe of the data by the BIP check code word of the previous subframe through BIP processing, and performing scrambling processing;

fourthly, the first FPGA outputs the data after scrambling to an SERDES, and the SERDES performs parallel-serial conversion and then transmits the data to the second FPGA;

and fifthly, the second FPGA receives data from the SERDES, the data are sequentially written into the RX _ RAM array after descrambling, BIP check is carried out simultaneously, and the BIP check code is compared with the BIP check code sent along the channel to monitor whether errors occur in the transmission process.

And sixthly, reading data from the RX _ RAM array of the second FPGA according to the columns, deleting the control code words or check code words of the lowest bytes in the data, and outputting the control code words or check code words to other modules of the second FPGA.

In one implementation, the BIP check is implemented by completing the data check of the previous subframe and the calculation of the data check code of the current subframe.

The following describes a specific implementation process of the present embodiment in detail.

The process of executing the inter-FPGA chip high bit width data transmission by the inter-FPGA chip high bit width data transmission apparatus in this embodiment may be implemented by using a flow shown in fig. 8. It should be noted that fig. 8 is only an exemplary implementation manner, and details or an execution sequence of steps in the implementation manner may be adjusted according to needs in practical applications, which is not limited herein.

As shown in fig. 8, the execution flow of the FPGA inter-chip high bit width data transmission may include:

step 801, a first FPGA combines parallel data to be transmitted and a control codeword (for example, a K28.5 codeword) to form a data subframe, where the control codeword is located at a lowest byte;

step 802, writing the data subframes into a TX _ RAM array, and outputting the data subframes in the TX _ RAM array in a TDM manner by column unit according to row number (namely, the row number of the TX _ RAM in the TX _ RAM array) in sequence from the first row in time division manner under an SERDES PCS interface clock domain;

step 803, performing BIP processing on the data output by the TX _ RAM array, and replacing a non-first subframe control code word of each data subframe in the data output by the TX _ RAM array with a BIP check code word of a previous subframe;

in this example, the data subframes output by the TX _ RAM are all K-code subframes, and after the BIP processing, the non-first subframe in the data frame is changed into the non-K-code subframe, that is, the control word in the K-code subframe is replaced by the BIP check code word. Here, the non-K-code subframe is a data subframe generated after replacing the control codeword in the K-code subframe with the BIP check codeword of the previous data subframe.

Step 804, scrambling the data processed by the BIP;

and step 805, outputting the data after scrambling to the SERDES through a PCS logic side interface of the SERDES, and transmitting the data to the second FPGA through parallel-serial conversion of the SERDES.

Step 806, performing K code synchronization, K code alignment and other processing on data output by a PCS logic side interface of the SERDES in the second FPGA, wherein when the processed data are output, the K code is located at the lowest byte;

step 807, descrambling the data after the processes of K code synchronization, K code alignment and the like, and taking out the data in the data subframe;

step 808, writing the descrambled data into an RX _ RAM array in sequence, and simultaneously performing BIP (binary processing) to realize online error monitoring;

wherein the data containing the control code words are written into the first row RX _ RAM of the RX _ RAM array in the second piece of FPGA.

And step 809, reading data from the RX _ RAM array of the second FPGA according to the columns, deleting the control code words or check code words of the lowest bytes in the data, and outputting the control code words or check code words.

In this embodiment, the data frame used in the FPGA inter-chip data transmission method adapted to various SERDES line rates includes three types of data: k code (K28.5 codeword), BIP check codeword, data to be transmitted. As shown in fig. 2, each data frame includes C _ K _ DIS (the parameter is an integer greater than 0) data subframes, at least 1K-code subframe, and several BIP subframes. When C _ K _ DIS is 1, the data frame includes only one K-code subframe. Each data subframe consists of N x L bits, N is a RAM matrix row parameter, L is a PCS interface data bit width of a SERDES hard IP, and the first byte in the data subframe is a K code or a BIP check code word.

Exemplary implementations of the above embodiments are described in detail below. It should be noted that the following examples may be arbitrarily combined. In addition, in practical applications, the above embodiments may have other implementation manners, and in the following examples, the flow, the execution process, and the like may also be adjusted according to needs of practical applications.

Example 1

For a specific example, the SERDES line rate is 10Gbps, an 8B/10B coding method is used, the PCS interface bit width is 32 bits, the clock of data to be transmitted is 0.01Ghz, the number of RAM rows of the RAM array is 25, that is, the number of TX _ RAM rows of the TX _ RAM array in the first FPGA is 25, the number of RX _ RAM rows of the RX _ RAM array in the second FPGA is 25, and the bearable data bit width is 792 bits. 792bit data and 0xBC (K28.5 code word) in the first FPGA are combined (the control code word is placed in the lowest byte), the combined data are written into a TX _ RAM array under a to-be-transmitted data clock domain, and the combined data are stored according to 32 byte sequence, wherein the lowest 32bit is in the first row, and the highest 32bit is in the last row. And under a PCS interface clock domain, sequentially taking out the data of the same column in 25 blocks of TX _ RAMs according to the sequence of the row numbers of the TX _ RAMs in the TX _ RAM array (because the same column in each TX _ RAM array forms a data subframe), sending the data to a BIP generation module, processing the data added with the BIP check information by a scrambling module, outputting the data to a SERDES through a PCS interface, and sending the data to a second FPGA through SERDES parallel-serial conversion. The 32bit data after SERDES serial conversion is output to the second FPGA through a PCS interface, and the second FPGA sends the data to a BIP analysis module after descrambling processing, and whether errors occur in the transmission process is detected. And simultaneously writing the descrambled data into an RX _ RAM array, storing the data with the control code words or the check code words into a first row RX _ RAM of the RX _ RAM array, and sequentially writing the rest data into the RX _ RAMs in each row according to the ascending sequence of the row numbers of the RX _ RAMs in the RX _ RAM array. On the read interface side of the RX _ RAM array, the 10Mhz clock is used for reading the whole column of data, the lowest byte of the data in the first row of RX _ RAM is deleted, and the data sent by the first FPGA is extracted.

When the SERDES line rate can only support 6Gbps, the number of the RAMs is only changed to 15, the clock of the data to be transmitted is still 0.01Gbps, the bit width of the data to be transmitted is changed to 472 bits, and the data can still be directly used in the prototype system.

Example 2

The FPGAs in the two prototype system boards communicate through a 10G SERDES via a hot plug Small Form-factor (SFP) optical module, if the PCS interface outputs a data bit width of 32bit and the operating frequency of the module to be tested is 25Mhz, the number of rows of the RAM in the RAM array is 10, that is, the number of rows of the TX _ RAM in the TX _ RAM array in the first FPGA is 10, the number of rows of the RX _ RAM in the RX _ RAM array in the second FPGA is 10, and the bit width of the data to be transmitted is 312. The first FPGA packs 312bit data and 0xBC to form a data subframe, and the data subframe is written into a TX _ RAM array under a 25Mhz clock domain; under the PCS interface clock domain 250Mhz, data subframes are sequentially read out from a first line from a TX _ RAM array according to the TX _ RAM line sequence, and are transmitted to a PCS interface of SERDES hard IP through a BIP generation module and a scrambling module. Through SERDES hard IP parallel-serial conversion, an optical signal is converted into an optical signal through SFP, the optical signal is transmitted to SFP of another single board through an optical fiber, the optical signal is input into SERDES through photoelectric conversion, the optical signal is output to a second FPGA from a PCS interface through serial-parallel conversion, a receiving link of the second FPGA uses a clock recovered by a clock data recovery module (CDR) to write data output by the PCS interface into a BIP check module and an RX _ RAM array respectively; and reading the data of the same column in multiple rows of RX _ RAMs in the RX _ RAM array by using a 25Mhz clock generated by a Phase Locked Loop (PLL) through the CDR, and removing the lowest byte to output to other modules for use.

It will be understood by those skilled in the art that all or part of the steps of the above methods may be implemented by a program instructing associated hardware (e.g., a processor) to perform the steps, and the program may be stored in a computer readable storage medium, such as a read only memory, a magnetic or optical disk, and the like. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, the modules/units in the above embodiments may be implemented in hardware, for example, by an integrated circuit, or may be implemented in software, for example, by a processor executing programs/instructions stored in a memory to implement the corresponding functions. The present application is not limited to any specific form of hardware or software combination.

The foregoing shows and describes the general principles and features of the present application, together with the advantages thereof. The present application is not limited to the above-described embodiments, which are described in the specification and drawings only to illustrate the principles of the application, but also to provide various changes and modifications within the spirit and scope of the application, which are within the scope of the claimed application.

Claims

1. A method for transmitting high-bit-width data between FPGA chips comprises the following steps:

packaging parallel data to be sent in a first FPGA and control code words to form a data subframe and writing the data subframe into a TX _ RAM array of a random access memory of a transmitting terminal, wherein the number of TX _ RAM lines in the TX _ RAM array is matched with the line rate of a current SERDES and the data bit width of a PCS interface; wherein, the number of rows of the TX _ RAM is (XA/Y)/L, X is the line rate of the SERDES, A is the coding efficiency, Y is the data rate to be transmitted, and L is the data bit width of the PCS interface;

2. The method of claim 1, wherein the data bit width of each TX RAM in the TX RAM array matches the physical coding sublayer PCS interface data bit width of a SERDES.

3. The method of claim 1, wherein before the packaging the parallel data to be transmitted in the first FPGA with the control codeword into a data subframe and writing the data subframe to the TX _ RAM array, the method further comprises:

and determining the number of TX _ RAM rows in the TX _ RAM array according to the line rate of the current SERDES, the data bit width of the PCS interface and the data rate to be transmitted, and forming the TX _ RAM array according to the determined number of the TX _ RAM rows.

4. The method of claim 1, wherein before sending the BIP processed data to the SERDES, the method further comprises:

and scrambling the data processed by the BIP.

5. A method for transmitting high-bit-width data between FPGA chips comprises the following steps:

writing data from an SERDES PCS interface into a receiving end random access memory (RX _ RAM) array of a second FPGA, wherein the number of RX _ RAM rows in the RX _ RAM array is matched with the line rate of the SERDES and the data bit width of a PCS interface; wherein, the number of rows of the RX _ RAM is (XA/Y)/L, X is the line rate of the SERDES, A is the coding efficiency, Y is the data rate to be transmitted, and L is the data bit width of the PCS interface;

6. The method of claim 5, wherein before writing data from the SERDES PCS interface to the RX _ RAM array of the second slice FPGA, further comprising:

and performing descrambling processing on the data from the SERDES PCS interface.

7. The method of claim 5, wherein writing data from the SERDES PCS interface to the RX _ RAM array of the second slice FPGA further comprises:

and carrying out BIP check on the data from the SERDES PCS interface, and comparing the data with the BIP check code word sent along the channel to monitor whether errors occur in the transmission process.

8. The method of claim 5, wherein before writing data from the SERDES PCS interface to the RX _ RAM array of the second slice FPGA, further comprising:

and determining the number of RX _ RAM rows in the RX _ RAM array according to the line rate of the current SERDES, the data bit width of the PCS interface and the data rate to be transmitted, and forming the RX _ RAM array according to the determined number of RX _ RAM rows.

9. The method according to any one of claims 5 to 8, wherein before writing the data from the SERDES PCS interface into the RX _ RAM array of the receiving random access memory of the second FPGA, the method further comprises:

judging whether a receiving link enters a synchronous state according to the data output by the PCS interface and a K code indicating signal, and receiving the data from the SERDES PCS interface after the receiving link enters the synchronous state;

and carrying out byte alignment adjustment on the data from the SERDES PCS interface, and adjusting the K code to the lowest byte.

10. An FPGA supporting high-bit-width data transfers, comprising:

the data frame generating module comprises a transmitting terminal random access memory TX _ RAM array, wherein the number of TX _ RAM rows in the TX _ RAM array is matched with the line rate of the current SERDES and the data bit width of a PCS interface; the system comprises a TX _ RAM array, a time division multiplexing TDM mode, a parallel data transmission module, a time division multiplexing TDM mode and a control code word, wherein the TX _ RAM array is used for transmitting parallel data and control code words to be transmitted; wherein, the number of rows of the TX _ RAM is (XA/Y)/L, X is the line rate of the SERDES, A is the coding efficiency, Y is the data rate to be transmitted, and L is the data bit width of the PCS interface;

11. The FPGA of claim 10, further comprising:

and the scrambling module is used for scrambling the data processed by the BIP and sending the scrambled data to the SERDES so that the SERDES can be sent to other FPGAs after parallel-serial conversion.

12. An FPGA supporting high-bit-width data transfers, comprising:

the data frame analysis module comprises a receiving end random access memory (RX _ RAM) array, wherein the number of RX _ RAM rows in the RX _ RAM array is matched with the line rate of a SERDES (serial data encryption standard) and the data bit width of a PCS (personal communications System) interface, and the data frame analysis module is used for writing data from an SERDES PCS interface into the RX _ RAM array, reading the data from the RX _ RAM array of a second FPGA according to columns, deleting a control code word or a check code word of the lowest byte in the data and outputting the control code word or the check code word; wherein, the number of rows of the RX _ RAM is (XA/Y)/L, X is the line rate of the SERDES, A is the coding efficiency, Y is the data rate to be transmitted, and L is the data bit width of the PCS interface.

13. The FPGA of claim 12, further comprising:

and the descrambling module is used for descrambling the data from the SERDES PCS interface and then sending the descrambled data to the data frame analysis module.

14. The FPGA of claim 12, further comprising:

and the BIP analysis module is used for carrying out BIP check on the data from the SERDES PCS interface and comparing the data with the BIP check code word sent along the channel so as to monitor whether errors occur in the transmission process.

15. The FPGA of any one of claims 12 to 14, further comprising:

the K code synchronization module is used for judging whether a receiving link enters a synchronization state according to the data output by the PCS interface and a K code indication signal and receiving the data from the SERDES PCS interface after the receiving link enters the synchronization state;

and the K code alignment module is used for carrying out byte alignment adjustment on the data from the SERDES PCS interface, adjusting the K code to the lowest byte, and outputting the adjusted data to the data frame analysis module or the descrambling module.

16. An apparatus for high bit width data transmission between FPGA chips, comprising: the device comprises a first FPGA, an SERDES and a second FPGA, wherein the first FPGA and the second FPGA are respectively connected with a physical coding sublayer PCS interface of the SERDES;

the first FPGA comprises a transmitting-end random access memory TX _ RAM array, the number of rows of TX _ RAM in the TX _ RAM array is matched with the line rate of the SERDES and the data bit width of the PCS interface, and the first FPGA is configured to execute an FPGA inter-chip high-bit-width data transmission program so as to execute the operation of the method according to any one of claims 1 to 4;

the second FPGA chip comprises a RX _ RAM array, wherein the number of RX _ RAM rows in the RX _ RAM array matches the line rate of the SERDES and the data bit width of the PCS interface, and is configured to execute an FPGA chip-to-chip high bit width data transmission program to perform the operations of the method according to any one of claims 5 to 9;