CN112445659B - Multi-protocol high-speed serdes test implementation method and system - Google Patents
Multi-protocol high-speed serdes test implementation method and system Download PDFInfo
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- CN112445659B CN112445659B CN201910797541.4A CN201910797541A CN112445659B CN 112445659 B CN112445659 B CN 112445659B CN 201910797541 A CN201910797541 A CN 201910797541A CN 112445659 B CN112445659 B CN 112445659B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Abstract
The invention discloses a multi-protocol high-speed serdes test implementation method and a system, and relates to the field of testing, wherein the method comprises the steps of checking a test file corresponding to a high-speed serdes interface to be tested in a CPU to obtain a check code, wherein the test file is a data packet containing a pseudo-random code, and a frame header of the data packet corresponds to a protocol of the high-speed serdes interface to be tested; sending an FPGA file and a test file to an FPGA of a test platform through a high-speed serdes interface to be tested, wherein the FPGA file comprises a verification algorithm for verifying the test file; the FPGA checks the test file, and sends the check code obtained by the check to the CPU through the high-speed serdes interface to be tested; and the CPU receives the check code sent by the FPGA, compares the check code with the check code obtained by the previous check, and completes the test of the high-speed serdes interface. The invention can greatly improve the test efficiency of the high-speed serdes interface.
Description
Technical Field
The invention relates to the field of testing, in particular to a method and a system for realizing multi-protocol high-speed serdes testing.
Background
With the development of embedded technology, the development of moore's law, the continuous improvement of technology level, the continuous enhancement of miniaturization requirement and the continuous increase of data throughput, the functions integrated on a piece of embedded CPU (Central Processing Unit ) are more and more, the speed is higher and higher, in order to consider factors such as product life cycle, development period and the like, and combine comprehensive factors such as wider use scenes, the high-speed serdes (SERializer-DESerializer) interface of the CPU is compatible with different protocol standards, such as PCI-E (peripheral component interconnect express, high-speed serial computer expansion bus standard) protocol standard interface, SGMII (Serial Gigabit Media Independent Interface, serial media independent media interface) protocol standard interface, SATA (Serial Advanced Technology Attachment, computer bus) protocol interface standard, XFI protocol interface (10 gigabit per second inter-chip electrical interface specification) and the like.
In the current general design, the above protocols and interfaces are generally set based on application scenarios, and are implemented by different CPU configuration words, where each scenario corresponds to a configuration word, and the configuration word is written into an RCW file, that is, the relevant configuration word file is fixed at the beginning of setting the application scenario, so that the system cannot be modified after running. For testing of the high-speed interface of the CPU, the current common practice is to independently design a test platform to realize testing and verification of the high-speed interface and protocol according to different application scenes, but the common practice is to face the increasingly updated CPU technology and flexible configuration of the high-speed interface, the common practice has been proved to be the forefront, the working of verifying the high-speed interface of the same CPU in different application scenes can not be realized, or related verification can not be realized due to great waste of manpower, material resources and financial resources, and a new method is needed to realize the testing and verification.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention aims to provide a method and a system for realizing multi-protocol high-speed serdes test, which can greatly improve the test efficiency of a high-speed serdes interface.
In order to achieve the above purpose, the invention provides a method for implementing multi-protocol high-speed serdes test, which comprises the following steps:
checking a test file corresponding to a high-speed serdes interface to be tested in a CPU to obtain a check code, wherein the test file is a data packet containing a pseudo-random code, and the frame header of the data packet corresponds to a protocol of the high-speed serdes interface to be tested;
sending an FPGA file and a test file to an FPGA of a test platform through a high-speed serdes interface to be tested, wherein the FPGA file comprises a verification algorithm for verifying the test file;
the FPGA checks the test file, and sends the check code obtained by the check to the CPU through the high-speed serdes interface to be tested;
and the CPU receives the check code sent by the FPGA, compares the check code with the check code obtained by the previous check, and completes the test of the high-speed serdes interface.
On the basis of the technical scheme, the data packet contains check bytes, and the check bytes are used for obtaining check codes when the test file is checked by a check algorithm.
Based on the technical scheme, the test file corresponding to the high-speed serdes interface to be tested is checked in the CPU to obtain a check code, and the specific steps include:
loading an FPGA file and a test file corresponding to a high-speed serdes interface to be tested into a nonvolatile memory Flash corresponding to a CPU, wherein the FPGA file comprises a verification algorithm for verifying the test file;
the CPU checks the test file through a checking algorithm, analyzes check bytes inserted in the data packet, and obtains a check code.
On the basis of the technical proposal, the method comprises the following steps,
the FPGA file and the test file are sent to the FPGA of the test platform through the high-speed serdes interface to be tested, and the specific steps are as follows: compiling the FPGA file and the test file into format files corresponding to the high-speed serdes interface protocol to be tested, and then sending the compiled FPGA file and test file to the FPGA of the test platform through the high-speed serdes interface to be tested;
and the check code obtained by the check is sent to the CPU through the high-speed serdes interface to be tested, and the specific steps are as follows: and compiling the check code obtained by checking into a format file corresponding to the high-speed serdes interface protocol to be tested, and then sending the format file to the CPU through the high-speed serdes interface to be tested.
On the basis of the technical scheme, the test files are checked in the CPU and the FPGA for set times, if the check code obtained by checking each test file in the CPU is the same as the check code obtained by checking each test file in the CPU, the test is passed, and if not, the test is terminated.
The invention provides a multi-protocol high-speed serdes test implementation system, which comprises a PC and a test platform;
the PC is used for connecting a CPU to be tested so as to send a test file to the CPU to be tested through the switch, after the test file reaches the CPU to be tested, the CPU to be tested checks the test file to obtain a check code, meanwhile, the CPU to be tested sends the test file and the FPGA file to an FPGA of a test platform corresponding to the current CPU to be tested, then the check code obtained by checking the test file by the CPU to be tested is compared with the check code obtained by checking the test file by the FPGA, the FPGA file comprises a check algorithm for checking the test file, the test file is a data packet containing pseudo random codes, and the frame header of the data packet corresponds to a protocol of a high-speed serdes interface to be tested in the CPU to be tested;
the testing platform is used for being connected with the CPU to be tested through the high-speed serdes interface to be tested, the FPGA in the testing platform is used for checking the test file sent by the CPU to be tested to obtain the check code, and the obtained check code is sent to the CPU to be tested through the high-speed serdes interface to be tested.
On the basis of the technical scheme, the data packet contains check bytes, and the check bytes are used for obtaining check codes when the test file is checked by a check algorithm.
On the basis of the technical scheme, the CPU to be tested checks the test file to obtain the check code, and the specific process comprises the following steps:
loading an FPGA file and a test file corresponding to a high-speed serdes interface to be tested into a nonvolatile memory flash corresponding to a CPU, wherein the FPGA file comprises a verification algorithm for verifying the test file;
the CPU checks the test file through a checking algorithm, analyzes check bytes inserted in the data packet, and obtains a check code.
On the basis of the technical proposal, the method comprises the following steps,
the CPU to be tested sends the test file and the FPGA file to the FPGA of the test platform corresponding to the current CPU to be tested, and the specific steps are as follows: compiling the FPGA file and the test file into format files corresponding to the high-speed serdes interface protocol to be tested, and then sending the compiled FPGA file and test file to the FPGA of the test platform through the high-speed serdes interface to be tested;
the FPGA sends the obtained check code to the CPU to be tested through the high-speed serdes interface to be tested, and the method comprises the following specific steps of: and compiling the check code obtained by checking into a format file corresponding to the high-speed serdes interface protocol to be tested, and then sending the format file to the CPU through the high-speed serdes interface to be tested.
On the basis of the technical scheme, the test files are checked in the CPU and the FPGA for set times, if the check code obtained by checking each test file in the CPU is the same as the check code obtained by checking each test file in the CPU, the test is passed, and if not, the test is terminated.
Compared with the prior art, the invention has the advantages that: the test file is transmitted in the high-speed serdes interface to be tested, the frame header of the test file data packet corresponds to the protocol of the high-speed serdes interface to be tested, the test file is correlated with the protocol of the high-speed serdes interface to be tested, the test of the high-speed interface and the protocol under the condition of different scenes of the same CPU can be completed by replacing the test file, the test of one set of test platform on different high-speed serdes interfaces and protocols of the same CPU is realized, the test efficiency of the high-speed serdes interface is greatly improved, and the test cost is reduced.
Drawings
FIG. 1 is a flow chart of a method for implementing a multi-protocol high-speed serdes test in an embodiment of the invention;
fig. 2 is a schematic structural diagram of a multi-protocol high-speed serdes test implementation system according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a method for realizing the multi-protocol high-speed serdes test, which can flexibly test and verify high-speed interfaces and protocols under different use scenes, effectively improves the test efficiency of the high-speed serdes interfaces, and correspondingly provides a system for realizing the multi-protocol high-speed serdes test.
Referring to fig. 1, an embodiment of a method for implementing a multi-protocol high-speed serdes test according to an embodiment of the present invention includes:
s1: and checking the test file corresponding to the high-speed serdes interface to be tested in the CPU to obtain a check code. The test file is a data packet containing pseudo-random codes, and the frame header of the data packet corresponds to a protocol of a high-speed serdes interface to be tested;
in the embodiment of the invention, the data packet contains the check byte, and the check byte is used for obtaining the check code when the test file is checked by the check algorithm, for example, the check byte is inserted in a fixed position of the data packet, and a fixed check code such as an MD5 value can be obtained by calculation of the check algorithm.
For the CPU, through flexible configuration words, a plurality of different high-speed Serdes interfaces can be simultaneously realized, for example, a CPU can realize 1 PCI-E interface and 4 SGMII interfaces through flexible configuration words, and can also realize 3 PCI-E interfaces and 1 SGMII interface, wherein the PCI-E interfaces correspond to PCI-E protocol, the SGMII interfaces correspond to SGMII protocol, because one CPU can realize a plurality of high-speed Serdes interfaces, when testing is carried out on the high-speed Serdes interfaces in the prior art, a plurality of test platforms are needed to be used on different interfaces, so that the test period is long, each verification platform needs to be put into a large amount of manpower, material resources and a long development period, and serious waste of resources is caused, each verification platform needs a set of corresponding software and hardware, so that management difficulty, archiving difficulty, difficulty in use and the like are caused, and the like are caused by the fact that the CPU is difficult to use a set of corresponding to the corresponding protocol, namely, the CPU can not finish the test for the protocol, namely, the invention can realize the test for the protocol, the test for the corresponding interface, the protocol, namely, the test platform is different from the protocol, the test platform, E, SGMII, SATA, XFI, and the test platform is different from the common interface.
S2: the test file is sent to the FPGA (Field-Programmable Gate Array, field programmable gate array) of the test platform via the high-speed services interface to be tested. Under different application scenarios, the types of the high-speed serdes interfaces of the CPU are different, but each high-speed serdes interface corresponds to a specific protocol.
S3: the FPGA checks the test file, and sends the check code obtained by the check to the CPU through the high-speed serdes interface to be tested;
s4: and the CPU receives the check code sent by the FPGA, compares the check code with the check code obtained by the previous check, and completes the test of the high-speed serdes interface. And when the check code sent by the FPGA and received by the CPU is consistent with the check code obtained by the previous check, the test result of the high-speed serdes interface to be tested is successful, otherwise, the test result is unsuccessful.
According to the multi-protocol high-speed serdes test implementation method, the test file is transmitted in the high-speed serdes interface to be tested, the frame header of the test file data packet corresponds to the protocol of the high-speed serdes interface to be tested, the test file is related to the protocol of the high-speed serdes interface to be tested, the test of the high-speed interface and the protocol under the condition of different scenes of the same CPU can be completed by replacing the test file, the test of one set of test platform on the different high-speed serdes interfaces and the protocol of the same CPU is realized, the test efficiency of the high-speed serdes interface is greatly improved, and the test cost is reduced.
Optionally, in a first alternative embodiment of the implementation method of the multi-protocol high-speed serdes test provided by the embodiment of the present invention based on the corresponding embodiment of fig. 1, a test file corresponding to a high-speed serdes interface to be tested is checked in a CPU to obtain a check code, which specifically includes the steps of:
s101: loading an FPGA file and a test file corresponding to a high-speed serdes interface to be tested into a nonvolatile memory Flash (Flash memory) corresponding to a CPU, wherein the FPGA file comprises a verification algorithm for verifying the test file, and analyzing a protocol;
s102: the CPU checks the test file through a checking algorithm, analyzes check bytes inserted in the data packet, and obtains a check code.
Optionally, based on the first alternative embodiment of the implementation method of the multi-protocol high-speed serdes test, in a second alternative embodiment of the implementation method of the multi-protocol high-speed serdes test provided by the embodiment of the present invention,
the method comprises the following specific steps of sending an FPGA file and a test file to an FPGA of a test platform through a high-speed serdes interface to be tested: and compiling the FPGA file and the test file into format files corresponding to the high-speed serdes interface protocol to be tested, and then sending the compiled FPGA file and test file to the FPGA of the test platform through the high-speed serdes interface to be tested. For example, when the protocol of the high-speed serdes interface to be tested is PCI-E protocol, the FPGA file and the test file are compiled into PCI-E protocol format file.
The check code obtained by checking is sent to the CPU through the high-speed serdes interface to be tested, and the specific steps are as follows: and compiling the check code obtained by checking into a format file corresponding to the high-speed serdes interface protocol to be tested, and then sending the format file to the CPU through the high-speed serdes interface to be tested.
The test files are checked in the CPU and the FPGA for set times, if the check code obtained by checking each test file in the CPU is the same as the check code obtained by checking each test file in the CPU, the test is passed, and if not, the test is terminated. And the consistency and accuracy of test results are ensured through multiple tests.
Referring to fig. 2, the system for implementing multi-protocol high-speed serdes test provided by the embodiment of the invention includes a PC and test platforms, in a specific operation process, the number of test platforms may be multiple, and the number of CPUs to be tested of the test platforms is the same, each test platform corresponds to one CPU to be tested, and when the number of CPUs to be tested is multiple, each CPU to be tested is connected with the PC through a switch. For example, when the number of the CPUs to be tested is one, the number of the test platforms is one, when the number of the CPUs to be tested is two, the number of the test platforms is two, the simultaneous test of one or more CPUs to be tested is realized, and the test of different high-speed serdes interfaces of each CPU to be tested is completed through one test platform corresponding to the CPU to be tested.
The PC is used for connecting the CPU to be tested so as to send the test file to the CPU to be tested through the switch, and optionally, the PC can be connected with the CPU to be tested through the switch. DDR (Double Data Rate) memory, flash, network port, CPLD (Complex Programmable Logic Device ) and CPU to be tested form a system to be tested, wherein the CPLD comprises a configuration word module and a communication module, and the communication module is connected with the CPU to be tested through IFC signals. The testing platform comprises a DDR and an FPGA, wherein the FPGA comprises a receiving module, a checking module and a sending module. The CPU to be tested is communicated with the test platform through a serdes signal, SPI (Serial Peripheral Interface ) and I2C bus.
The test file is a data packet containing pseudo-random codes, and the frame header of the data packet corresponds to a protocol of a high-speed serdes interface to be tested in the CPU to be tested. The TFTP (Trivial File Transfer Protocol, simple file transfer protocol) server of the PC stores all test files corresponding to the protocols of the high-speed services interface. After starting the test, the PC automatically loads a test file and an FPGA file in a scene into a nonvolatile memory Flash corresponding to the CPU to be tested through a network port, the CPU to be tested automatically works an IFC control management interface, a configuration word command of the application scene is sent to an output IO of the CPLD, the value is always maintained, the configuration word is an interface of an initialization CPU of an Enzhi CPU or other manufacturer CPUs, the configuration word is realized by using a high-low level binary system, different functions and interface configurations of different CPUs or the same CPU are carried out, the values are different, the configuration is determined according to actual CPU manufacturers, CPU models and functions and configurations, then the CPU to be tested is reset and restarted, the configuration word, a software package and the FPGA file of the application scene are loaded in the Flash, and the FPGA application program is updated.
When the test file reaches the CPU to be tested, the CPU to be tested checks the test file to obtain a check code, meanwhile, the CPU to be tested sends the test file and the FPGA file to the FPGA of the test platform corresponding to the current CPU to be tested, and then the check code obtained by the CPU to be tested checking the test file is compared with the check code obtained by the FPGA checking the test file, wherein the FPGA file comprises a check algorithm for checking the test file. The testing platform is used for being connected with the CPU to be tested through the high-speed serdes interface to be tested, the FPGA in the testing platform is used for checking the test file sent by the CPU to be tested to obtain the check code, and the obtained check code is sent to the CPU to be tested through the high-speed serdes interface to be tested.
Optionally, on the basis of the foregoing embodiment corresponding to fig. 2, in a first optional embodiment of the system for implementing multi-protocol high-speed serdes testing according to the embodiment of the present invention, a data packet includes a check byte, where the check byte is used to obtain a check code when a test file is checked by a check algorithm.
The CPU to be tested checks the test file to obtain a check code, and the specific process comprises the following steps:
loading an FPGA file and a test file corresponding to a high-speed serdes interface to be tested into a nonvolatile memory flash corresponding to a CPU, wherein the FPGA file comprises a verification algorithm for verifying the test file;
the CPU checks the test file through a checking algorithm, analyzes check bytes inserted in the data packet, and obtains a check code.
The CPU to be tested sends the test file and the FPGA file to the FPGA of the test platform corresponding to the current CPU to be tested, and the specific steps are as follows: compiling the FPGA file and the test file into format files corresponding to the high-speed serdes interface protocol to be tested, and then sending the compiled FPGA file and test file to the FPGA of the test platform through the high-speed serdes interface to be tested; the FPGA sends the obtained check code to the CPU to be tested through the high-speed serdes interface to be tested, and the method comprises the following specific steps: and compiling the check code obtained by checking into a format file corresponding to the high-speed serdes interface protocol to be tested, and then sending the format file to the CPU through the high-speed serdes interface to be tested. The test files are checked in the CPU and the FPGA for set times, if the check code obtained by checking each test file in the CPU is the same as the check code obtained by checking each test file in the CPU, the test is passed, and if not, the test is terminated.
The invention is not limited to the embodiments described above, but a number of modifications and adaptations can be made by a person skilled in the art without departing from the principle of the invention, which modifications and adaptations are also considered to be within the scope of the invention. What is not described in detail in this specification is prior art known to those skilled in the art.
Claims (8)
1. The method for realizing the multi-protocol high-speed serdes test is characterized by comprising the following steps of:
checking a test file corresponding to a high-speed serdes interface to be tested in a CPU to obtain a check code, wherein the test file is a data packet containing a pseudo-random code, the frame header of the data packet corresponds to a protocol of the high-speed serdes interface to be tested, and each high-speed serdes interface to be tested corresponds to one protocol;
sending an FPGA file and a test file to an FPGA of a test platform through a high-speed serdes interface to be tested, wherein the FPGA file comprises a verification algorithm for verifying the test file;
the FPGA checks the test file, and sends the check code obtained by the check to the CPU through the high-speed serdes interface to be tested;
the CPU receives the check code sent by the FPGA, compares the check code with the check code obtained by the previous check, and completes the test of the high-speed serdes interface;
the data packet contains check bytes, and the check bytes are used for obtaining check codes when the test file is checked by a check algorithm.
2. The method for implementing the multi-protocol high-speed serdes test according to claim 1, wherein the checking the test file corresponding to the high-speed serdes interface to be tested in the CPU to obtain the check code specifically comprises the following steps:
loading an FPGA file and a test file corresponding to a high-speed serdes interface to be tested into a nonvolatile memory Flash corresponding to a CPU, wherein the FPGA file comprises a verification algorithm for verifying the test file;
the CPU checks the test file through a checking algorithm, analyzes check bytes inserted in the data packet, and obtains a check code.
3. The method for implementing the multi-protocol high-speed serdes test according to claim 1, wherein:
the FPGA file and the test file are sent to the FPGA of the test platform through the high-speed serdes interface to be tested, and the specific steps are as follows: compiling the FPGA file and the test file into format files corresponding to the high-speed serdes interface protocol to be tested, and then sending the compiled FPGA file and test file to the FPGA of the test platform through the high-speed serdes interface to be tested;
and the check code obtained by the check is sent to the CPU through the high-speed serdes interface to be tested, and the specific steps are as follows: and compiling the check code obtained by checking into a format file corresponding to the high-speed serdes interface protocol to be tested, and then sending the format file to the CPU through the high-speed serdes interface to be tested.
4. The method for implementing the multi-protocol high-speed serdes test according to claim 1, wherein: and the test files are checked for set times in the CPU and the FPGA, if the check code obtained by checking the test files in the CPU at each time is the same as the check code obtained by checking the test files in the FPGA at each time, the test is passed, and if not, the test is terminated.
5. The system for realizing the multi-protocol high-speed serdes test is characterized by comprising a PC and a test platform;
the PC is used for connecting a CPU to be tested so as to send a test file to the CPU to be tested through the switch, after the test file reaches the CPU to be tested, the CPU to be tested checks the test file to obtain a check code, meanwhile, the CPU to be tested sends the test file and the FPGA file to an FPGA of a test platform corresponding to the current CPU to be tested, then the check code obtained by checking the test file by the CPU to be tested is compared with the check code obtained by checking the test file by the FPGA, the FPGA file comprises a check algorithm for checking the test file, the test file is a data packet containing pseudo random codes, the frame header of the data packet corresponds to a protocol of a high-speed serdes interface to be tested in the CPU to be tested, and each high-speed serdes interface to be tested corresponds to one protocol;
the testing platform is used for connecting a CPU to be tested through a high-speed serdes interface to be tested, the FPGA in the testing platform is used for checking a test file sent by the CPU to be tested to obtain a check code, and the obtained check code is sent to the CPU to be tested through the high-speed serdes interface to be tested;
the data packet contains check bytes, and the check bytes are used for obtaining check codes when the test file is checked by a check algorithm.
6. A multi-protocol high-speed serdes test implementation system according to claim 5, wherein: the CPU to be tested checks the test file to obtain a check code, and the specific process comprises the following steps:
loading an FPGA file and a test file corresponding to a high-speed serdes interface to be tested into a nonvolatile memory flash corresponding to a CPU, wherein the FPGA file comprises a verification algorithm for verifying the test file;
the CPU checks the test file through a checking algorithm, analyzes check bytes inserted in the data packet, and obtains a check code.
7. A multi-protocol high-speed serdes test implementation system according to claim 5, wherein:
the CPU to be tested sends the test file and the FPGA file to the FPGA of the test platform corresponding to the current CPU to be tested, and the specific steps are as follows: compiling the FPGA file and the test file into format files corresponding to the high-speed serdes interface protocol to be tested, and then sending the compiled FPGA file and test file to the FPGA of the test platform through the high-speed serdes interface to be tested;
the FPGA sends the obtained check code to the CPU to be tested through the high-speed serdes interface to be tested, and the method comprises the following specific steps of: and compiling the check code obtained by checking into a format file corresponding to the high-speed serdes interface protocol to be tested, and then sending the format file to the CPU through the high-speed serdes interface to be tested.
8. A multi-protocol high-speed serdes test implementation system according to claim 5, wherein: and the test files are checked for set times in the CPU and the FPGA, if the check code obtained by checking the test files in the CPU at each time is the same as the check code obtained by checking the test files in the FPGA at each time, the test is passed, and if not, the test is terminated.
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