CN109426636A - The method and device that high-bit width data are transmitted between a kind of FPGA piece - Google Patents
The method and device that high-bit width data are transmitted between a kind of FPGA piece Download PDFInfo
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Abstract
The method and device that high-bit width data between a kind of FPGA piece are transmitted is disclosed herein, it include: by parallel data to be sent in first FPGA and to control code word packing group into data burst and be written in TX_RAM array, the TX_RAM line number in the TX_RAM array matches with the line rate of current SERDES, PCS interface data bit width；By the data burst in the TX_RAM array in a manner of arranging as unit according to TDM timesharing by row Sequential output；The BIP check code word that control code word in the data by row Sequential output is changed to a upper subframe is handled by BIP；The BIP treated data are sent into SERDES, to be sent to second FPGA after SERDES parallel-serial conversion.The application at least can be applicable in a variety of SERDES line rates by same framing device.
Description
Technical field
The present invention relates to field of computer technology, and in particular to a kind of FPGA (Field Programmable Gate
Array, field programmable gate array) high-bit width data are transmitted between piece method and device.
Background technique
In recent years, chip industry is quickly grown, and to improve flow success rate of chip, accelerates software kit maturation, more
Lai Yueduo producer carries out chip functions verifying using FPGA prototype system.Therewith between bring FPGA piece high-bit width data transmission at
For the major issue of prototype system.
The transmission mode of high-bit width data includes parallel transmission and serial transmission between FPGA piece.Wherein, parallel transmission passes through
Data bit width is improved to realize that data bandwidth increases, is unable to satisfy in chip prototype system between FPGA piece hundreds of upper kilobits easily
The transmission demand of parallel data.In the related technology general method be using SERDES (SERializer/DESerializer,
Serializer/simultaneously changes device, also known as parallel series and staticizer) serialized transport is carried out, convert parallel data into single bit's
Differential signal is transmitted, and can not only provide higher data bandwidth and transmission stability is high.
Existing prototype system transmits the scheme of high-bit width data between FPGA piece by SERDES, some agreements complexity, such as with
Too fidonetFido, Peripheral Component Interconnect extension standards (PCIe, peripheral component interconnect express)
Deng only supporting the application scenarios of fixed SERDES rate, using limited, adapting to scene has limitation；Some versatilities are poor, needle
The application scenarios of different SERDES rates are needed with different framing devices, it is at high cost.It follows that in the related technology otherwise branch
Different framing device is needed under the SERDES line rate held is single or different SERDES rates, is that technology urgently to be resolved is asked
Topic.
Summary of the invention
In order to solve the above-mentioned technical problem, the embodiment of the invention provides the sides that high-bit width data between a kind of FPGA piece are transmitted
Method and device at least can be applicable in a variety of SERDES line rates by same framing device.
This application provides:
A kind of method that high-bit width data are transmitted between FPGA piece, comprising:
At data burst and transmitting terminal is written into parallel data to be sent in first FPGA and control code word packing group
In random access memory TX_RAM array, the TX_RAM line number in the TX_RAM array connects with the line rate of current SERDES, PCS
Mouth data bit width matches；
By the data burst in the TX_RAM array in a manner of arranging as unit according to time division multiplexing tdm timesharing by row sequence
Output；
Code word will be controlled by being handled by bit interleaved parity BIP in the data by row Sequential output is changed to
The BIP check code word of one subframe；
The BIP treated data are sent into SERDES, to be sent to second FPGA after SERDES parallel-serial conversion.
Wherein, the data bit width of each TX_RAM and the Physical Coding Sublayer PCS interface of SERDES in the TX_RAM array
Data bit width matches.
Wherein, described at data burst and to write parallel data to be sent in first FPGA and control code word packing group
Before entering in TX_RAM array, further includes: according to the line rate of current SERDES, PCS interface data bit width and number to be transmitted
According to rate, the TX_RAM line number in the TX_RAM array is determined, and the TX_ is formed according to identified TX_RAM line number
Array ram.
Wherein, described that the BIP treated data are sent into before SERDES, further includes: by the BIP, treated
Data carry out scrambling processing.
A kind of method that high-bit width data are transmitted between FPGA piece, comprising:
The receiving end random access memory RX_RAM array of second FPGA will be written from the data of SERDES PCS interface,
RX_RAM line number in the RX_RAM array matches with the line rate of the SERDES, PCS interface data bit width；
Data are read according to column from the RX_RAM array of second FPGA, and delete lowest byte in the data
Control code word or check code word.
Wherein, described by before the RX_RAM array that second FPGA is written in the data of SERDES PCS interface, it goes back
It include: the data progress scramble process by described from SERDES PCS interface.
Wherein, it is described by from the data of SERDES PCS interface be written second FPGA RX_RAM array when, also wrap
It includes: the data from SERDES PCS interface is subjected to BIP verification, the BIP check code word that the road Bing Yusui is sent carries out pair
Than to monitor whether transmission process mistake occurs.
Wherein, described by before the RX_RAM array that second FPGA is written in the data of SERDES PCS interface, it goes back
It include: that the RX_RAM is determined according to the line rate of current SERDES, PCS interface data bit width and data to be transmitted rate
RX_RAM line number in array, and the RX_RAM array is formed according to identified RX_RAM line number.
Wherein, the receiving end random access memory that second FPGA will be written from the data of SERDES PCS interface
Before RX_RAM array, further includes: whether judge receives link according to the data of PCS interface output and K code indication signal
Into synchronous regime, the data from SERDES PCS interface are received after entering synchronous regime；It is come from by described in
The data of SERDES PCS interface carry out byte-aligned adjustment, and K code is adjusted to lowest byte.
A kind of FPGA for supporting high-bit width data to transmit, comprising:
Data frame generation module, includes transmitting terminal random access memory TX_RAM array, the TX_ in the TX_RAM array
RAM row number matches with the line rate of current SERDES, PCS interface data bit width；For by parallel data and control to be sent
Code word processed is packaged composition data burst and is simultaneously written in the TX_RAM array, and by the data burst in the TX_RAM array
By column be unit according to time division multiplexing tdm in a manner of timesharing press row Sequential output；
Bit interleaved parity BIP generation module, it is for being handled by BIP that the data frame generation module is suitable by row
Control code word is changed to the BIP check code word of a subframe in the data of sequence output, by the BI P treated data feeding
SERDES, to be sent to other FPGA after SERDES parallel-serial conversion.
Wherein, further includes: scrambling module, for by the BIP, treated that data carry out scrambling processing, and will be at scrambling
Data after reason are sent into SERDES, to be sent to other FPGA after SERDES parallel-serial conversion.
A kind of FPGA for supporting high-bit width data to transmit, comprising: data frame analyzing module includes receiving end random access memory
RX_RAM array, line rate, PCS interface data bit width phase of the RX_RAM line number with the SERDES in the RX_RAM array
Matching, for the RX_RAM array being written from the data of SERDES PCS interface, and from second FPGA's
In RX_RAM array according to column read data, and delete lowest byte in the data control code word or check code word after it is defeated
Out.
Wherein, further includes: descrambling module, after the data from SERDES PCS interface are carried out scramble process
It is sent into the data frame analyzing module.
Wherein, further includes: BIP parsing module, for the data from SERDES PCS interface to be carried out the school BIP
It tests, the BIP check code word that the road Bing Yusui is sent compares, to monitor whether transmission process mistake occurs.
Wherein, further includes: K code synchronization module, data and K code indication signal for being exported according to the PCS interface are sentenced
Whether disconnected receives link enters synchronous regime, and the data from SERDES PCS interface are received after entering synchronous regime；K
K code is adjusted to minimum for the data from SERDES PCS interface to be carried out byte-aligned adjustment by code alignment module
Byte, and data adjusted are output to the data frame analyzing module or the descrambling module.
The device that high-bit width data are transmitted between a kind of FPGA piece, comprising: first FPGA, SERDES and second
FPGA, wherein the Physical Coding Sublayer PCS that first FPGA and second FPGA are separately connected the SERDES connects
Mouthful；
First FPGA includes transmitting terminal random access memory TX_RAM array, the TX_RAM in the TX_RAM array
Line number matches with the line rate of the SERDES, PCS interface data bit width, is configured to high-bit width data between executing FPGA piece and passes
Defeated program is to execute the operation of the above method；
Second FPGA includes receiving end random access memory RX_RAM array, the RX_RAM in the RX_RAM array
Line number matches with the line rate of the SERDES, PCS interface data bit width, is configured to high-bit width data between executing FPGA piece and passes
Defeated program is to execute the operation of the above method；
The SERDES, for be output to described the after carrying out parallel-serial conversion from the data of first FPGA
Two FPGA.
The application can at least obtain following technical effect:
On the one hand, line rate, the PCS interface data bit width phase by data burst write-in TX_RAM line number with current SERDES
Matched TX_RAM array, then from the TX_RAM array by column be unit according to time division multiplexing tdm in a manner of timesharing by row sequence
Output data realizes the adjust automatically of data frame structure by adjusting the TX_RAM line number in TX_RAM array, do not need needle
Different SERDES line rates are configured with different framing devices, it is not only at low cost, but also be adaptable under a variety of SERDES rates
The application scenarios that data are transmitted between FPGA piece.
On the other hand, using data to be sent and control code word framing, in this way, the present embodiment is compared to the relevant technologies, into
One step reduces framing difficulty, and so as to the application scenarios transmitted suitable for data between a variety of FPGA pieces, versatility is higher.
Another aspect, code word will be controlled by being handled using BIP in the data by row Sequential output is changed to a upper subframe
BIP check code word, provide transmission link on-line testing function, improve data transmission reliability, be applicable to a variety of
The application scenarios that data are transmitted between FPGA piece, versatility are higher.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by specification, right
Specifically noted structure is achieved and obtained in claim and attached drawing.
Detailed description of the invention
Attached drawing is used to provide to further understand technical solution of the present invention, and constitutes part of specification, with this
The embodiment of application technical solution for explaining the present invention together, does not constitute the limitation to technical solution of the present invention.
Fig. 1 is the method flow schematic diagram that high-bit width data are transmitted between FPGA piece in embodiment one；
Fig. 2 is the exemplary diagram of the application data frame structure；
Fig. 3 is the composed structure schematic diagram that the FPGA of high-bit width data transmission is supported in embodiment one；
Fig. 4 is the method flow schematic diagram that high-bit width data are transmitted between FPGA piece in embodiment two；
Fig. 5 is the composed structure schematic diagram that the FPGA of high-bit width data transmission is supported in embodiment two；
Fig. 6 is the composed structure schematic diagram for the device that high-bit width data are transmitted between FPGA piece in embodiment three；
Fig. 7 is the exemplary structure schematic diagram for the device that high-bit width data are transmitted between FPGA piece in embodiment three；
Fig. 8 is the schematic diagram for the exemplary execution process that high-bit width data are transmitted between FPGA piece in embodiment three.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
Step shown in the flowchart of the accompanying drawings can be in a computer system such as a set of computer executable instructions
It executes.Also, although logical order is shown in flow charts, and it in some cases, can be to be different from herein suitable
Sequence executes shown or described step.
For needing difference under the SERDES line rate either supported in the related technology is single or different SERDES rates
The technical issues of framing device, present applicant proposes following technical solutions.In the application, RAM row number and current SERDES are utilized
Line rate, the array ram (for example, TX_RAM array, RX_RAM array) that matches of PCS interface data bit width realize FPGA piece
Between high-bit width data transmit, it is not only at low cost, but also be adaptable under a variety of SERDES rates that data between FPGA piece transmit answers
Use scene.
The technical solution of the application is described in detail below.
Embodiment one
A kind of method that high-bit width data are transmitted between FPGA piece, as shown in Figure 1, may include:
Step 101, parallel data to be sent in first FPGA and control code word packing group at data burst and are write
Enter in transmitting terminal random access memory (TX_RAM, Transmitter Xlane random access memory) array, it is described
The line rate of TX_RAM line number and current SERDES in TX_RAM array, Physical Coding Sublayer (PCS, Physical Code
Sublayer) interface data bit wide matches；
Step 102, by the data burst in the TX_RAM array to arrange as unit according to time division multiplexing (TDM, Time
Division Multiplex) mode timesharing press row Sequential output；
Step 103, it is handled by bit interleaved parity (BIP, Bit Interleaved Parity) and is pressed by described in
The BIP check code word that code word is changed to a subframe is controlled in the data of row Sequential output；
Step 104, the BIP treated data are sent into SERDES, to be sent to the after SERDES parallel-serial conversion
Two FPGA.
In the present embodiment, by line rate, the PCS interface data bit of data burst write-in TX_RAM line number and current SERDES
The TX_RAM array that width matches, then from the TX_RAM array by column be unit according to time division multiplexing tdm in a manner of timesharing by row
Sequential output data realize the automatic of data frame structure and data capacity by adjusting the TX_RAM line number in TX_RAM array
Adjustment does not need to configure different framing devices for different SERDES line rates, not only at low cost, but also is adaptable to a variety of
The application scenarios that data are transmitted between FPGA piece under SERDES rate.
In the present embodiment, using data to be sent and control code word (for example, K28.5 code word) framing, in this way, the present embodiment
Compared to the relevant technologies, framing difficulty further reduced, so as to the applied field transmitted suitable for data between a variety of FPGA pieces
Scape, versatility are higher.
In the present embodiment, the BIP that control code word is changed to a upper subframe in the data by row Sequential output is verified
Code word, so that the K numeral frame is converted to non-K numeral frame, to execute subsequent processing.Wherein, the data burst is divided into two kinds
Type: K numeral frame and non-K numeral frame.
In the present embodiment, also code word will be controlled using BIP processing in the data by row Sequential output and be changed to upper one
The BIP check code word of subframe provides transmission link on-line testing function, improves the reliability of data transmission, is applicable to
The application scenarios that data are transmitted between a variety of FPGA pieces, versatility are higher.
In practical applications, the chip module operation clock integrated in FPGA prototype system is faster, and platform service efficiency is got over
Height, but be transmitted through between FPGA piece SERDES carrying data bit width it is lower, the SERDES number needed in system is more.In FPGA
SERDES line rate be XGbps, using 8B/10B coding mode, PCS interface data bit width is L bit, data to be transmitted speed
Rate is YGbps, then the TX_RAM line number N of TX_RAM array is (X*0.8/Y)/L, and wherein N is the integer greater than 0, and SERDES is logical
Road can carry data bit width W equal to N*L-8, and the present embodiment can meet any type of number under module working frequency to be measured as a result,
According to transmission, such as interrupts, resets.
In the present embodiment, the data bit width of each TX_RAM and the Physical Coding Sublayer of SERDES in the TX_RAM array
PCS interface data bit width matches.
In the present embodiment, the length of data burst is N*L bit, and N is the TX_RAM line number of TX_RAM array, and L is
The PCS interface data bit width of SERDES.In this way, by the way that the TX_RAM line number of the length of data burst and TX_RAM array is closed
Connection can make data frame structure change and adjust automatically with the TX_RAM line number of TX_RAM array, to be adaptable to a variety of
The application scenarios that data are transmitted between FPGA piece under SERDES rate.
To adapt to a variety of SERDES line rates, the data frame that the present embodiment the method uses includes three types data: K
Code (for example, can be K28.5 code word), BIP check code word, data to be sent.In a kind of implementation, as shown in Fig. 2, this reality
Applying the data frame that the method uses may include a data burst of C_K_DIS (parameter is greater than 0 integer), at least 1
A K numeral frame and several BIP subframes.It only include a K numeral frame in data frame when C_K_DIS is 1.Each data
Subframe is made of N*L bit, and N is the TX_RAM line number of TX_RAM array, and L is the PCS interface data bit width of SERDES, data
First character section is K code or BIP check code word in frame.
In the present embodiment, realize the TX_RAM array mode can there are many.It is described by a kind of implementation
Parallel data to be sent and control code word packing group are at data burst and before being written in TX_RAM array in a piece of FPGA, also
It may include: that the TX_ is determined according to the line rate of current SERDES, PCS interface data bit width and data to be transmitted rate
TX_RAM line number in array ram, and the TX_RAM array is formed according to identified TX_RAM line number.
In the present embodiment, it is described the BIP treated data are sent into SERDES before, can also include: will be described
Treated that data carry out scrambling processing by BIP.In this way, the reliable of transmission link can be improved by the scrambling for increasing data
Property.
Correspondingly, the present embodiment also provides a kind of FPGA for supporting high-bit width data to transmit, as shown in figure 3, may include:
Data frame generation module 31, includes transmitting terminal random access memory TX_RAM array, the TX_ in the TX_RAM array
RAM row number matches with the line rate of current SERDES, PCS interface data bit width；For by parallel data and control to be sent
Code word processed is packaged composition data burst and is simultaneously written in the TX_RAM array, and by the data burst in the TX_RAM array
By column be unit according to time division multiplexing tdm in a manner of timesharing press row Sequential output；
BIP generation module 32, for being handled the data frame generation module by BIP by the data of row Sequential output
Control code word is changed to the BIP check code word of a subframe, by the BI P treated data feeding SERDES, so as to
Other FPGA are sent to after SERDES parallel-serial conversion.
In a kind of implementation, above-mentioned FPGA can also include: scrambling module 33, for by the BIP treated number
According to carrying out scrambling processing, and will scrambling treated that data are sent into SERDES, to be sent to other after SERDES parallel-serial conversion
FPGA。
FPGA described in the present embodiment can realize all of high-bit width data transmission method between FPGA piece described in the present embodiment
Details can refer to the record of method above, repeat no more.
The PCS for supporting the FPGA of high-bit width data transmission that can connect the hard IP of SERDES in practical application, in the present embodiment is patrolled
Side interface is collected, is sent into SERDES by the data that the PCS logic side interface completes processing.
In practical application, each module is supported in the FPGA of high-bit width data transmission to may respectively be software, hard in the present embodiment
The combination of part or both is responsible for implementing function such as:
Data frame generation module 31 includes above-mentioned TX_RAM array, is mainly responsible for and realizes data to be sent and control code word
Merging, parallel data to be sent parallel-serial conversion and across clock and conversion function, parallel high-bit width data to be sent are turned
At with the matched data frame of PCS interface data bit width.By adjusting the TX_RAM line number of TX_RAM array, can support a variety of
SERDES line rate.
Scrambling module 33 is responsible for scrambling data according to given seed by data frame head of K code, completes to be sent
The pseudorandom permutation of data reduces continuous " 0 ", " 1 " appearance, dispersion power spectrum etc., to enhance the reliability of data transmission.
BIP generation module can be responsible for generating the BIP check code word of data burst and according to the type of data burst selectivity
It replaces it and controls code word, to realize the online fault monitoring function of FPGA, the reliability of improve data transfer.
It should be noted that data frame generation module 31 turns data polarity parallel-serial conversion to be sent and cross clock domain
It changes, it is therefore an objective to be matched with PCS interface；SERDES is responsible for carrying out PCS interface data into parallel-serial conversion and cross clock domain conversion, purpose
It is to match with SERDES hardware transport line.
Embodiment two
A kind of method that high-bit width data are transmitted between FPGA piece, as shown in figure 4, may include:
Step 401, the receiving end random access memory of second FPGA will be written from the data of SERDES PCS interface
(RX_RAM, Receiver Xlane random access memory) array, the RX_RAM line number in the RX_RAM array
Match with the line rate of the SERDES, PCS interface data bit width；
Step 402, data are read according to column from the RX_RAM array of second FPGA, and deleted in the data
It is exported after the control code word or check code word of lowest byte.
In the present embodiment, by line rate, the PCS interface data bit of data burst write-in RX_RAM line number and current SERDES
The RX_RAM array that width matches, then to arrange for unit output data, by adjusting RX_RAM array from the RX_RAM array
In TX_RAM line number realize the adjust automatically of data frame structure and data capacity, do not need for different SERDES line rates
Different framing devices is configured, it is not only at low cost, but also it is adaptable under a variety of SERDES rates what data between FPGA piece were transmitted
Application scenarios.
In a kind of implementation, the RX_RAM battle array that second FPGA will be written from the data of SERDES PCS interface
It can also include: the data progress scramble process by described from SERDES PCS interface before column.In this way, by increasing number
According to descrambling function, the reliability of transmission link can be improved.
In the present embodiment, the RX_RAM array that second FPGA will be written from the data of SERDES PCS interface
When, it can also include: the data progress BIP verification by described from SERDES PCS interface, the BIP verification that the road Bing Yusui is sent
Code word compares, to monitor whether transmission process mistake occurs.In this way, providing transmission link on-line testing function by BIP
Can, the reliability of data transmission is improved, the application scenarios of data transmission between a variety of FPGA pieces are applicable to, versatility is higher.
In the present embodiment, realize the RX_RAM array mode can there are many.In a kind of implementation, the future
It can also include: according to current before the RX_RAM array of second FPGA is written from the data of SERDES PCS interface
Line rate, PCS interface data bit width and the data to be transmitted rate of SERDES, determines the RX_RAM in the RX_RAM array
Line number, and the RX_RAM array is formed according to identified RX_RAM line number.
In a kind of implementation, it is described will be written from the data of SERDES PCS interface the receiving end of second FPGA with
It can also include: the data and the judgement of K code indication signal according to PCS interface output before machine memory RX_RAM array
Whether receives link enters synchronous regime, and the data from SERDES PCS interface are received after entering synchronous regime；It will
The data from SERDES PCS interface carry out byte-aligned adjustment, and K code is adjusted to lowest byte.
To adapt to a variety of SERDES line rates, data frame used in method described in the present embodiment includes three types number
According to: K code (for example, K28.5 code word), BIP check code word, data to be sent.In a kind of implementation, as shown in Fig. 2, every number
According to frame may include a data burst of C_K_DIS (parameter be greater than 0 integer), at least one K numeral frame and several
BIP subframe.It only include a K numeral frame in data frame when C_K_DIS is 1.Each data burst is made of N*L bit, N
For the RX_RAM line number of RX_RAM array, L is the PCS interface data bit width of SERDES, and first character section is K code in data burst
Or BIP check code word.
Correspondingly, the present embodiment also provides a kind of FPGA for supporting high-bit width data to transmit, as shown in figure 5, may include:
Data frame analyzing module 51, includes receiving end random access memory RX_RAM array, the RX_ in the RX_RAM array
RAM row number matches with the line rate of the SERDES, PCS interface data bit width, for will be from SERDES PCS interface
The RX_RAM array is written in data, and reads data according to column from the RX_RAM array of second FPGA, and delete
Except being exported after the control code word of lowest byte or check code word in the data.
In a kind of implementation, the FPGA of above-mentioned support high-bit width data transmission can also include: BIP parsing module 52,
For the data from SERDES PCS interface to be carried out BIP verification, the BIP check code word that the road Bing Yusui is sent is carried out pair
Than to monitor whether transmission process mistake occurs.
In a kind of implementation, the FPGA of above-mentioned support high-bit width data transmission can also include: descrambling module 53, be used for
The data frame analyzing module is sent into after the data from SERDES PCS interface are carried out scramble process.
In a kind of implementation, the FPGA of above-mentioned support high-bit width data transmission can also include:
K code synchronization module 54, data and K code indication signal for being exported according to the PCS interface judge receives link
Whether enter synchronous regime, the data from SERDES PCS interface are received after entering synchronous regime；
K code alignment module 55, for the data from SERDES PCS interface to be carried out byte-aligned adjustment, by K
Code is adjusted to lowest byte, and data adjusted are output to the data frame analyzing module 51 or the descrambling module 53.
FPGA described in the present embodiment can realize all of high-bit width data transmission method between FPGA piece described in the present embodiment
Details can refer to the record of method above, repeat no more.
The PCS for supporting the FPGA of high-bit width data transmission that can connect the hard IP of SERDES in practical application, in the present embodiment is patrolled
Side interface is collected, the data of the PCS logic side interface after SERDES parallel-serial conversion are passed through.
In practical application, each module is supported in the FPGA of high-bit width data transmission to may respectively be software, hard in the present embodiment
The combination of part or both is responsible for implementing function such as:
Data frame analyzing module 51 includes above-mentioned RX_RAM array, is mainly responsible for and reads and writes ground by RX_RAM antenna array control
The frame decoding format function for receiving data is realized in location, deletes control code word (for example, K28.5), BIP check code word etc. in subframe
And the data that parsing obtains are exported, data frame analyzing module 51 can be supported not by adjusting the RX_RAM line number in RX_RAM array
With SERDES line rate application scenarios.
BIP verification parsing module 52 is mainly responsible for realization reception subframe BIP check code word calculating and BIP check results are sentenced
Disconnected function, so that the BIP verification of data (for example, data after descrambling) is realized, to monitor whether transmission process mistake occurs.
Descrambling module 53 can be responsible for parsing the data received by that will receive data solution pseudo-random process.Actually answer
In, descrambling module 53 and scrambling module 33 occur in pairs.In this way, increasing scrambling code function, it can reduce and continuously to occur in transmission
" 0 ", " 1 " sequence disperses power spectrum, to enhance the reliability of data transmission.
K code synchronization module 54 is mainly responsible for the synchronizing function for realizing receiving end link, is connect by the realization of K code detecting state machine
Receive the synchronous detection of link state；
K code alignment module 55 is mainly responsible for the function of realizing that K code position is adjusted to lowest byte (for example, 32bit).
Embodiment three
As shown in fig. 6, providing the device that high-bit width data are transmitted between a kind of FPGA piece, comprising: first FPGA 61,
SERDES 62 and second FPGA 63, wherein first FPGA 61 and second FPGA 63 are separately connected
The Physical Coding Sublayer PCS interface of the SERDES 62；
First FPGA 61 includes TX_RAM array, the TX_RAM line number in the TX_RAM array with it is described
The line rate of SERDES, PCS interface data bit width match, and high-bit width data distributing program is between being configured to execution FPGA piece to hold
The operation of one the method for row embodiment；
Second FPGA 63 includes receiving end random access memory RX_RAM array, the RX_ in the RX_RAM array
RAM row number matches with the line rate of the SERDES, PCS interface data bit width, is configured to high-bit width number between execution FPGA piece
The operation of two the method for embodiment is executed according to transfer program；
The SERDES 62 can be used for after carrying out parallel-serial conversion from the data of first FPGA 61 exporting
To second FPGA 63.
In a kind of implementation, the Physical Coding Sublayer of first hard IP of the connection of FPGA 61 SERDES 62 (PCS,
Physical Code Sublayer) logic side interface, by the PCS logic side interface by data be sent into SERDES 62, with into
Row parallel-serial conversion.The PCS logic side interface of second hard IP of the connection of FPGA 63 SERDES 62, the PCS of the hard IP of SERDES 62 are patrolled
It collects side interface and the data after parallel-serial conversion is output to second FPGA 63.
As shown in fig. 7, the schematic diagram for the device exemplary structure that high-bit width data are transmitted between FPGA piece in the present embodiment.
Wherein, first FPGA 61 includes data frame generation module 31, BIP verification generation module 32 and scrambling module 33, and second
FPGA 63 may include data frame analyzing module 51, BIP verification parsing module 52, descrambling module 53, K code synchronization module 54, K
Code alignment module 55.
Wherein, data frame generation module 31 can be responsible for realizing data to be sent and K code character frame, data across clock and conversion,
Subframe timesharing output function；
BIP verification generation module 32 can be responsible for according to the input data, calculating BIP check code word, and more according to frame structure
The control code word of new subframe.
Scrambling module 33 can be responsible for scrambling data according to given seed using K code as data frame head, enhance data
Transmission reliability.
Data frame analyzing module 51 is mainly made of RX_RAM, can be responsible for realizing data across clock and conversion, serioparallel exchange
And control code word or BIP code word delete function.
BIP verification parsing module 52 can be responsible for data after descrambling and carry out BIP verification, and send with first FPGA with road
BIP check code word compare, monitoring transmission process whether there is mistake.
Descrambling module 53 can be responsible for the data for exporting K code alignment module and carry out scramble process.
Whether the data and K code indication signal that K code synchronization module 54 can be responsible for being exported according to PCS interface judge receives link
Into synchronous regime, PCS output data is exported after entering synchronous regime.
K code alignment module 55 can be responsible for the data for exporting PCS interface and carry out byte-aligned adjustment, and K code is adjusted to most
Low byte.
Correspondingly, the present embodiment also provides the method that high-bit width data between a kind of FPGA piece are transmitted, may include:
The first step, by parallel data to be sent in first FPGA and control code word packing group at data burst, and by institute
State data burst write-in TX_RAM array；
Second step, by data are suitable by row according to TDM mode timesharing to arrange as unit in TX_RAM array in first FPGA
Sequence output；
Third step is handled by BIP by the control code in its non-K numeral frame for the data by row Sequential output
Word is changed to the BIP check code word of a subframe, and carries out scrambling processing；
4th step, first FPGA will scramble that treated data are output to SERDES, after SERDES carries out parallel-serial conversion
Transmit that data to second FPGA；
5th step, second FPGA receive the data from SERDES, RX_RAM times are sequentially written in after scramble process
Column, while BIP verification is carried out, the BIP check code word that the road Bing Yusui is sent compares, to monitor whether transmission process mistake occurs
Accidentally.
6th step reads data according to column from the RX_RAM array of second FPGA, deletes in the data most
It is output to after the control code word or check code word of low byte in other modules of second FPGA.
A kind of implementation, it is above-mentioned by completing upper sub-frame data verification and the calculating realization of this sub-frame data check code word
BIP verification.
The specific implementation process of the present embodiment is described in detail below.
The device that high-bit width data are transmitted between FPGA piece in the present embodiment executes the mistake of high-bit width data transmission between FPGA piece
Journey can be realized using process as shown in Figure 8.It should be noted that Fig. 8 is merely illustrative implementation, it can in practical application
The execution sequence of details therein or step is adjusted as needed, in this regard, herein with no restriction.
As shown in figure 8, the execution process that high-bit width data are transmitted between FPGA piece may include:
Step 801, first FPGA merges parallel data to be sent and control code word (for example, K28.5 code word) forms number
According to subframe, wherein the control codeword bit is in lowest byte；
Step 802, TX_RAM array is written into the data burst, and will be described under SERDES PCS interface clock domain
Data burst in TX_RAM array in a manner of arranging as unit according to TDM timesharing by line number (that is, TX_RAM in TX_RAM array
Line number) Sequential output since the first row；
Step 803, every in the data that TX_RAM array is exported to the data progress BIP processing of TX_RAM array output
Non- first subframe control code word of a data burst is changed to the BIP check code word of a subframe；
In this example, the data burst type of TX_RAM output is K numeral frame, is handled by BIP, will be non-in data frame
First subframe is changed to non-K numeral frame, i.e., control word in K numeral frame is replaced with BIP check code word.Here, the non-K code
Subframe is the data burst generated after the BIP check code word that the control code word in K numeral frame is replaced with to a upper data burst.
Step 804, by BIP, treated that data carry out scrambling processing；
Step 805, scrambling treated data by the PCS logic side interface of SERDES are output to SERDES, process
The parallel-serial conversion of SERDES is transferred to second FPGA.
Step 806, the data progress K code of the PCS logic side interface output of SERDES is synchronized in second FPGA, K code
The processing such as alignment, wherein when exporting after processing, K code bit is in lowest byte；
Step 807, treated that data descramble for K code is synchronous, K code alignment etc., the data in taking-up data burst；
Step 808, the data after descrambling are sequentially written in RX_RAM array, while carry out BIP processing to realize online mistake
Accidentally monitor；
Wherein, the first row RX_RAM of RX_RAM array in second FPGA is written in the data containing control code word.
Step 809, data are read according to column from the RX_RAM array of second FPGA, deletes Least Significant Character in the data
It is exported after the control code word or check code word of section.
In the present embodiment, data frame packet used in data transmission method between the FPGA piece of a variety of SERDES line rates is adapted to
Include three types data: K code (K28.5 code word), BIP check code word, data to be sent.As shown in Fig. 2, each data frame includes
A data burst of C_K_DIS (parameter is greater than 0 integer), at least one K numeral frame and several BIP subframes.Work as C_K_
It only include a K numeral frame in data frame when DIS is 1.Each data burst is made of N*L bit, and N is RAM row matrix ginseng
Number, L are the PCS interface data bit width of the hard IP of SERDES, and first character section is K code or BIP check code word in data burst.
The example implementations of the various embodiments described above are described in detail below.It should be noted that hereafter each reality
Example can any combination.Also, in practical applications, the various embodiments described above can also have other implementations, in Examples below
Each process, implementation procedure etc. can also be adjusted according to the needs of practical application.
Example 1
For specific example, SERDES line rate is 10Gbps, and using 8B/10B coding mode, PCS interface bit wide is
32bit, data to be transmitted clock are 0.01Ghz, then the RAM row number of array ram is 25, i.e. TX_RAM array in first FPGA
TX_RAM line number be 25, the RX_RAM line number of RX_RAM array is 25 in second FPGA, and the data bit width that can be carried is
792bit.(control code word is placed on Least Significant Character after 792bit data in first FPGA are merged with " 0xBC " (K28.5 code word)
Section), it is written in TX_RAM array, is stored by 32 byte orders, wherein minimum 32bit is first under data clock domain to be sent
Row, highest 32bit is in last line.Again under PCS interface clock domain, according in TX_RAM array each TX_RAM line number sequence,
The data of same column in 25 pieces of TX_RAM are successively taken out (because identical column form one in each row TX_RAM in TX_RAM array
A data burst), it is sent to BIP generation module, the scrambled resume module of data of BIP check information will be added, pass through PCS
Interface is output to SERDES, is sent to second FPGA by SERDES parallel-serial conversion.By the 32bit of SERDES serial conversion
Data export second FPGA by PCS interface, which is sent to BIP parsing mould by second FPGA after scramble process
Whether block, detection transmission process there is mistake.Meanwhile RX_RAM array is written into the data after descrambling, it will be with control code word
Or the first row RX_RAM of the data deposit RX_RAM array of check code word, remainder data is according to the RX_RAM in RX_RAM array
The incremental sequence of line number is sequentially written in each row RX_RAM.It is whole using 10Mhz Clockreading in the reading interface side of RX_RAM array
Column data deletes the lowest byte of data in the first row RX_RAM, extracts the data of first FPGA transmission.
When SERDES line rate can only support 6Gbps, RAM quantity is only revised as 15, data to be transmitted clock is still
0.01Gbps, data to be transmitted bit wide become 472bit, still can directly use in prototype system.
Example 2
FPGA in two blocks of prototype system plates passes through hot plug small package optical module (SFP, Small by 10G SERDES
Form-factor Pluggables) it is communicated, if PCS interface output data bit wide is 32bit, module work frequency to be tested
Rate is 25Mhz, then the RAM row number of array ram is 10, i.e. the TX_RAM line number of TX_RAM array is 10 in first FPGA, the
The RX_RAM line number of RX_RAM array is 10 in two FPGA, and carrying data bit width to be sent is 312.First FPGA will
312bit data with " 0xBC " be packaged composition data burst, under 25Mhz clock domain by the data burst be written TX_RAM array；
At PCS interface clock domain 250Mhz, successively data burst is opened from the first row by TX_RAM row sequence from TX_RAM array
Begin to read, the PCS interface of the hard IP of SERDES is transferred to by BIP generation module, scrambling module.Turn by the hard IP of SERDES and string
It changes, optical signal is converted by SFP and is transferred to by optical fiber in the SFP of another veneer, is input to SERDES by photoelectric conversion
In, it is output to second FPGA from PCS interface using serioparallel exchange, the receives link of second FPGA is extensive using clock data
The data that PCS interface exports are respectively written into the school BIP by the clock that multiple module (CDR, clock data recovery) is recovered
It tests in module and RX_RAM array；Pass through the 25Mhz clock that phaselocked loop (PLL, Phase Locked Loop) is generated using CDR
The data of same column in multirow RX_RAM in RX_RAM array are read, rejecting lowest byte is exported to be used to other modules.
Those of ordinary skill in the art will appreciate that all or part of the steps in the above method can be instructed by program
Related hardware (such as processor) is completed, and described program can store in computer readable storage medium, as read-only memory,
Disk or CD etc..Optionally, one or more integrated circuits also can be used in all or part of the steps of above-described embodiment
It realizes.Correspondingly, each module/unit in above-described embodiment can take the form of hardware realization, such as pass through integrated circuit
It realizes its corresponding function, can also be realized in the form of software function module, such as be stored in and deposited by processor execution
Program/instruction in reservoir realizes its corresponding function.The application is not limited to the knot of the hardware and software of any particular form
It closes.
The advantages of basic principles and main features and the application of the application have been shown and described above.The application is not by upper
The limitation for stating embodiment, the above embodiments and description only describe the principles of the application, are not departing from the application
Under the premise of spirit and scope, the application be will also have various changes and improvements, these changes and improvements both fall within claimed
Within the scope of the application.
Claims (16)
1. a kind of method that high-bit width data are transmitted between FPGA piece, comprising:
By parallel data to be sent in first FPGA with control code word packing group is at data burst and that transmitting terminal is written is random
In memory TX_RAM array, the line rate of TX_RAM line number and current SERDES in the TX_RAM array, PCS interface number
Match according to bit wide；
By the data burst in the TX_RAM array, timesharing is defeated by row sequence in a manner of arranging as unit according to time division multiplexing tdm
Out；
Code word will be controlled by being handled by bit interleaved parity BIP in the data by row Sequential output is changed to a upper son
The BIP check code word of frame；
The BIP treated data are sent into SERDES, to be sent to second FPGA after SERDES parallel-serial conversion.
2. the method according to claim 1, wherein in the TX_RAM array data bit width of each TX_RAM with
The Physical Coding Sublayer PCS interface data bit width of SERDES matches.
3. the method according to claim 1, wherein it is described by parallel data to be sent in first FPGA with
Code word packing group is controlled at data burst and before being written in TX_RAM array, further includes:
According to the line rate of current SERDES, PCS interface data bit width and data to be transmitted rate, determine TX_RAM gusts described
TX_RAM line number in column, and the TX_RAM array is formed according to identified TX_RAM line number.
4. the method according to claim 1, wherein described send the BIP treated data into SERDES
Before, further includes:
By the BIP, treated that data carry out scrambling processing.
5. a kind of method that high-bit width data are transmitted between FPGA piece, comprising:
The receiving end random access memory RX_RAM array of second FPGA will be written from the data of SERDES PCS interface, it is described
RX_RAM line number in RX_RAM array matches with the line rate of the SERDES, PCS interface data bit width；
Data are read according to column from the RX_RAM array of second FPGA, and delete the control of lowest byte in the data
Code word processed or check code word.
6. according to the method described in claim 5, it is characterized in that, described will be from the data of SERDES PCS interface write-in the
Before the RX_RAM array of two FPGA, further includes:
The data from SERDES PCS interface are subjected to scramble process.
7. according to the method described in claim 5, it is characterized in that, described will be from the data of SERDES PCS interface write-in the
When the RX_RAM array of two FPGA, further includes:
The data from SERDES PCS interface are subjected to BIP verification, the BIP check code word that the road Bing Yusui is sent carries out pair
Than to monitor whether transmission process mistake occurs.
8. according to the method described in claim 5, it is characterized in that, described will be from the data of SERDES PCS interface write-in the
Before the RX_RAM array of two FPGA, further includes:
According to the line rate of current SERDES, PCS interface data bit width and data to be transmitted rate, determine RX_RAM gusts described
RX_RAM line number in column, and the RX_RAM array is formed according to identified RX_RAM line number.
9. according to the described in any item methods of claim 5 to 8, which is characterized in that it is described will be from SERDES PCS interface
Data are written before the receiving end random access memory RX_RAM array of second FPGA, further includes:
Judge whether receives link enters synchronous regime according to the data of PCS interface output and K code indication signal, is entering
The data from SERDES PCS interface are received after synchronous regime；
The data from SERDES PCS interface are subjected to byte-aligned adjustment, K code is adjusted to lowest byte.
10. a kind of FPGA for supporting high-bit width data to transmit, comprising:
Data frame generation module, includes transmitting terminal random access memory TX_RAM array, the TX_RAM row in the TX_RAM array
Number matches with the line rate of current SERDES, PCS interface data bit width；For by parallel data and control code to be sent
Word is packaged composition data burst and is written in the TX_RAM array, and by the data burst in the TX_RAM array to arrange
Row Sequential output is pressed according to time division multiplexing tdm mode timesharing for unit；
Bit interleaved parity BIP generation module, it is for being handled by BIP that the data frame generation module is defeated by row sequence
Code word is controlled in data out and is changed to the BIP check code word of a subframe, by the BI P treated data feeding
SERDES, to be sent to other FPGA after SERDES parallel-serial conversion.
11. FPGA according to claim 10, which is characterized in that further include:
Scrambling module, for by the BIP treated data carry out scrambling processing, and will scrambling treated that data are sent into
SERDES, to be sent to other FPGA after SERDES parallel-serial conversion.
12. a kind of FPGA for supporting high-bit width data to transmit, comprising:
Data frame analyzing module, includes receiving end random access memory RX_RAM array, the RX_RAM row in the RX_RAM array
Number matches with the line rate of the SERDES, PCS interface data bit width, for writing the data from SERDES PCS interface
Enter the RX_RAM array, and reads data according to column from the RX_RAM array of second FPGA, and described in deletion
It is exported after the control code word of lowest byte or check code word in data.
13. FPGA according to claim 12, which is characterized in that further include:
Descrambling module, for being sent into the data frame solution after the data from SERDES PCS interface are carried out scramble process
Analyse module.
14. FPGA according to claim 12, which is characterized in that further include:
BIP parsing module, for the data from SERDES PCS interface to be carried out BIP verification, what the road Bing Yusui was sent
BIP check code word compares, to monitor whether transmission process mistake occurs.
15. 2 to 14 described in any item FPGA according to claim 1, which is characterized in that further include:
K code synchronization module, data and K code indication signal for being exported according to the PCS interface judge receives link whether into
Enter synchronous regime, the data from SERDES PCS interface are received after entering synchronous regime；
K code alignment module adjusts K code for the data from SERDES PCS interface to be carried out byte-aligned adjustment
The data frame analyzing module or the descrambling module are output to lowest byte, and by data adjusted.
16. the device that high-bit width data are transmitted between a kind of FPGA piece, comprising: first FPGA, SERDES and second FPGA,
Wherein, first FPGA and second FPGA is separately connected the Physical Coding Sublayer PCS interface of the SERDES；
First FPGA includes transmitting terminal random access memory TX_RAM array, the TX_RAM line number in the TX_RAM array
Match with the line rate of the SERDES, PCS interface data bit width, is configured to high-bit width data between executing FPGA piece and transmits journey
Sequence is to execute the operation such as any one of Claims 1-4 the method；
Second FPGA includes receiving end random access memory RX_RAM array, the RX_RAM line number in the RX_RAM array
Match with the line rate of the SERDES, PCS interface data bit width, is configured to high-bit width data between executing FPGA piece and transmits journey
Sequence is to execute the operation such as any one of claim 5 to 9 the method；
The SERDES, for being output to described second after carrying out parallel-serial conversion from the data of first FPGA
FPGA。
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110233708A (en) * | 2019-07-12 | 2019-09-13 | 中国电子科技集团公司第三十四研究所 | A kind of data transmit-receive speed adjust device and its operation method |
| CN111339018A (en) * | 2020-02-18 | 2020-06-26 | 济南浪潮高新科技投资发展有限公司 | System and method for high-speed data transmission with adjustable speed between FPGA (field programmable Gate array) board cards |
| CN112445659A (en) * | 2019-08-27 | 2021-03-05 | 烽火通信科技股份有限公司 | Method and system for realizing multi-protocol high-speed serdes test |
| CN112799983A (en) * | 2021-01-29 | 2021-05-14 | 广州航天海特系统工程有限公司 | Byte alignment method, device and equipment based on FPGA and storage medium |
| CN113676310A (en) * | 2021-07-29 | 2021-11-19 | 北京无线电测量研究所 | Data transmission device for radar system |
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| CN114024609A (en) * | 2021-11-11 | 2022-02-08 | 中国电子科技集团公司第三十八研究所 | Data composite time sequence transmission method based on SERDES |
| WO2022205560A1 (en) * | 2021-03-31 | 2022-10-06 | 德氪微电子(深圳)有限公司 | Millimeter-wave communication chip, and display apparatus and method |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102480334A (en) * | 2010-11-24 | 2012-05-30 | 中兴通讯股份有限公司 | Method and device for rate matching |
| CN102611522A (en) * | 2011-01-25 | 2012-07-25 | 中兴通讯股份有限公司 | Data reconstruction method and device |
| US20140022090A1 (en) * | 2012-07-17 | 2014-01-23 | Robert Bosch Gmbh | Method for Robust Wireless Monitoring and Tracking of Solar Trackers in Commercial Solar Power Plants |
| CN103716118A (en) * | 2012-09-28 | 2014-04-09 | 京信通信系统（中国）有限公司 | Self-adaption multi-rate data transmitting and receiving method and device |
| CN103873188A (en) * | 2012-12-13 | 2014-06-18 | 中兴通讯股份有限公司 | Parallel rate de-matching method and parallel rate de-matching device |
| US20150189047A1 (en) * | 2013-09-16 | 2015-07-02 | Annapurna Labs, LTD. | Generic data integrity check |
| CN105354160A (en) * | 2015-10-09 | 2016-02-24 | 中国科学院上海高等研究院 | Connecting method and system for communication between rate configurable FPGA chips |
-
2017
- 2017-08-22 CN CN201710725378.1A patent/CN109426636B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102480334A (en) * | 2010-11-24 | 2012-05-30 | 中兴通讯股份有限公司 | Method and device for rate matching |
| CN102611522A (en) * | 2011-01-25 | 2012-07-25 | 中兴通讯股份有限公司 | Data reconstruction method and device |
| US20140022090A1 (en) * | 2012-07-17 | 2014-01-23 | Robert Bosch Gmbh | Method for Robust Wireless Monitoring and Tracking of Solar Trackers in Commercial Solar Power Plants |
| CN103716118A (en) * | 2012-09-28 | 2014-04-09 | 京信通信系统（中国）有限公司 | Self-adaption multi-rate data transmitting and receiving method and device |
| CN103873188A (en) * | 2012-12-13 | 2014-06-18 | 中兴通讯股份有限公司 | Parallel rate de-matching method and parallel rate de-matching device |
| US20150189047A1 (en) * | 2013-09-16 | 2015-07-02 | Annapurna Labs, LTD. | Generic data integrity check |
| CN105354160A (en) * | 2015-10-09 | 2016-02-24 | 中国科学院上海高等研究院 | Connecting method and system for communication between rate configurable FPGA chips |
Non-Patent Citations (1)
| Title |
|---|
| 陈俊宇: "《一种专用可重构流水信号处理器的设计》", 《微电子学与计算机》 * |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110233708A (en) * | 2019-07-12 | 2019-09-13 | 中国电子科技集团公司第三十四研究所 | A kind of data transmit-receive speed adjust device and its operation method |
| CN110233708B (en) * | 2019-07-12 | 2023-12-29 | 中国电子科技集团公司第三十四研究所 | Data receiving and transmitting rate adjusting device and operation method thereof |
| CN112445659B (en) * | 2019-08-27 | 2023-07-21 | 烽火通信科技股份有限公司 | Multi-protocol high-speed serdes test implementation method and system |
| CN112445659A (en) * | 2019-08-27 | 2021-03-05 | 烽火通信科技股份有限公司 | Method and system for realizing multi-protocol high-speed serdes test |
| CN111339018A (en) * | 2020-02-18 | 2020-06-26 | 济南浪潮高新科技投资发展有限公司 | System and method for high-speed data transmission with adjustable speed between FPGA (field programmable Gate array) board cards |
| CN111339018B (en) * | 2020-02-18 | 2023-08-25 | 山东浪潮科学研究院有限公司 | High-speed data transmission system and method with adjustable rate between FPGA boards |
| WO2022022231A1 (en) * | 2020-07-31 | 2022-02-03 | 深圳市中兴微电子技术有限公司 | Writing method, reading method, processor chip, storage medium and electronic device |
| CN112799983A (en) * | 2021-01-29 | 2021-05-14 | 广州航天海特系统工程有限公司 | Byte alignment method, device and equipment based on FPGA and storage medium |
| WO2022205560A1 (en) * | 2021-03-31 | 2022-10-06 | 德氪微电子(深圳)有限公司 | Millimeter-wave communication chip, and display apparatus and method |
| CN113676310A (en) * | 2021-07-29 | 2021-11-19 | 北京无线电测量研究所 | Data transmission device for radar system |
| CN113676310B (en) * | 2021-07-29 | 2023-09-12 | 北京无线电测量研究所 | Data transmission device for radar system |
| CN113821463A (en) * | 2021-09-23 | 2021-12-21 | 深圳忆联信息系统有限公司 | PCIE controller verification method and device based on FPGA and computer equipment |
| CN114024609B (en) * | 2021-11-11 | 2023-06-20 | 中国电子科技集团公司第三十八研究所 | SERDES-based data composite time sequence transmission method |
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| CN117353873B (en) * | 2023-12-04 | 2024-02-13 | 科谱半导体(天津)有限公司 | Uplink frame verification method and device, electronic equipment and storage medium |
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