CN203896368U

CN203896368U - Dual-port test device provided with PXI board and used for POS protocol consistency testing

Info

Publication number: CN203896368U
Application number: CN201420120787.0U
Authority: CN
Inventors: 段美霞
Original assignee: North China University of Water Resources and Electric Power
Current assignee: North China University of Water Resources and Electric Power
Priority date: 2014-03-17
Filing date: 2014-03-17
Publication date: 2014-10-22
Anticipated expiration: 2024-03-17

Abstract

The utility model provides a dual-port test device provided with a PXI board and used for POS(IP over SDH) protocol consistency testing. The dual-port test device includes a bottom board, a front face board and a data analyzing board. A testing circuit is installed on the bottom board and the data analyzing board and includes a data sending buffer memory, a data receiving and capturing buffer memory, a CPU module, a PXI bus module, a power module, a clock generating module, a DPRAM module, an FPGA module, a POS interface module, a photoelectric converting module and a signal conditioning module. According to the utility model, problems that the quantity of testing boards is large since the testing boards with different rates are needed for POS protocol consistency testing at different rates and a testing device is complex are solved. When testing, only the photoelectric modules of different testing wavelengths and different testing rates are needed to change and different rates are set for interfaces through software, so that POS protocol consistency testing at different rates can be realized.

Description

The testing apparatus of the POS testing protocol consistency PXI board of dual-port

Technical field

The utility model relates to a kind of testing apparatus of POS testing protocol consistency PXI board of the device that POS link is tested, especially dual-port.

Background technology

POS (IP over SDH) technology refers to by SDH high-speed transfer passage and directly transmits IP grouping, POS technology is mainly used in transfer of data backbone network, use PPP peer-peer protocol that IP packet is mapped on SDH frame, transmit continuously by each the corresponding wire rate of group, its network is mainly formed by connecting via high speed fibre transmission channel by jumbo high-end router.This technology is actually the continuity to traditional IP concept, compatible traditional IP protocol architecture completely, the point-to-point physical connection just providing by SDH on physical channel, thereby make speed bring up to Gbit/s magnitude, POS technology will be all very important IP network transmission means now and from now on.POS link is tested and is necessary, POS link test is mainly comprised to the test of 2 aspects: be i.e. the test of the test of SDH layer and IP layer.

The problem existing is at present, the domestic panel assembly relevant to POS or instrument are all for communication aspects, for testing almost not having at present of aspect, existing test board device or instrument are exclusively used in IP test or for SDH test, want the test of SDH layer and the test of IP layer that in a 3U PXI panel assembly, complete multiple different rates to yet there are no Related product or report.

Utility model content

The purpose of this utility model is need to change when solving the test POS network performance of different rates and equipment thereof the test board device of different rates, has solved the synchronous problem of different link time tags.

The utility model solves the technical scheme that its technical problem adopts: the testing apparatus of the POS testing protocol consistency PXI board of dual-port, comprising: base plate, the front panel of installing on base plate and be arranged on equally the Data Analysis plate on base plate, wherein test circuit is arranged on base plate and Data Analysis plate, comprise and depositing, the data that send Frame send buffer memory, frames received certificate the data receiver of depositing are wherein caught buffer memory, CPU module, PXI bus module, power module and clock generation module, test circuit also comprises the photoelectric conversion module that can make mutual conversion between light signal and the signal of telecommunication, analog signal is transformed to the signal condition module of digital signal, for realizing the mapping of IP packet and SDH frame and going the pos interface module of shining upon, complete the FPGA module of the processing to SDH layer and IP layer data frame and expense, deposit the DPRAM module of the interaction data of local cpu and host computer, described pos interface module, data send buffer memory, data receiver is caught buffer memory, CPU module and is all connected with FPGA module, signal condition module connects photoelectric conversion module and pos interface module, DPRAM module connects CPU module and PXI bus module, and clock generation module connects pos interface module, FPGA module and CPU module, and power circuit connects whole modular circuit.

Further, described photoelectric conversion module is RTXM192-401 or RTXM159-403 or RTXM159-151.

Further, the interface chip in described pos interface module adopts many rate interfaces chip PM5360.

Further, 2 SFP sockets are installed on described base plate, 2 high-density sockets, 2 data transmission interfaces.

The utility model has solved the test board device that needs different rates due to different rates POS testing protocol consistency, and the test board device needs that cause are too much, testing equipment complexity, the nonsynchronous problem of clock between board, in the time of test, only need to change different test wavelengths, the optical-electric module of different test digit rates, the different rates of configuration interface on software, can realize the POS link protocol uniformity test to different rates.

The beneficial effects of the utility model are: only need a POS test board device, can complete STM-1, STM-4, POS testing protocol consistency on STM-16 different rates and uplink and downlink POS performance test, and do not need the POS test board device of polylith different rates, and having solved the nonsynchronous problem of the time clock being caused by plurality of plates device, testing equipment is simplified.

Brief description of the drawings

Fig. 1 is schematic block circuit diagram of the present utility model;

Fig. 2 is structural representation of the present utility model.

Embodiment

Below in conjunction with drawings and Examples, the utility model is further illustrated.

Fig. 1 is the circuit module design function block diagram of utility model, whole circuit module comprises: deposit, the data that send Frame send buffer memory, frames received certificate the data receiver of depositing are wherein caught buffer memory, CPU module, PXI bus module, power module and clock generation module, test circuit also comprises the photoelectric conversion module that can make mutual conversion between light signal and the signal of telecommunication, analog signal is transformed to the signal condition module of digital signal, for realizing the mapping of IP packet and SDH frame and going the pos interface module of shining upon, complete the FPGA module of the processing to SDH layer and IP layer data frame and expense, deposit the DPRAM module of the interaction data of local cpu and host computer, described pos interface module, data send buffer memory, data receiver is caught buffer memory, CPU module and is all connected with FPGA module, signal condition module connects photoelectric conversion module and pos interface module, DPRAM module connects CPU module and PXI bus module, and clock generation module connects pos interface module, FPGA module and CPU module, and power circuit connects whole modular circuit.

In Fig. 1, POS test board device mainly comprises the processing of circuit of data feedback channel and down going channel two aspects.In direction, IP data envelope is contained in SDH frame, then delivers in SDH transmission network; On receive direction, the IP packet being encapsulated in SDH frame is extracted to the frame overhead processing of delivering to protocol processing unit or carrying out SDH level.

On input direction; the light signal importing into from single mode or multimode fiber is sent into signal condition module after photoelectric conversion module conversion; signal condition module sends in pos interface module after analog signal is transformed to digital signal; complete Timing Processing, frame synchronization, go mapping; from incoming bit stream, extract SDH frame and and then recover PPP frame, and be cached in inner FIFO by interface.IP data processing module in FPGA module is by reading the FIFO of pos interface module, obtains PPP frame and also completes PPP relevant treatment, recovers IP message, protocol massages is further processed simultaneously, or real-time storage or carry out Data Matching identification.

On outbound course, the IP datagram literary composition sending completes protocol massages and is packaged into PPP frame in FPGA inside modules, then be sent to SDH interface treatment circuit, interface treatment circuit completes the mapping of payload to SDH frame, delivers to outside SDH network finally by electric light conversion by optical fiber.

In circuit, photoelectric conversion module is mainly realized the conversion between light signal and the signal of telecommunication.

The major function of pos interface module is exactly realize the mapping of IP packet and SDH frame and remove mapping process, mainly comprises: SDH frame is gone expense and tears frame processing open, and output SDH network management information also extracts PPP frame; Taking PPP frame data as payload, add SDH frame overhead information, form SDH frame and send.

In the utility model, interface process chip has adopted many rate interfaces chip PM5360.PM5360 is the solution serial chip of SONET OC48/ OC12/ OC3 interface, carries out string conversion and frame measuring ability, adds descrambling function.PM5360 converts the serial data code stream that is up to 2.488Gb/s receiving to low-speed parallel byte code stream.Its work mainly comprises that serial input, string conversion, frame detect and the output of 32 parallel-by-bits, and supports the line loopback that sends to the diagnosis loopback of reception and receive transmission simultaneously, can support at most up to 4 road STM-16 frame data transmitting-receivings.

FPGA module is the nucleus module place of testing apparatus, in FPGA module, complete the processing to SDH layer and IP layer data frame and expense, comprise mapping, go mapping, multiplexing, demultiplexing, IP data framing, separate frame, emulation etc., also comprise the linear speed of data is occurred, catches processing etc. in real time, in the utility model, test rate is the highest can support 2.488Gb/s data flow.

DDR3 memory bar is as receiving data capture buffer memory, during the frame data of reception are stored in so that next step processing.

Data send buffer memory and adopt synchronous SRAM to deposit transmission Frame to realize reading fast of hardware.

What CPU module realized is the first cumulative of control to bottom register and statistics, realizes mutual with PXI bus, complete bottom data and PXI bus host side alternately.

In DPRAM module, deposit the interaction data of local cpu and host computer.

Power module adopts LM6416 power circuit and produces the needed 1.2V of this test board device, 1.8V, 2.5V, 3.3V power supply.

Clock generation module produces the needed clock signal of this testing apparatus, comprise the needed 12M clock of CPU and the needed 50M of FPGA module, 125M, 200M clock, clock is except with active High Precision Crystal Oscillator, the 33M clock that has also used PXI bus module to provide.

Fig. 2 is structural design block diagram of the present utility model, and the utility model is mainly made up of two circuit boards, and Data Analysis plate 2 and base plate 3 form.Data Analysis plate 2 comprises FPGA module, and data send buffer memory, data receiver trapping module, CPU module; Base plate 3 comprises power module, signal condition module, PXI bus module.

In embodiment illustrated in fig. 2,1, two SFP socket of front panel to be installed on base plate and to be also arranged on base plate 3, the differential data line after opto-electronic conversion is delivered in the FPGA on Data Analysis plate 2 and is resolved by high-density socket X1.On whole plate, data are undertaken by P1 and P2 mouth and PXI bus alternately.Photoelectric conversion module has been selected the RTXM192-401(2.5G photoelectricity/electrooptic conversion module of Wuhan Telecommunication Devices Co., Ltd), RTXM159-403(622M photoelectricity/electrooptic conversion module) and RTXM159-151(155M photoelectricity/electrooptic conversion module); when test, only need to select different photoelectric conversion modules; adopt single mode or the multimode fiber of coupling; circuit automatically switches to the test channel circuit of coupling; software selects different speed that control is set automatically, can realize the POS link protocol uniformity test to different rates.The utility model adopts dual-port structure, makes can adopt same clock to carry out homology time tag counting, the clock synchronization issue of having avoided different panel assemblies to solve to two communication links in the design of FPGA module time tag.

Claims

1. a testing apparatus for the POS testing protocol consistency PXI board of dual-port, comprising: base plate, the front panel of installing on base plate and be arranged on equally the Data Analysis plate on base plate, wherein test circuit is arranged on base plate and Data Analysis plate, comprise and depositing, the data that send Frame send buffer memory, frames received certificate the data receiver of depositing are wherein caught buffer memory, CPU module, PXI bus module, power module and clock generation module, it is characterized in that: test circuit also comprises the photoelectric conversion module that can make mutual conversion between light signal and the signal of telecommunication, analog signal is transformed to the signal condition module of digital signal, for realizing the mapping of IP packet and SDH frame and going the pos interface module of shining upon, complete the FPGA module of the processing to SDH layer and IP layer data frame and expense, deposit the DPRAM module of the interaction data of local cpu and host computer, described pos interface module, data send buffer memory, data receiver is caught buffer memory, CPU module and is all connected with FPGA module, signal condition module connects photoelectric conversion module and pos interface module, DPRAM module connects CPU module and PXI bus module, and clock generation module connects pos interface module, FPGA module and CPU module, and power circuit connects whole modular circuit.

2. the testing apparatus of the POS testing protocol consistency PXI board of dual-port according to claim 1, is characterized in that: described photoelectric conversion module is RTXM192-401 or RTXM159-403 or RTXM159-151.

3. the testing apparatus of the POS testing protocol consistency PXI board of dual-port according to claim 1, is characterized in that: the interface chip in described pos interface module adopts many rate interfaces chip PM5360.

4. the testing apparatus of the POS testing protocol consistency PXI board of dual-port according to claim 2, is characterized in that: 2 SFP sockets are installed, 2 high-density sockets, 2 data transmission interfaces on base plate.