CN207560149U - The fibre-optic transmission system (FOTS) of linear array camera image acquisition is realized based on FPGA - Google Patents
The fibre-optic transmission system (FOTS) of linear array camera image acquisition is realized based on FPGA Download PDFInfo
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- CN207560149U CN207560149U CN201721636178.0U CN201721636178U CN207560149U CN 207560149 U CN207560149 U CN 207560149U CN 201721636178 U CN201721636178 U CN 201721636178U CN 207560149 U CN207560149 U CN 207560149U
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Abstract
The utility model is related to optical communication technology field more particularly to a kind of fibre-optic transmission system (FOTS)s that linear array camera image acquisition is realized based on FPGA.Including transmitting terminal and receiving terminal, the transmitting terminal includes 2 route array cameras, transmitting terminal fpga chip, crystal oscillator and transmitting terminal optical module, the input terminal of the transmitting terminal fpga chip is connected respectively with the 2 route array camera, and output terminal is connect with the transmitting terminal optical module；The receiving terminal includes host computer, receiving terminal fpga chip, crystal oscillator and receiving terminal optical module, and the input terminal of the receiving terminal fpga chip connect with the receiving terminal optical module, and the transmitting terminal optical module is connect with institute receiving terminal optical module by optical fiber.By the function that completion could be realized using special chip in FPGA, the remote transmission of line-scan digital camera Camera link interface signals can be realized, it is stable, reliable, easy to operate, easy to maintain, reach design requirement.
Description
Technical field
The utility model is related to optical communication technology fields more particularly to a kind of FPGA that is based on to realize linear array camera image acquisition
Fibre-optic transmission system (FOTS).
Background technology
Line-scan digital camera scans object using single beam line, can ensure the accurate of scanning result in quickly scanning object,
Therefore extensive purposes is obtained in industrial circle, the occasion in some needs high-precision scannings can be applied.Line-scan digital camera one
As using Camera link interfaces transmit image information.Camera link interfaces are a kind of high-speed figure camera and Image Acquisition
Communication interface between card passes through the parallel LVDS signal transmitted datas of multipath high-speed, Camera link interface data wire transmission ranges
Limited, maximum distance is only several meters, can not realize Long-range Data Transmission.Acquisition Circuit of the prior art is of high cost, knot
Structure is complicated.
Utility model content
The purpose of the utility model is to overcome the deficiency of above-mentioned technology, and provide a kind of based on FPGA realization line-scan digital cameras
The fibre-optic transmission system (FOTS) of Image Acquisition.
The utility model to achieve the above object, using following technical scheme：
A kind of fibre-optic transmission system (FOTS) that linear array camera image acquisition is realized based on FPGA, it is characterised in that:Including transmitting terminal
And receiving terminal, the transmitting terminal include 2 route array cameras, transmitting terminal fpga chip, crystal oscillator and transmitting terminal optical module, the transmission
The input terminal of end fpga chip is connected by 2 road Camera link interfaces with the 2 route array camera respectively, output terminal and institute
State the connection of transmitting terminal optical module；The receiving terminal includes host computer, receiving terminal fpga chip, crystal oscillator and receiving terminal optical module, institute
The input terminal for stating receiving terminal fpga chip is connect with the receiving terminal optical module, output terminal by Camera link interfaces with it is upper
Position machine connection, the transmitting terminal optical module are connect with the receiving terminal optical module by optical fiber, and the receiving terminal FPGA passes through
RS232 serial line interfaces receive host computer instruction, remote control are carried out to line-scan digital camera, host computer is for 2 route array cameras of display
The image collected data.
Preferably, the transmitting terminal fpga chip and receiving terminal fpga chip use the XC6VLX25T- of Xilinx companies
FGG484。
Preferably, the line-scan digital camera uses the L301kc of Basler companies.
Preferably, the fpga chip is connect by RS232 serial line interfaces with host computer.
Preferably, governor circuit, clock management circuits, Image Acquisition electricity are divided into inside the transmitting terminal fpga chip
Road, GTP transceiver control circuitries, link synchronization status monitor circuit；
Transmitting terminal governor circuit is connected with each circuit, is responsible for the management and scheduling of each unit circuit signal；
Transmitting terminal clock management circuits input 20MHz clocks, export the clock of 60MHz, the clock of output is as main work
Clock；
The input signal of transmitting terminal image acquisition circuit is the output of industrial camera Camera link interfaces, output signal
It is connected to governor circuit；
Transmitting terminal GTP transceiver control circuitry data transmit-receive signals are connected to governor circuit, and link state signal is output to
Link synchronization status monitor circuit；
The input signal of transmitting terminal link synchronization status monitor circuit is the status signal of GTP transceiver control circuitries, defeated
Go out to be signally attached to governor circuit.
Preferably, it is received inside receiving terminal fpga chip by governor circuit, clock management circuits, image transmission circuit, GTP
Send out device control circuit, link synchronization status monitor circuit, RS232 serial port circuits composition；
Receiving terminal governor circuit is connected with each circuit, is responsible for the management and scheduling of each unit circuit signal；
Receiving terminal clock management circuits input 20MHz clocks, export the clock of 60MHz as GTP transceiver control circuitries
Reference clock, the 60MHz recovered clocks obtained from GTP transceiver control circuitries are as work master clock；
The input signal of receiving terminal image transmission circuit is the output of governor circuit, and output signal is connected to host computer；
Receiving terminal GTP transceiver control circuitry data transmit-receive signals are connected to governor circuit, and link state signal is output to
Link synchronization status monitor circuit；
The input signal of receiving terminal link synchronization status monitor circuit is the status signal of GTP transceiver control circuitries, defeated
Go out to be signally attached to governor circuit；
Receiving terminal RS232 serial port circuits are connected with host computer, send and receive the control instruction to line-scan digital camera.
The beneficial effects of the utility model are:Relative to the prior art, by being completed in FPGA using special chip
The function that can be realized can realize the remote transmission of line-scan digital camera Camera link interface signals, stable, reliable, behaviour
Make simple, easy to maintain, reached design requirement.
Description of the drawings
Fig. 1 is the hardware of the utility model and main signal line connection diagram；
Fig. 2 is transmitting terminal FPGA inner function module connection diagrams in the utility model；
Fig. 3 is receiving terminal FPGA inner function module connection diagrams in the utility model.
Specific embodiment
Below in conjunction with the accompanying drawings and specific embodiment of the present utility model is described in detail in preferred embodiment.Such as Fig. 1 and Fig. 2 institutes
Show, a kind of fibre-optic transmission system (FOTS) that linear array camera image acquisition is realized based on FPGA, including：
1) crystal oscillator：The clock signal of 20MHz high-precision low jitters is provided FPGA；
2)FPGA：Reception, processing and the forwarding of the main picture signal for completing the transmission of Camera link interfaces；
3) line-scan digital camera：It is main to complete image collecting function；
4) host computer：The main image display function and human-computer interaction function for completing line-scan digital camera；
5) optical module：The main mapping function completed between high speed optoelectronic signal.
After the power is turned on, transmitting terminal connects initialization to this system into uplink synchronization first with receiving terminal, and both ends are according to 8B/10B
The bi-directionally sent K28.5 data of coding protocol complete symbol synchronization, then carry out two-way frame synchronization judgement, once symbol synchronization and frame
It synchronously completes, you can carry out the normal transmission of image data.
The image information that the transmitting terminal fpga chip is acquired by 2 route array camera of Camera link interfaces, is pressed
Data multiplexing is carried out according to the different operating frequency of line-scan digital camera 20MHz, 40MHz, 60MHz, is then passed through using FIFO across clock
Domain processing transforms to local 60MMHz clock domains, and 2 road Parallel image datas and synchronizing signal are passed through GTP transceiver control circuitries
The obtained serial signal of high speed parallel serial conversion give transmitting terminal optical module, optical module converts electrical signals to optical signals optical fiber
Receiving terminal optical module is sent to, optical signal is become electric signal and gives receiving terminal FPGA by receiving terminal optical module, and receiving terminal FPGA will
The data received are reduced to 2 tunnel picture signals by processing, then give industrial personal computer via Camera link interfaces and carry out rear end
Display and processing.
It is communicated between industrial personal computer and receiving terminal FPGA by RS232 serial ports, it can be with 2 road transmitting terminal linear array of remote control
Camera.
Hardware and main signal line connection diagram are as shown in Figure 1.
Transmitting terminal FPGA inner function module connection diagrams are as shown in Figure 2.
Receiving terminal FPGA inner function module connection diagrams are as shown in Figure 3.
Line-scan digital camera can be operated under three kinds of clock frequencies in this system：20MHz、40MHz、60MHz.In basic configuration
Camera link interfaces have three port 8 data A, B, C after carrying out reduction under pattern, in 20MHz using port A, port B and
In 40MHz using port A and port B, port A is used in 60MHz by port C.Every port can be 8 under three kinds of rates,
It can be 10 only in 60MHz and 40MHz frequency lower ports bit wide.
Transmitting terminal clock management circuits, by the way that FPGA IP kernels is called to realize.20MHz clocks are inputted, export 60MHz clocks.
Master clock of the clock of output as other all circuits.
Transmitting terminal image acquisition circuit handles 2 road Camera link interface data, is carried out at cross clock domain using FIFO
Reason, local 60MHz clock domains are adjusted to, while data are generated to 10 bit datas after multiple connection by three kinds of working frequencies, and
FVAL, LVAL data controlling signal are adjusted to local 60MHz clock domains.
Transmitting terminal GTP transceiver control circuitries complete the parallel serial conversion of 32 bit parallel datas using the IP kernel inside FPGA
And serial to parallel conversion, linear speed 2.4GHz.Line transmission pattern is encoded using 8B/10B.
Transmitting terminal link synchronization status monitor circuit receives GTP transceiver line of-step signals, under circuit desynchronizing state
Send symbol synchronization data K28.5.Frame synchronizing signal is sent after line synchronization, and continues monitoring link after frame synchronization is completed
Frame synchronization state.
Transmitting terminal governor circuit completes 2 road Camera link interface data signals and controls signal and synchronizing signal
Multiple connection, synchronous in 32 bit parallel datas and control signal occupy 2, and 2 road Camera link interface signals respectively occupy 14, empty
Not busy 2 can be used as accessory channel to transmit information.The state alarm signal provided according to other circuits generates reset signal to control
It makes the initialization of each circuit and carries out signal reset.By state machine manage circuit, basic status include initial state, synchronous state,
Idle state, operating conditions.It when system electrification and step-out, in initial state, needs to send symbol synchronization and frame synchronizing signal, from right
Synchronizing signal is detected in the transmission data of end, link synchronization is established by transmitting-receiving two-end handshake.Enter after link synchronization same
Gait, detection image data valid signal.If not detecting useful signal, into Idle state, otherwise into operating conditions.
It needs to send symbol synchronization data K28.5 maintenance link synchronization states in Idle state.Two-way 32 parallel-by-bit number is completed in operating conditions
According to multiple connection and tap.K28.5 data are filled during frame gap.
Receiving terminal clock management circuits, by the way that FPGA IP kernels is called to realize.20MHz clocks are inputted, export 60MHz clocks
Reference clock as receiving terminal GTP transceiver control circuitries.The recovered clock that receiving terminal GTP transceiver control circuitries generate is made
For global work clock, the output clock of 20MHz, 40MHz and 60MHz of generation as Camera link interfaces.
Receiving terminal GTP transceiver control circuitries complete the parallel serial conversion of 32 bit parallel datas using the IP kernel inside FPGA
And serial to parallel conversion, linear speed 2.4GHz.Line transmission pattern is encoded using 8B/10B.
Receiving terminal link synchronization status monitor circuit receives GTP transceiver line of-step signals, under circuit desynchronizing state
Send symbol synchronization data K28.5.Frame synchronizing signal is sent after line synchronization, and continues monitoring link after frame synchronization is completed
Frame synchronization state.
Receiving terminal governor circuit completes data-signal and the tap of control signal and synchronizing signal from transmitting terminal, and
The state alarm signal provided according to other circuits generates reset signal so that the initialization of each circuit and signal to be controlled to reset, and passes through
State machine carries out Circuit management, and basic status includes initial state, synchronous state, Idle state and operating conditions.When system electrification and step-out
When, in initial state, need to send symbol synchronization and frame synchronizing signal, detect synchronizing signal from the transmission data of opposite end, pass through
Transmitting-receiving two-end handshake establishes link synchronization.Enter synchronous state after link synchronization, detect and controlled from receiving terminal GTP transceivers
Circuit, which whether there is, receives image data useful signal, if without useful signal, into Idle state, otherwise into operating conditions.
Idle state needs to send symbol synchronization data K28.5 maintenance link synchronization states.Two-way 32 bit parallel data is completed in operating conditions
Multiple connection and tap.K28.5 data are filled during frame gap.
Receiving terminal image transmission circuit obtains the Camera link interface data of 2 tunnels reduction from governor circuit, utilizes
FIFO carries out cross clock domain processing, data is adjusted to one of three kinds of working frequencies by 60MHz clock domains according to control instruction, together
When 10 bit datas and FVAL, LVAL data controlling signal are reduced to three port datas and through Camera by data tapping
Link interfaces are sent to host computer.
RS232 serial port circuits are connected with host computer, are realized by the data for reading and writing line-scan digital camera register to line-scan digital camera
Remote control.
According to the above description, the embodiment of the utility model can be realized with reference to art technology.
The above is only the preferred embodiment of the utility model, it is noted that for the common skill of the art
For art personnel, under the premise of the utility model principle is not departed from, several improvements and modifications can also be made, these improve and
Retouching also should be regarded as the scope of protection of the utility model.
Claims (6)
1. a kind of fibre-optic transmission system (FOTS) that linear array camera image acquisition is realized based on FPGA, it is characterised in that:Including transmitting terminal and
Receiving terminal, the transmitting terminal include 2 route array cameras, transmitting terminal fpga chip, crystal oscillator and transmitting terminal optical module, the transmitting terminal
The input terminal of fpga chip is connected by 2 road Camera link interfaces with the 2 route array camera respectively, output terminal with it is described
Transmitting terminal optical module connects；The receiving terminal includes host computer, receiving terminal fpga chip, crystal oscillator and receiving terminal optical module, described
The input terminal of receiving terminal fpga chip is connect with the receiving terminal optical module, output terminal by Camera link interfaces with it is upper
Machine connects, and the transmitting terminal optical module is connect with the receiving terminal optical module by optical fiber, and the receiving terminal FPGA passes through RS232
Serial line interface receives host computer instruction, and remote control is carried out to line-scan digital camera, and host computer collects for 2 route array cameras of display
Image data.
2. the fibre-optic transmission system (FOTS) of linear array camera image acquisition is realized based on FPGA according to claim 1, it is characterised in that:
The transmitting terminal fpga chip and receiving terminal fpga chip use the XC6VLX25T-FGG484 of Xilinx companies.
3. the fibre-optic transmission system (FOTS) of linear array camera image acquisition is realized based on FPGA according to claim 2, it is characterised in that:
The line-scan digital camera uses the L301kc of Basler companies.
4. the fibre-optic transmission system (FOTS) of linear array camera image acquisition is realized based on FPGA according to claim 3, it is characterised in that:
The fpga chip is connect by RS232 serial line interfaces with host computer.
5. the fibre-optic transmission system (FOTS) of linear array camera image acquisition is realized based on FPGA according to claim 1, it is characterised in that:
Governor circuit, clock management circuits, image acquisition circuit, the control of GTP transceivers are divided into inside the transmitting terminal fpga chip
Circuit, link synchronization status monitor circuit；
Transmitting terminal governor circuit is connected with each circuit, is responsible for the management and scheduling of each unit circuit signal；
Transmitting terminal clock management circuits input 20MHz clocks, the clock of 60MHz are exported, when the clock of output is as main work
Clock；
The input signal of transmitting terminal image acquisition circuit is the output of industrial camera Camera link interfaces, and output signal connects
To governor circuit；
Transmitting terminal GTP transceiver control circuitry data transmit-receive signals are connected to governor circuit, and link state signal is output to link
Synchronous regime monitors circuit；
The input signal of transmitting terminal link synchronization status monitor circuit is the status signal of GTP transceiver control circuitries, output letter
Number it is connected to governor circuit.
6. the fibre-optic transmission system (FOTS) of linear array camera image acquisition is realized based on FPGA according to claim 1, it is characterised in that:
By governor circuit, clock management circuits, image transmission circuit, GTP transceiver control circuitries, link inside receiving terminal fpga chip
Synchronous regime monitoring circuit, RS232 serial port circuits composition；
Receiving terminal governor circuit is connected with each circuit, is responsible for the management and scheduling of each unit circuit signal；
Receiving terminal clock management circuits input 20MHz clocks, export ginseng of the clock of 60MHz as GTP transceiver control circuitries
Clock is examined, the 60MHz recovered clocks obtained from GTP transceiver control circuitries are as work master clock；
The input signal of receiving terminal image transmission circuit is the output of governor circuit, and output signal is connected to host computer；
Receiving terminal GTP transceiver control circuitry data transmit-receive signals are connected to governor circuit, and link state signal is output to link
Synchronous regime monitors circuit；
The input signal of receiving terminal link synchronization status monitor circuit is the status signal of GTP transceiver control circuitries, output letter
Number it is connected to governor circuit；
Receiving terminal RS232 serial port circuits are connected with host computer, send and receive the control instruction to line-scan digital camera.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721636178.0U CN207560149U (en) | 2017-11-30 | 2017-11-30 | The fibre-optic transmission system (FOTS) of linear array camera image acquisition is realized based on FPGA |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721636178.0U CN207560149U (en) | 2017-11-30 | 2017-11-30 | The fibre-optic transmission system (FOTS) of linear array camera image acquisition is realized based on FPGA |
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| CN207560149U true CN207560149U (en) | 2018-06-29 |
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| CN201721636178.0U Expired - Fee Related CN207560149U (en) | 2017-11-30 | 2017-11-30 | The fibre-optic transmission system (FOTS) of linear array camera image acquisition is realized based on FPGA |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108712625A (en) * | 2018-08-07 | 2018-10-26 | 成都希格玛光电科技有限公司 | Multichannel real-time high definition image Transmission system and transmission method |
| CN110632090A (en) * | 2019-09-05 | 2019-12-31 | 浙江翼晟科技有限公司 | Scanning imaging system based on multiple CIS cascade connection and scanning imaging method thereof |
| CN111050093A (en) * | 2019-12-17 | 2020-04-21 | 中国科学院光电技术研究所 | Camera-link full-based embedded image storage and image processing system and method |
| CN111435983A (en) * | 2019-11-21 | 2020-07-21 | 北京仁光科技有限公司 | Photoelectric return partition interaction system for interacting signal sources in each subnet |
| CN113204505A (en) * | 2021-03-31 | 2021-08-03 | 桂林电子科技大学 | FPGA-based interface conversion method with different rates |
| CN113934388A (en) * | 2020-07-14 | 2022-01-14 | 华为技术有限公司 | Synchronous display method, terminal and storage medium |
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2017
- 2017-11-30 CN CN201721636178.0U patent/CN207560149U/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108712625A (en) * | 2018-08-07 | 2018-10-26 | 成都希格玛光电科技有限公司 | Multichannel real-time high definition image Transmission system and transmission method |
| CN108712625B (en) * | 2018-08-07 | 2024-02-23 | 成都希格玛光电科技有限公司 | Multichannel real-time high-definition image transmission system and transmission method |
| CN110632090A (en) * | 2019-09-05 | 2019-12-31 | 浙江翼晟科技有限公司 | Scanning imaging system based on multiple CIS cascade connection and scanning imaging method thereof |
| CN111435983A (en) * | 2019-11-21 | 2020-07-21 | 北京仁光科技有限公司 | Photoelectric return partition interaction system for interacting signal sources in each subnet |
| CN111050093A (en) * | 2019-12-17 | 2020-04-21 | 中国科学院光电技术研究所 | Camera-link full-based embedded image storage and image processing system and method |
| CN111050093B (en) * | 2019-12-17 | 2021-11-19 | 中国科学院光电技术研究所 | Camera-link full-based embedded image storage and image processing system and method |
| CN113934388A (en) * | 2020-07-14 | 2022-01-14 | 华为技术有限公司 | Synchronous display method, terminal and storage medium |
| CN113204505A (en) * | 2021-03-31 | 2021-08-03 | 桂林电子科技大学 | FPGA-based interface conversion method with different rates |
| CN113204505B (en) * | 2021-03-31 | 2023-03-14 | 桂林电子科技大学 | FPGA-based interface conversion method with different rates |
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Granted publication date: 20180629 Termination date: 20201130 |