CN113204505A

CN113204505A - FPGA-based interface conversion method with different rates

Info

Publication number: CN113204505A
Application number: CN202110351082.4A
Authority: CN
Inventors: 张向利; 蒋浩云; 王俊凯; 董国华
Original assignee: Guilin University of Electronic Technology
Current assignee: Guilin University of Electronic Technology
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2021-08-03
Anticipated expiration: 2041-03-31
Also published as: CN113204505B

Abstract

The invention discloses an interface conversion method based on FPGA with different rates, which is characterized in that data of a main communication board card is sent to a low-speed cache high-speed sending conversion module through a data line and a control line of GTP, wherein the data comprises data flow and a control signal; after receiving the data stream and the corresponding control signal, integrating the received low-speed data stream into a high-speed data stream based on a cache sending mode, and sending the high-speed data stream to a driving sending module; converting the high-speed data stream into serial data by using the driving transmission module, converting the serial data into parallel data, and transmitting the parallel data to a high-speed cache low-speed transmission conversion module; and integrating the parallel data into the low-speed data stream based on a cache sending mode, recovering the control signal, and sending the low-speed data stream and the control signal to a slave communication board card, so that the memory resource of the FPGA required by the conversion of interfaces with different rates is reduced.

Description

FPGA-based interface conversion method with different rates

Technical Field

The invention relates to the technical field of FPGA communication, in particular to an interface conversion method based on different rates of an FPGA.

Background

The heaven-earth integrated information network taking the satellite constellation system as an important component is an important network foundation for supporting the economic development and the informatization construction of national defense, and becomes an important development direction of new capital construction in China. The inter-satellite communication needs high-efficiency and stable transmission rate, ensures large bandwidth and high-rate data transmission among satellites, and is an important basis for the integration of the space and the ground.

Taking the Beidou satellite as an example, the communication chip used by the interplanetary interface is TLK 2711. The chip TLK2711 has its own set of communication protocols, which are different from the communication protocols of the communication IP core GTP built in the FPGA chip that is currently used to process high-speed data.

GTP is a low power gigabit transceiver on FPGA. The GTP bit number is 8 bits, the rate can be realized to 1Git/s, the TLK2711 bit number is 16 bits, and the rate can reach 1.6 Gbit/s-2.5 Gbit/s. The interface conversion with different bits and different rates is a ping-pong method which is used in the FPGA for multiple purposes, and occupies a large amount of storage resources when the data volume is large, but the storage resources in the FPGA are not abundant, and the situation that the storage resources in the FPGA are not enough when the data volume is large can be caused.

Disclosure of Invention

The invention aims to provide an interface conversion method based on different rates of an FPGA (field programmable gate array), which reduces the memory resources of the FPGA required by interface conversion of different rates.

In order to achieve the above object, the present invention provides an interface conversion method based on FPGA with different rates, which comprises the following steps:

sending the data flow of the main communication board card to a low-speed cache high-speed sending conversion module through a data line and a control line of GTP;

after receiving the data stream and the corresponding control signal, integrating the received low-speed data stream into a high-speed data stream based on a cache sending mode, and sending the high-speed data stream to a driving sending module;

converting the high-speed data stream into serial data by using the driving sending module, sending the serial data to a receiving recovery module, converting the serial data into parallel data by using the receiving recovery module, and sending the parallel data to a high-speed cache low-speed sending conversion module;

and integrating the parallel data into the low-speed data stream based on a cache sending mode, recovering the control signal, and sending the low-speed data stream and the control signal to a slave communication board card.

After receiving the data stream and the corresponding control signal, the method integrates the received low-speed data stream into a high-speed data stream based on a cache sending mode, and sends the high-speed data stream to the driving sending module, and the method comprises the following steps:

acquiring the position of a data frame through a frame head, a frame tail and a control signal on the data stream, and reading the frame head, effective data and the frame tail of the data frame;

starting a write-in counter to count data in a read data frame and simultaneously pulling up write enable of an FIFO (first in first out) to write the data frame into the FIFO, modifying count value of a frame number counter in a cache after the write-in counter counts for one frame, simultaneously pulling down the write enable of the FIFO and closing write data;

when the count value of the frame number counter in the cache is greater than 1, the read enable of the FIFO is raised, and the read counter is started to count the read data frames until the reading of one data frame is finished;

and transmitting the read data frame to a driving sending module through a driving control line and a driving data line.

When the count value of the frame number in cache counter is greater than 1, the read enable of the FIFO is raised and the read counter is started to count the read data frames until one data frame is read, and the method further includes:

and after the reading of one data frame is finished, clearing the reading counter, pulling down the reading enable of the FIFO, subtracting 1 from the count value of the frame number counter in the buffer, and closing the reading of data.

The method for converting the high-speed data stream into serial data by using the driving sending module, sending the serial data to the receiving recovery module, converting the serial data into parallel data by using the receiving recovery module, and sending the parallel data to the high-speed cache low-speed sending conversion module comprises the following steps:

receiving the high-speed data stream by using a sending end in the driving sending module, converting the high-speed data stream into serial data and sending the serial data to a receiving and recovering module;

and recovering the received serial data into 16-bit parallel data by using the receiving recovery module, and sending the data to the cache low-speed sending conversion module.

The method for integrating the parallel data into the low-speed data stream based on a cache sending mode, recovering the control signal, and sending the low-speed data stream and the control signal to a slave communication board card includes:

judging the frame header of the parallel data by using an enable control line in the drive sending module, and raising the write enable of FIFO when the corresponding frame header position is obtained;

when the count value of a frame number counter in the cache low-speed transmission conversion module is greater than 1, pulling up the corresponding read enable, and simultaneously starting a read counter to count the read data frames;

after the reading counter is full of one data frame, subtracting 1 from the count value of the frame number counter in the cache, emptying the reading counter, simultaneously pulling down the reading enable of FIFO, and closing the reading data;

and according to the read data frame, recovering the corresponding control signal by counting the data of the data frame, and sending the data frame and the control signal to a slave communication board card.

The method comprises the following steps of judging a frame header of the parallel data by using an enabling control line in the driving sending module, and after the corresponding write enable is pulled up when the position of the corresponding frame header is obtained, the method also comprises the following steps:

writing the data into FIFO according to a data specification with a bit width of 16 and a frequency of 100MHZ, simultaneously starting a corresponding write-in counter, and judging that frame data is complete when the write-in counter is full of one data frame and the count value of the write-in counter is the same as the length of an agreed frame;

and adding 1 to the frame number counter in the cache, simultaneously pulling down the write enable, closing write data, and finishing the caching process of one data frame.

The invention relates to an interface conversion method based on different rates of an FPGA (field programmable gate array). data of a main communication board card is sent to a low-speed cache high-speed sending conversion module through a GTP (GPRS tunneling protocol) data line and a control line, wherein the data comprises data flow and control signals; after receiving the data stream and the corresponding control signal, integrating the received low-speed data stream into a high-speed data stream based on a cache sending mode, and sending the high-speed data stream to a driving sending module; converting the high-speed data stream into serial data by using the driving sending module, sending the serial data to a receiving recovery module, converting the serial data into parallel data by using the receiving recovery module, and sending the parallel data to a high-speed cache low-speed sending conversion module; and integrating the parallel data into the low-speed data stream based on a cache sending mode, recovering the control signal, and sending the low-speed data stream and the control signal to a slave communication board card, so that the memory resource of the FPGA required by the conversion of interfaces with different rates is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic step diagram of an interface conversion method based on different speeds of an FPGA according to the present invention.

Fig. 2 is a hardware framework diagram of an interface conversion method based on different rates of an FPGA according to the present invention.

Fig. 3 shows the data flow between modules after the GTP adaptation TLK2711 provided by the present invention.

Fig. 4 shows the internal data flow of the low-speed memory high-speed transmission conversion module provided by the invention.

FIG. 5 is a block diagram of the internal data flow of the cache slow-forward translation module provided by the present invention.

FIG. 6 is a block diagram of a writing _ flag structure provided by the present invention.

FIG. 7 is a state machine for writing and reading the writing _ flag provided by the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

Referring to fig. 1 to 3, the present invention provides an interface conversion method based on FPGA with different speeds, including the following steps:

and S101, sending the data stream of the main communication board to a low-speed cache high-speed sending conversion module through a data line and a control line of GTP.

Specifically, the original communication system uses an XK7C325 chip of XILINX KINTEX-7 series. The GTP communication soft core carried by the chip is used for communication, the rate is 125 multiplied by 8Mbp/s, and the subsequent processing of data in the soft core is designed by 1 Gbp/s. Later on, the communication serial port needs to be changed into TLK2711 due to requirements, and the communication rate of the TLK2711 is 100 x 16 Mbp/s. As shown in fig. 3, a schematic diagram of data flow between modules after the original communication system is modified into the TLK2711 is shown.

The main communication board card sends a data frame with a bit width of 8 bits through a data line of the processing module and sends a control signal with a bit width of 1bit through a control line. And sending the data of the main communication board card to a low-speed cache high-speed sending conversion module.

S102, after receiving the data stream and the corresponding control signal, integrating the received low-speed data stream into a high-speed data stream based on a cache sending mode, and sending the high-speed data stream to a driving sending module.

Specifically, as shown in fig. 3 and 4, the data line: the data line is data to be transmitted by the low-speed communication system, the bit width is 8, and the frequency is 125 MHz. Including the wait for synchronization data, the header, the payload data, and the trailer. The waiting synchronization data needs to be removed when transmitting. When the 8B/10B control signal is high level and the frame head is on the data line, the frame is judged to start, at this time, the write enable line is pulled high, the FIFO data writing end is opened, and the data is written into the FIFO from the data line. When the 8B/10B control signal is high level and the frame end is on the data line, the frame end is judged, the write enable line is pulled down, and the FIFO data writing end is closed.

Writing an enable line: the writing function of the FIFO is controlled by the cooperation of the data line and the high and low levels of the write enable line.

Enable counter: and controlling a write counter, and enabling the write counter to pull up to activate the write counter when the write enable line is pulled up.

Enabling the counter: controlling the counter of frame number in buffer, when the write-in counter is full of one frame, enabling the counter to be pulled high, and enabling the counter of frame number in buffer to be increased by 1.

Reading an enable line: controlling the reading function of FIFO, when the frame number counter in the buffer is greater than 1, pulling up the read enable line, controlling FIFO to start reading data from the data line to the TLK2711 sending end.

Sixthly, enabling a counter: and controlling a frame number counter in the buffer, and when the reading counter counts one frame, controlling the frame number counter in the buffer to be reduced by 1.

And a data line: the data line is a high-speed data stream which is sent to a TLK2711 sending end by FIFO, the bit width is 16, and the frequency is 100 MHZ.

Enabling a counter: controlling a reading counter, and when the TLK2711 transmitting terminal receives data transmitted by the data line, enabling the counter to be pulled up to activate the reading counter to start counting.

The buffer FIFO used here is a soft core FIFO built in vivado, a queue storage. The data writing method is characterized in that asynchronous FIFO is set, a writing clock is 125MHZ, a reading clock is 100MHZ, the bit width of a writing data line is 8, and the bit width of a reading data line is 16.

The low-speed cache high-speed sending conversion module judges the position of the data frame through a frame head, a frame tail and a control signal on the data stream, and reads the frame head, the effective data and the frame tail of the data frame and stores the frame head, the effective data and the frame tail into FIFO. The bit width of the write FIFO is 8 and the frequency is 125 MHz. And activating a write-in counter while writing in the FIFO, adding 1 to the counter of the frame number in the cache of the sending end when the write-in counter is full of one data frame and can be matched with the frame tail of the data frame on the data line, simultaneously pulling down the write enable of the FIFO, and closing the write-in data.

In the low-speed cache high-speed transmission conversion module, when the frame number counter in the cache of the sending end is greater than 1, the cache of the sending end has at least one complete data frame, at the moment, the reading enable of the FIFO is pulled high, the data starts to be read, the bit width of the FIFO data is read to be 16, and the frequency is 100 MHZ. And simultaneously activating a reading counter, subtracting 1 from the frame number counter in the buffer of the sending end after the reading counter counts a data frame, simultaneously pulling down the reading enable of the FIFO, and closing the reading data. Error-free high-speed transmission of the low-speed data stream will be completed. The frame structure employed in the present invention is as follows.

S103, converting the high-speed data stream into serial data by using the driving sending module, sending the serial data to a receiving recovery module, converting the serial data into parallel data by using the receiving recovery module, and sending the parallel data to a high-speed cache low-speed sending conversion module.

Specifically, the driving and transmitting module converts sixteen-bit data into serial data, and then transmits the serial data to the receiving and recovering module. The receiving recovery module recovers sixteen-bit parallel data after receiving the serial data and sends the data to the cache low-frequency sending conversion module. The receiving end high-speed communication interface TLK2711 receives serial data sent by the sending end through the TLK2711, and the TLK2711 of the receiving end restores the serial data into a data stream with bit width of 16 and frequency of 100MHZ and enable control lines RKMSB and RKLSB of the two TLKs 2711.

S104, integrating the parallel data into the low-speed data stream based on a cache sending mode, recovering the control signal, and sending the low-speed data stream and the control signal to a slave communication board card.

Specifically, as shown in fig. 5, the data line: the data line is the data received by TLK2711, the bit width is 16, and the frequency is 100 MHZ. Including the wait for synchronization data, the header, the payload data, and the trailer. When storing in FIFO, the waiting synchronization data, the frame header and the frame trailer need to be removed. And when the frame head is ready to be written, the write enable line is pulled high, and the data writing end of the FIFO is opened. And when the frame tail is ready to be written, the write enable line is pulled down, and the data writing end of the FIFO is closed.

Writing an enable line: the writing function of the FIFO is controlled by matching the data line with the high and low levels of the writing enable line to control the on and off of the writing data of the FIFO.

Data line: the data line is a low-speed data stream which is sent to the interior of the low-speed communication system by the FIFO, the bit width is 8, and the frequency is 125 MHZ.

Enabling a counter: and controlling a frame number counter in the buffer, and when the reading counter counts one frame, controlling the frame number counter in the buffer to be reduced by 1.

Enabling a counter: controlling the read counter, when the data line sends effective data, enabling the counter to be pulled up, and activating the read counter to start counting.

Ninthly, control line: and recovering a control line of the head frame and the tail frame of the TLK2711 from the last main low-speed communication system through a counter to send the control line to the slave low-speed popular communication system to judge the head frame and the tail frame of the data frame.

In a cache low-speed transmission conversion module, judging a frame header of TLK2711 through an enable control line and a data stream of TLK2711, raising write enable of a receiving FIFO (first in first out) after judging the frame header, writing data frames without the frame header of TLK2711 into the receiving FIFO with the bit width of 16 and the frequency of 100MHZ, simultaneously activating a write counter, adding 1 to the frame number counter in the cache of a receiving end when the write counter is full of one data frame and can be matched with the frame tail of the data frame on a data line, simultaneously lowering the FIFO write enable, and closing write data.

In the cache low-speed transmission conversion module, when the frame number counter in the cache of the receiving end is greater than 1, the cache of the receiving end has at least one complete data frame, at this time, the reading of the data is started by pulling up the read enable of the FIFO, the bit width of the read FIFO data is 8, and the frequency is 125 MHZ. And simultaneously activating a reading counter, subtracting 1 from a frame number counter in a buffer of a receiving end after the reading counter counts a data frame, simultaneously pulling down the reading enable of the FIFO, and closing the reading data. The high-speed data stream is cached and processed at a low speed.

For the specific implementation of the caching mode of the writing _ flag, as shown in fig. 6, the writing _ flag structure block diagram is shown, and as shown in fig. 7, the writing _ flag structure block diagram is a state machine for writing and reading the writing _ flag.

Specifically, the FIFO is an asynchronous FIFO buffer, w _ en is write enable, r _ en is read enable, in _ d is a write data port, out _ d is a read data port, wclk is a write clock, and rclk is a read clock.

The in _ data is input data stream, the bit width of the input data stream is 8 bits, the frequency is 125MHZ, and the input data stream is composed of a data line and a control signal. write _ num is a write counter, when a frame header arrives in _ data (the judgment rule of the frame header is 0x1c on a data line and a high level on a control line), the write _ num counter is activated to start counting and pull up w _ en, the write _ num is self-increased by 1 every time one data frame data is written into FIFO, and when the count value of the write _ num counter is equal to length (frame length), the frame _ num is self-increased by 1 and the write _ num is reset. write _ clk is write clock 125 MHz.

out _ data is the output data stream with a bit width of 16 bits and a frequency of 100MHZ, consisting of a data stream and control signals. frame _ num is a FIFO internal frame number counter, read _ num is a reading counter, when frame _ num is greater than or equal to 1, the data in the FIFO is indicated to be at least complete by one frame, at the moment, the read _ num is activated to start counting, r _ en is pulled up, the counting rule is that the read _ num is automatically increased by 1 every time one FIFO internal data is read, and when the counting value of the read _ num counter is equal to length (frame length), the frame _ num is activated to be automatically decreased by 1, and the read _ num is reset. read _ clk is a write clock of 100 MHz.

Wherein the data frame is a fixed length frame having a determined frame length.

The conclusions can be drawn from fig. 6 and 7 and their explanations. The invention provides a 'watching flag' cache sending mode, which can solve the problem that after a high-speed interface of a low-speed communication system is changed, a low-speed data stream of the low-speed communication system is converted into a high-speed data stream without errors and is sent out through the high-speed communication interface. Compared with the traditional method, the method has the following advantages:

saving memory resources: compared with the traditional method that two FIFOs are used for alternately receiving and transmitting, only one FIFO is used, and half of cache resources inside the FPGA can be saved.

Secondly, the sequential logic is simple: only one FIFO is used, compared with the traditional method that two FIFOs are used alternately, the timing control is simpler, and the data stream conversion is completed by controlling the reading and writing of one FIFO through only a plurality of counters.

Advantageous effects

The 'watching flag' cache sending mode provided by the invention saves the storage resources in the FPGA, thereby improving the condition that the storage resources in the FPGA are possibly insufficient. Firstly, in the aspect of sequential logic, compared with a common buffering mode of a ping-pong receiving method, the 'gating flag' buffering transmission mode only needs one FIFO buffer, and compared with a common mode of using two FIFOs for alternate buffering, the 'gating flag' buffering transmission mode has simpler sequential logic. Secondly, in the aspect of storage resource occupation, two FIFO buffers slightly longer than the frame length are needed in a common mode, and only one FIFO buffer slightly longer than the frame length is needed in a 'watching flag' buffer sending mode, so that half of memory resources are saved compared with the common method.

The invention relates to an interface conversion method based on FPGA with different rates, which is characterized in that data of a main communication board card is sent to a low-speed cache high-speed sending conversion module through a data line and a control line of a data processing module which originally uses GTP as a communication serial port, wherein the data comprises data flow and control signals; after receiving the data stream and the corresponding control signal, integrating the received low-speed data stream into a high-speed data stream based on a cache sending mode, and sending the high-speed data stream to a driving sending module; converting the high-speed data stream into serial data by using the driving and sending module, transmitting the serial data to a receiving and recovering module by using the driving and sending module, converting the serial data into parallel data by using the receiving and recovering module, and sending the parallel data to a high-speed cache low-speed sending and converting module; and integrating the parallel data into the low-speed data stream based on a cache sending mode, recovering the control signal, and sending the low-speed data stream and the control signal to a slave communication board card, wherein only one FIFO is used in a single sending process and a single receiving process respectively, so that compared with the traditional ping-pong method, the method saves half of the memory resource of an FPGA chip by using two FIFOs, and reduces the memory resource of the FPGA required by interface conversion at different rates.

While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An interface conversion method with different rates based on FPGA is characterized by comprising the following steps:

2. The method as claimed in claim 1, wherein after receiving the data stream and the corresponding control signal, the method integrates the received low-speed data stream into a high-speed data stream based on a cache transmission manner, and transmits the high-speed data stream to the driving transmission module, and comprises:

3. The FPGA-based differential rate interface conversion method of claim 2, wherein when said count value of said in-buffer frame count counter is greater than 1, a read enable of said FIFO is raised and a read counter is enabled to count said read data frames until after a read of one of said data frames is completed, said method further comprising:

4. The method as claimed in claim 1, wherein the method for converting interfaces with different speeds based on FPGA includes converting the high-speed data stream into serial data by the driving transmission module, transmitting the serial data to the receiving recovery module, converting the serial data into parallel data by the receiving recovery module, and transmitting the parallel data to the cache low-speed transmission conversion module, and includes:

5. The method as claimed in claim 1, wherein the method for converting interfaces with different speeds based on FPGA includes integrating the parallel data into the low-speed data stream based on a cache transmission manner, recovering the control signal, and then transmitting the low-speed data stream and the control signal to a slave communication board, including:

6. The method according to claim 5, wherein an enable control line in the driving and sending module is used to determine a frame header of the parallel data, and when the corresponding frame header position is obtained, after the corresponding write enable is raised, the method further comprises: