CN111404652A - Multi-channel data acquisition and real-time hybrid transmission platform based on FPGA - Google Patents
Multi-channel data acquisition and real-time hybrid transmission platform based on FPGA Download PDFInfo
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Abstract
The multi-channel data acquisition and real-time hybrid transmission platform based on the FPGA comprises an FPGA data processor, an external image acquisition circuit, an optical module, a lower-level processor and an upper computer module. The FPGA data processor receives the instructions of the upper computer through the Ethernet communication module and disassembles the instructions into a detector enabling signal and a download control signal. The upper computer module is communicated with the FPGA data processor through the Ethernet module, and the external image acquisition circuit is driven to work through an enabling signal to send two paths of image data. The FPGA data processor receives two paths of image data and download control data, performs data mixing and performs data caching on the on-chip DRAM. The FPGA data processor calls a high-speed serial IP core and sends the multi-channel mixed data to the lower-level processor in an optical fiber mode. The invention realizes effective sampling of multi-channel data, avoids the defects of the traditional parallel and serial transmission (clock jitter, parallel multi-bit propagation delay and the like), and realizes high-speed effective downloading of multi-channel mixed data by utilizing a Serdes protocol interface.
Description
Technical Field
The invention belongs to the field of data transmission and interface communication, and relates to a platform based on FPGA multi-path data acquisition and real-time hybrid transmission.
Background
With the continuous expansion of the industries such as aerospace, rail transit, communication measurement and control, deep sea exploration and the like in China, the application of high-speed image acquisition and real-time transmission technology is more and more extensive, such as the fields of traffic supervision systems, real-time video conferences, medical equipment, industrial control, aerospace, aviation and military and the like. With the development of the technology, the requirements of the fields on the transmission rate and the data throughput of the image transmission system are higher and higher, especially for some occasions requiring mutual transmission and processing of a large amount of real-time data. For example, the frame resolution is 256 × 256, the frame rate is 80fps image data, and the image transfer rate is 900 Mbps. The earlier parallel transmission bus has the defects that effective data is difficult to maintain due to factors such as signal crosstalk and clock skew between boards because the clock frequency is higher, and the parallel bus needs to occupy more chip pin units and a larger wiring area along with the increase of the data bit width. Therefore, the parallel bus transmission mode is regarded as being open 23651in the field of high-speed communication. Other traditional image transmission interfaces, such as a UART serial port (115Kbps), a USB2.0(480Mbps), and the like, are limited by low transmission rate, poor stability of the transmission process, short transmission distance, and the like, and cannot meet specific requirements of the current advanced field.
SerDes high-speed interface communication, as a high-speed serial point-to-point communication technology, possesses transmission characteristics of high bandwidth, high throughput, and low latency. The SerDes high-speed interface communication generally adopts a differential signal pair form for transmission, has strong anti-interference capability and longer transmission distance, and does not need to transmit synchronous clock signals, so that data is not influenced by clock skew. In addition, compared with a parallel transmission technology, the serial transmission mode has less restriction on hardware pins and transmission signal amplitude. Therefore, more and more serial link count SerDes for fiber optic transmission is applied to the upper and lower level communication or inter-board system communication.
The Field Programmable Gate Array (FPGA) technology is a semi-custom circuit technology in the Field of Application Specific Integrated Circuits (ASICs), and with the increasing innovation of computer technology and technology in the process Field, the hardware resources and even the system architecture of the FPGA are greatly improved, and with the advantages of reconfigurability, parallelism, high integration level, and various interface types, the FPGA is widely applied to image acquisition, transmission, and processing.
Although the development of FPGAs is well-established, the following disadvantages still exist: there is no special platform for multi-channel data acquisition and hybrid transmission, the multi-channel data (high and low speed) hybrid transmission is not stable, the communication interfaces of the platform are not abundant, effective data acquisition and transmission are restricted, and the communication transmission rate of the SerDes high-speed interface is low by using FPGA, so that real-time control operation cannot be performed.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the defects of the prior art are overcome, the multi-channel data acquisition and real-time hybrid transmission platform based on the FPGA is provided, effective acquisition and hybrid stable transmission of single-channel, double-channel and multi-channel data are realized, the platform communication interfaces are rich, and the real-time performance is strong.
The technical solution of the invention is as follows:
the FPGA-based multi-channel data acquisition and real-time hybrid transmission platform comprises an FPGA data processor, an external image acquisition circuit, an optical module, a lower-level processor and an upper computer module, wherein the external image acquisition circuit comprises an image detector I, an image detector II, an AD (analog-to-digital) conversion module and a T L K1501 optical fiber transmission module;
the upper computer module: receiving an instruction input by an operator through a human-computer interaction interface, processing the instruction to obtain an upper computer instruction, and outputting the upper computer instruction to the FPGA data processor;
an FPGA data processor: disassembling an upper computer instruction to obtain a detector I enabling signal, a detector II enabling signal and a download control signal, sending the detector I enabling signal to an image detector I, and sending the detector II enabling signal to an image detector II; caching and transmitting the download control signal, the image I signal and the image II data, outputting each path of data to an optical module in real time through high-speed switching, and communicating with a lower-level processor through an optical fiber form;
an image detector I: outputting an image I analog signal to an AD analog-to-digital conversion module under the driving of a detector I enable signal;
an AD analog-to-digital conversion module: carrying out digital quantity conversion on the image I analog signal to obtain an image I signal and outputting the image I signal to the FPGA data processor;
the image detector II is driven by a detector II enabling signal to output image II data to the T L K1501 optical fiber sending module;
the T L K1501 fiber optic transmission module is used for processing the image II data to obtain image II fiber optic data and transmitting the image II fiber optic data to the FPGA data processor;
the FPGA data processor comprises an Ethernet communication module, a detector driving module, an oversampling module, a multi-channel data mixing and checking module, a multi-channel data cache DRAM, a data sending and switching state machine, a multiplexer and a SerDes high-speed communication module;
the Ethernet communication module receives an upper computer instruction output by the upper computer module and disassembles the upper computer instruction into a detector enabling instruction and a downlink control signal, the detector enabling instruction is sent into the detector driving module to be analyzed, and a detector I enabling signal and a detector II enabling signal are obtained after the analysis; the downlink control signal is sent to a multi-channel data mixing and checking module;
the oversampling module performs oversampling on the image I signal to obtain oversampling image 1 data and outputs the oversampling image 1 data to the multi-path data mixing and checking module, and the multi-path data mixing and checking module simultaneously receives image II optical fiber data output by the T L K1501 optical fiber sending module;
the multi-path data mixing and checking module mixes the optical fiber data of the image II, the data of the ultra-sampling image 1 and the downlink control signal, the mixed three paths of data are sent into a multi-path data cache DRAM for caching and output to a multiplexer, a data sending switching state machine outputs a data switching enabling signal to the multiplexer, the multiplexer realizes effective switching of the output data of the multi-path data cache DRAM according to the data switching enabling signal, and the switched data are output to a SerDes high-speed communication sending module; the SerDes high-speed communication sending module transmits the received multipath data to an optical module and communicates with a lower-level processor through an optical fiber form.
The super-sampling module is as follows: the sampling ratio of 1 processes the image I data, so that the over-sampling image 1 data and the working clock of the image detector I are kept consistent.
The multi-channel data mixing and checking module respectively adds frame head and frame counting mark signals for distinguishing data types to the received ultra-sampling image 1 data, image II optical fiber data and downlink control signals, and simultaneously adds check sum and frame counting in the image II optical fiber data and the ultra-sampling image 1 data so as to check the problems of image messy codes and loss in link transmission.
The transmission mode of the super-sampling image I data in the multi-channel data mixing and checking module is as follows:
"CFAA + frame count + one frame of super-capture image I data + CF55+ check";
the transmission mode of the image II optical fiber data in the multi-channel data mixing and checking module is as follows:
"4 FAA + frame count + one frame image II fiber data +4F55+ kernel check";
the transmission mode of the downlink control signal in the multi-channel data mixing and checking module is as follows:
"FFAA + frame count + downstream control signal + FF55+ core check";
the method comprises the following steps of acquiring image I data, acquiring image II optical fiber data, acquiring a CFAA (frame head of super-acquisition image I) data, acquiring FFAA (frame head of down-transmission control signal), acquiring CF55 (frame tail marker) of the super-acquisition image I data, acquiring 4F55 of the frame tail marker of the image II optical fiber data, and acquiring FF55 of the frame tail marker of the down-transmission control signal.
The multi-path data cache DRAM comprises an on-chip block RAM with 8M memory capacity, and the on-chip block RAM is used for storing the mixed three paths of data respectively.
The multichannel data cache DRAM opens up three FIFO storage blocks, and the download control signal, the super-sampling image I data and the image II optical fiber data are respectively cached in the respective FIFO storage blocks in corresponding formats.
The working process of the data sending switching state machine is as follows:
(1) during initialization, setting the priority of a FIFO storage block corresponding to the super-sampling image I data to be highest by a program;
(2) a working starting state, wherein the working starting state is defaulted to enter an idle state; setting a data switching enable signal to be '000', sequentially judging whether data exist in the three FIFO memory blocks, if no data exist, entering a data waiting state, keeping the data switching enable signal unchanged, and entering the step (6); if the three FIFO storage blocks have data, entering the step (3); if one or two of the three FIFO storage blocks have data, directly sending the data out when judging that a certain FIFO storage block has data, and entering the step (6) after the data of each storage block is sent;
(3) preferentially reading super-sampling image I data, entering an image data I sending state, setting a data switching enabling signal to be '001', and entering a step (4) to start to transmit other data if a FIFO storage block of the super-sampling image I data is empty and a frame tail mark of CF55 is judged;
(4) judging whether data exist in the image II optical fiber data FIFO storage block or not, if the data exist in the image II optical fiber data FIFO storage block, starting a data switching enabling signal '010', entering an image data II sending state, and if the image II optical fiber data FIFO storage block is empty and the frame tail mark of 4F55 is judged, entering the step (5) and starting to transmit other data;
(5) judging whether the data exists in the downlink control signal FIFO storage block, if so, starting a data switching enabling signal '100', entering an upper computer data sending state, and if the downlink control signal FIFO storage block enters a read-empty state and judges that a frame tail mark of FF55 exists, entering step (6);
(6) and (5) returning to the step (2) to perform the next round of judgment.
The image detector I is a RC016B high-performance snapshot mode image detector, the image detector II is a long-wave MSM image detector, and the image detector I and the image detector II can acquire image data under different frequency spectrums.
The FPGA data processor is provided with a source synchronous parallel interface, an Ethernet communication interface and a Serdes high-speed interface of T L K1501.
The invention has the beneficial effects that:
1. the invention realizes the acquisition and real-time hybrid transmission of multi-channel high-speed and low-speed data, wherein the FPGA data processor can be compatible with a hybrid transmission mechanism of single-channel, double-channel and multi-channel data.
2. The FPGA data processor designed by the invention supports multiple types of data communication interfaces, and comprises a universal source synchronous parallel interface, an Ethernet communication interface, a SerDes high-speed interface supported by a hardware chip T L K1501 and a SerDes high-speed interface supported by the FPGA, wherein the richness of the high-speed interfaces meets the diversified selection of peripheral equipment, and meanwhile, the interface design of the FPGA data processor realizes the effective acquisition and highly stable transmission of data.
3. The upper computer module can regulate and control the opening and closing of the data of the detector in the external image acquisition circuit, and a visual operation interface of the upper computer module provides a visual experimental research platform for the research of a multi-channel data transmission mechanism.
4. The FPGA data processor adopts a high-speed interface technology, the transmission bandwidth of image data can reach 6.25Gbs, and the data acquisition time and the transmission time are greatly reduced.
5. The FPGA data processor carries out real-time check error correction and data classification on the data in transmission by methods such as XOR, checksum, frame head mark and the like; and the design of a multi-path data transmission switching state machine is adopted, so that multi-path data are mixed into one path of data under flexible arrangement and then are downloaded to a lower-level processor.
Drawings
FIG. 1 is a schematic structural diagram of a platform system according to the present invention;
FIG. 2 is a schematic diagram of a multi-channel data transmission switching state machine;
FIG. 3 is a SerDes protocol high speed hardware interface model.
Detailed Description
The design structure of the multi-channel data acquisition and real-time hybrid transmission platform based on the FPGA is described below with reference to the accompanying drawings.
The invention provides an FPGA multi-channel acquisition and real-time hybrid transmission platform, which realizes effective sampling of multi-channel data, avoids the defects of the traditional parallel and serial transmission (clock jitter, parallel multi-bit propagation delay and the like), and realizes high-speed and effective downloading of the multi-channel hybrid data by utilizing a Serdes protocol interface.
Specifically, the invention is composed of an FPGA data processor 1, an external image acquisition circuit 2, an optical module 4, a lower-stage processor 5 and an upper computer module 3. The FPGA data processor 1 is used for realizing acquisition, caching, preprocessing and process transmission of multi-channel mixed data. The external image acquisition circuit 2 is used for realizing hardware driving of the image detector, the upper computer module 3 realizes a man-machine operation interface through VB programming, communication with the FPGA data processor 1 is realized through the Ethernet communication module 14, and the optical module 4 is used as a communication medium of a high-speed interface to realize data communication between the FPGA data processor 1 and the lower processor 5.
The FPGA data processor 1 serves as a core of the design platform, firstly, the FPGA data processor 1 receives an upper computer instruction 18 through an Ethernet communication module 14 and disassembles the upper computer instruction into a detector enabling instruction 19 and a downlink control signal 26, the detector enabling instruction 19 is sent into a detector driving module 10 for analysis, a detector I enabling signal 20 and a detector II enabling signal 21 are output, an image detector I6 and an image detector II7 respectively receive a detector I enabling signal 20 and a detector II enabling signal 21 output by the detector driving module 10, whether the detector I enabling signal 20 and the detector II enabling signal 21 are effective and directly control working states of an image detector I6 and an image detector II7, the working modes of the detectors are different according to different types of the detectors, wherein the image detector I6 outputs an image I analog signal 22 after working and transmits the image I analog signal 22 to an AD analog-to-conversion module 8, the AD analog-to-convert the image I analog signal 22, output image I analog-to-buffer 24, an image detector II buffer 7, an image detector II data buffer 23, an optical fiber-to-convert the optical-to-optical-to-optical-fiber-optical-fiber-to-optical-data conversion-data-multiplexer module-receive data-receive data-receive-data.
The external image acquisition circuit 2 comprises a high-performance snapshot mode image detector I6 and a long-wave MSM image detector II, wherein the model of the image detector I6 is RC016B, the two image detectors aim at different visible light spectrum wave bands, the image detector I6 outputs data with an image format of 128 x 128, and the image detector II outputs image data with an image format of 256 x 320, wherein analog signals of an image 1 output by the image detector I need to be subjected to analog-to-digital conversion through an AD analog-to-digital conversion module 8, the AD analog-to-digital conversion module 8 mainly adopts an integrated dual-core device AD9245 converter to convert the analog signals into digital signals, and the image detector II7 sends image II optical fiber data 25 through a T L K1501 optical fiber sending module 9.
The model of the AD analog-to-digital conversion module 8 chip is AD9245, the AD9245 adopts a multi-stage differential pipeline architecture, an output error correction logic is built in, 14-bit precision can be provided at the highest 65MSPS data rate, no missing code is ensured in the whole working temperature range, and the design requirement is met.
The FPGA data processor 1 adopts a finite state machine and a pipeline technology to realize the super-sampling module 11, the data sending switching state machine 15 and the multi-path data mixing and checking module 12. The super-sampling module 11 receives the image I signal 24 converted by the AD/a conversion module 8, and performs super-sampling. By the supersampling module 11, according to 16: the sampling ratio of 1 processes the image I data 24 such that the oversubscribed image 1 data 30 and the image detector I6 operating clock are consistent. The multi-path data mixing and checking module 12 adds operations such as checksum, frame counting and the like to the image II optical fiber data 25 and the ultra-sampling image 1 data 30 so as to check the problems such as image scrambling and loss in link transmission.
The FPGA data processor has rich interface design, including source synchronous parallel interface connected to external image acquisition circuit, Serdes high-speed interface of hardware T L K1501, Ethernet communication interface for upper computer communication, and FPGA Serdes high-speed interface for lower processor communication.
The FPGA data processor 1 and the image detector I6 adopt source synchronous parallel interface transmission, the FPGA data processor 1 and the image detector II adopt a T L K1501 optical fiber sending module to send, and high-speed transmission of parallel-serial-parallel image II optical fiber data 25 is realized.
The multi-way data cache DRAM comprises an on-chip block RAM of 8M memory capacity for storing the hybrid multi-way data 28, respectively.
In terms of hardware design, as shown in fig. 1, an FPGA data processor adopts an Artix-7xc7a100tcsg324-2 chip produced by Xilinx corporation, an external image acquisition circuit 2 comprises a high-performance snapshot mode image detector I and a long-wave MSM image detector II with the model of RC016B, the two image detectors output image data with the formats of 128 × 128 and 256 × 320 according to different visible light spectral bands, hardware circuits such as an image detector I and an AD analog-to-digital conversion module 8 perform data communication in a source synchronous parallel interface mode, communication interfaces are determined to be two 14-bit parallel interfaces by the working mode and the precision of an AD analog-to-digital conversion module 9245 chip, the image detector II and the FPGA data processor 1 perform data communication by adopting a SerDes protocol high-speed communication interface, a T L K1501 optical fiber transmission module 9 is designed on a hardware peripheral circuit, the design of communication links between the image detector II and the FPGA data processor 1 is completed, an upper computer operation interface 3 transmits an upper computer instruction 18, an upper computer instruction 18 comprises a lower transmission signal, a lower signal control module and a lower signal control module which enables the image detector I and a sampling signal processing module 19 to perform data processing, the signal processing module, the image detector I and the image detector M19, the image detector I and the image detector 19 and the image detector are enabled by a sampling system, the image detector 8, the image detector is enabled by the image detector, the image detector 8, the image detector is enabled by the image detector, the image detector is enabled and the image detector.
The multi-path data mixing and checking module 12 receives the downloaded control signal 26, the super-sampling image I data 30 and the image II optical fiber data 25 transmitted by the ethernet communication module 14, performs data preprocessing on the three paths of mixed data, and performs data downloading according to the following format. The transmission mode of the super-sampling image I data 30 in the multi-path data mixing and checking module 12 is as follows:
"CFAA + frame count + one frame of hyper-acquired image I data (128 x 128) + CF55+ check. The transmission mode of the image II fiber data 25 in the multi-path data mixing and verifying module 12 is as follows:
"4 FAA + frame count + one frame image II fiber data (256 × 320) +4F55+ nuclear check". The transmission mode of the downstream control signal 26 in the multi-path data mixing and verifying module 12 is:
"FFAA + frame count + control signal (8 × 8) + FF55+ check" for one frame.
CFAA is the frame head of the super-sampling image I data 26, 4FAA is the frame head of the image II fiber data 30, FFAA is the frame head of the download control signal 26, CF55 is the frame tail flag of the super-sampling image I data 26, 4F55 is the frame tail flag of the image II fiber data 30, and FF55 is the frame tail flag of the download control signal 26.
The check of the kernel adopts an exclusive or and check method, which comprises the following steps:
the core check is data 1^ data 2^ data 1 … … ^ data N; (N is image data count);
the multi-path data cache DRAM calls the FPGA on-chip DRAM, data caching is carried out on the download control signal 26, the ultra-collecting image I data 30 and the image II optical fiber data 25 by a three-path FIFO storage module method, the utilization rate of FPGA storage resources and data code stream transmission are considered, and FIFO cache spaces with the storage depths of 8192, 16384 and 64 are respectively opened up. The multiplexer 16 switches the multiplexed data buffer DRAM output data 29 according to the data switch enable signal 27. And the SerDes high-speed communication sending module 17 is called by the FPGA to transmit the multiplexed and selected multi-path data to the optical module 4, and the multi-path data is communicated with the lower-level processor 5 in an optical fiber form.
The schematic diagram of the multi-path data transmission switching state machine is shown in fig. 2: the three paths of data 28 after mixing include an idle state 31, an image data I sending state 32, an image data II sending state 33, an upper computer data sending state 34 and a data waiting and refreshing state 35, and the corresponding data output is switched in the transmission link according to the instruction signal sent by the data sending switching state machine 15. The download control signal 26, the super sampling image I data 30 and the image II optical fiber data 25 are respectively buffered in the corresponding format in the respective FIFO memory blocks, and the data transmission switching state machine 15 performs instruction judgment by judging the empty signal of the FIFO and the frame end flag of one frame of data. The data transmission switching state machine 15 has the following working procedures: the initial transmission data flow sets the higher priority of the super-capture image I data 30FIFO block. The initial state defaults to enter the idle state 31, turns on the data switch enable signal 27 "000", then judges whether data exists in three FIFO memory areas, if no data is transferred, the data wait state 35 is entered, and the data switch enable signal 27 is kept unchanged. Reading of the super-sampling image I data 30 is preferentially started, an image data I transmission state 32 is entered, meanwhile, a data switching enable signal 27 '001' is started, if the FIFO storage area of the super-sampling image I data 30 is empty and the frame tail mark of CF55 is judged, transmission of other data is started, whether data exists in the FIFO storage area of the image II optical fiber data 25 is judged, a data switching enable signal 27 '010' is started, and an image data II transmission state 33 is entered. If the FIFO storage area of the image II optical fiber data 25 enters into read-out and the end of frame mark of 4F55 is judged, other data starts to be transmitted. And judging whether the FIFO storage area of the control signal 26 is data or not, starting a data switching enable signal 27 of '100', and entering an upper computer data transmission state 34. If the FIFO storage area of the downstream control signal 26 goes into read empty and the end of frame flag of FF55 is asserted, then the transfer of additional data begins.
In the FPGA-based multi-channel data acquisition and real-time hybrid transmission platform, communication between an image detector II and an FPGA data processor 1 and communication between the FPGA data processor 1 and a lower-level processor 5 are both SerDes protocol high-speed interface communication, wherein a T L K1501 communication chip produced by TI company is adopted for communication between the image detector II and the FPGA data processor 1, a T L K1501 optical fiber transmission module is constructed for transmission of image II optical fiber data 25, an IP core GTX embedded in the FPGA chip by Xilinx company is adopted for communication between the FPGA data processor 1 and the lower-level processor 5 to form SerDes protocol high-speed interface communication, in the SerDes protocol high-speed hardware interface model, data to be transmitted firstly enters an input register 36, then passes through an 8b/10b encoder 37 to encode the data according to a specific high-speed protocol, the inside of the SerDes protocol high-speed interface communication is serial communication, the encoded data passes through a parallel-serial conversion module 38 and serial conversion module, then passes through a clock recovery module 42, a clock recovery module recovers information, a clock recovery module 42 sends the encoded data to a CDR 42, and a clock recovery module recovers effective data recovery module 42, and a clock recovery module 42 sends the encoded data recovery module 42 to a CDR 40, and a clock recovery module, and a transceiver module, wherein the transceiver module, and a transceiver.
The FPGA data processor 1 and the image detector I adopt source synchronous parallel interface transmission, the FPGA data processor 1 and the image detector II adopt a T L K1501 optical fiber sending module to send, and parallel-serial-parallel image II optical fiber data 25 high-speed transmission is realized, the FPGA data processor 1 calls a GTX IP core inside the FPGA, and high-speed communication with a lower-stage processor 5 is realized by a SerDes high-speed communication sending module 17 and an optical module device 4 as a transmission medium.
The invention realizes the acquisition and real-time hybrid transmission of multi-path high-speed and low-speed data, an upper computer is connected with an FPGA data processor through an Ethernet communication module, a detector driving module in the FPGA data processor outputs a detector enabling signal to operate the data on-off of an image detector I and an image detector II, the FPGA data processor can be compatible with a hybrid transmission mechanism of single-path, double-path and multi-path data, the image detector I outputs an analog signal due to the characteristic of the detector, the image detector I carries out digital processing through an AD sampling module and carries out data communication with the FPGA data processor in a source synchronization mode, the image detector II outputs a digital signal through internal processing, the inherent characteristic of the image detector II is considered, a T L K1501 optical fiber form is adopted on a hardware circuit for data transmission, the FPGA data processor is programmed to realize an oversampling module, the digital signal output by the AD sampling module is subjected to oversampling processing, the multi-path data mixing and checking module receives the control signal transmitted by the image detector I data after the oversampling, the image detector II data transmitted by the optical fiber and the control signal transmitted by the upper computer, the upper computer adds mark signals such as first frame, frame buffer, the frame count, the buffer count, the data are effectively classified, the multi-path data are simultaneously, the multi-path data mixing and the FPGA data are transmitted by the FPGA data processor, the FPGA data, the multi-path data are transmitted by the FPGA data processor, the multi-path data are transmitted by the FPGA data multiplexing module, the multi-path data processor, the multi-path mixed.
The FPGA data processor designed by the invention can be compatible with a mixed transmission mechanism of single-path, double-path and multi-path data. The FPGA data processor adopts a high-speed interface technology, the transmission bandwidth of image data can reach 6.25Gbs, and the data acquisition time and the transmission time are greatly reduced. Carrying out real-time check error correction and data classification on the data in transmission by methods such as an XOR sum check sum frame head mark and the like; and the design of a multi-path data transmission switching state machine is adopted, so that multi-path data are mixed into one path of data under flexible arrangement and then are downloaded to a lower-level processor. The upper computer module operation interface can regulate and control the on-off of the detector data in the external image acquisition circuit, and a visual experimental research platform is provided for the research of a multi-channel data transmission mechanism.
According to the invention, researchers can flexibly and conveniently complete related debugging of different types of communication interfaces, analyze a multi-channel high-speed and low-speed data hybrid transmission mechanism, control data acquisition through an operation interface, and provide important engineering value for researching multi-channel data acquisition and hybrid transmission communication.
Those skilled in the art will appreciate that the invention has not been described in detail in this specification.
Claims (10)
1. The multi-channel data acquisition and real-time hybrid transmission platform based on the FPGA is characterized by comprising an FPGA data processor (1), an external image acquisition circuit (2), an optical module (4), a lower-stage processor (5) and an upper computer module (3), wherein the external image acquisition circuit (2) comprises an image detector I (6), an image detector II (7), an AD analog-to-digital conversion module (8) and a T L K1501 optical fiber transmission module (9);
host computer module (3): receiving an instruction input by an operator through a human-computer interaction interface, processing the instruction to obtain an upper computer instruction (18), and outputting the upper computer instruction to the FPGA data processor (1);
FPGA data processor (1): disassembling an upper computer instruction (18) to obtain a detector I enabling signal (20), a detector II enabling signal (21) and a download control signal (26), sending the detector I enabling signal (20) to an image detector I (6), and sending the detector II enabling signal (21) to an image detector II (7); the downlink control signal (26), the image I signal (24) and the image II data (23) are cached and transmitted, and all paths of data are output to the optical module (4) in real time through high-speed switching and are communicated with the lower-level processor (5) through an optical fiber form;
image detector I (6): outputting an image I analog signal (22) to an AD analog-to-digital conversion module (8) under the driving of a detector I enable signal (20);
an AD analog-to-digital conversion module (8): carrying out digital quantity conversion on the image I analog signal (22) to obtain an image I signal (24) and outputting the image I signal to the FPGA data processor (1);
the image detector II (7) is driven by a detector II enabling signal (21) to output image II data (23) to the T L K1501 optical fiber sending module (9);
and the T L K1501 fiber optic transmission module (9) is used for processing the image II data (23) to obtain image II fiber optic data (25) and sending the image II fiber optic data to the FPGA data processor (1).
2. The FPGA-based multi-channel data acquisition and real-time hybrid transmission platform of claim 1, wherein: the FPGA data processor (1) comprises an Ethernet communication module (14), a detector driving module (10), a super sampling module (11), a multi-path data mixing and checking module (12), a multi-path data cache DRAM (13), a data sending and switching state machine (15), a multiplexer (16) and a SerDes high-speed communication module (17);
the Ethernet communication module (14) receives an upper computer instruction (18) output by the upper computer module (3) and disassembles the upper computer instruction into a detector enabling instruction (19) and a downlink control signal (26), the detector enabling instruction (19) is sent into the detector driving module (10) to be analyzed, and a detector I enabling signal (20) and a detector II enabling signal (21) are obtained after analysis; sending the downlink control signal (26) into a multi-channel data mixing and checking module (12);
the oversampling module (11) performs oversampling on the image I signal (24) to obtain oversampling image 1 data (30), and outputs the oversampling image 1 data to the multi-path data mixing and checking module (12), and the multi-path data mixing and checking module (12) simultaneously receives the image II optical fiber data (25) output by the T L K1501 optical fiber sending module (9);
the multi-path data mixing and checking module (12) mixes the image II optical fiber data (25), the ultra-acquisition image 1 data (30) and the download control signal (26), the mixed three paths of data (28) are sent into a multi-path data cache DRAM (13) for caching and output to the multiplexer (16), the data sending switching state machine (15) outputs a data switching enabling signal (27) to the multiplexer (16), the multiplexer (16) realizes effective switching of the output data (29) of the multi-path data cache DRAM according to the data switching enabling signal (27), and outputs the switched data to the SerDes high-speed communication sending module (17); the SerDes high-speed communication sending module (17) transmits the received multipath data to the optical module (4) and communicates with the lower-level processor (5) through an optical fiber form.
3. The FPGA-based multi-channel data acquisition and real-time hybrid transmission platform of claim 2, wherein: the oversampling module (11) is according to 16: the sampling rate of 1 processes the image I data (24) so that the working clocks of the oversubscribed image 1 data (30) and the image detector I (6) are kept consistent.
4. The FPGA-based multi-channel data acquisition and real-time hybrid transmission platform of claim 3, wherein: the multi-channel data mixing and checking module (12) respectively adds frame head and frame counting mark signals for distinguishing data types to the received ultra-collecting image 1 data (30), image II optical fiber data (25) and a download control signal (26), and meanwhile, the multi-channel data mixing and checking module (12) adds checksum and frame counting in the image II optical fiber data (25) and the ultra-collecting image 1 data (30) so as to check the problems of image messy codes and loss in link transmission.
5. The FPGA-based multi-channel data acquisition and real-time hybrid transmission platform of claim 4, wherein:
the transmission mode of the ultra-collecting image I data (30) in the multi-channel data mixing and checking module (12) is as follows:
"CFAA + frame count + one frame of super-capture image I data + CF55+ check";
the transmission mode of the image II optical fiber data (25) in the multi-channel data mixing and checking module (12) is as follows:
"4 FAA + frame count + one frame image II fiber data +4F55+ kernel check";
the transmission mode of the downlink control signal (26) in the multi-channel data mixing and checking module (12) is as follows:
"FFAA + frame count + downstream control signal + FF55+ core check";
CFAA is the frame head of the super-sampling image I data (26), 4FAA is the frame head of the image II optical fiber data (30), FFAA is the frame head of the downlink control signal (26), CF55 is the frame tail mark of the super-sampling image I data (26), 4F55 is the frame tail mark of the image II optical fiber data (30), and FF55 is the frame tail mark of the downlink control signal (26).
6. The FPGA-based multi-channel data acquisition and real-time hybrid transmission platform of claim 2, wherein: the multi-path data cache DRAM (13) comprises an on-chip block RAM with 8M memory capacity and is used for storing the mixed three paths of data (28) respectively.
7. The FPGA-based multi-channel data acquisition and real-time hybrid transmission platform of claim 6, wherein: the multi-path data cache DRAM (13) opens up three FIFO memory blocks, and the download control signal (26), the super-sampling image I data (30) and the image II optical fiber data (25) are respectively cached in the respective FIFO memory blocks in corresponding formats.
8. The FPGA-based multi-channel data acquisition and real-time hybrid transmission platform of claim 7, wherein: the data transmission switching state machine (15) has the working flow that:
(1) during initialization, setting the priority of a FIFO storage block corresponding to the super-sampling image I data (30) to be highest by a program;
(2) a work start state, entering an idle state (31) by default; setting a data switching enable signal (27) to be '000', sequentially judging whether data exist in the three FIFO memory blocks, if no data exist, entering a data waiting state (35), keeping the data switching enable signal (27) unchanged, and entering a step (6); if the three FIFO storage blocks have data, entering the step (3); if one or two of the three FIFO storage blocks have data, directly sending the data out when judging that a certain FIFO storage block has data, and entering the step (6) after the data of each storage block is sent;
(3) preferentially reading the super-sampling image I data (30), entering an image data I sending state (32), setting a data switching enable signal (27) to be '001', and entering a step (4) to start to transmit other data if a FIFO storage block of the super-sampling image I data (30) is empty and a frame tail mark of CF55 is judged;
(4) judging whether data exist in an image II optical fiber data (25) FIFO storage block, if so, starting a data switching enable signal (27) '010', entering an image II sending state (33), and if the image II optical fiber data (25) FIFO storage block is empty and the frame tail mark of 4F55 is judged, entering a step (5) and starting to transmit other data;
(5) judging whether the FIFO storage block of the download control signal (26) has data or not, if so, starting a data switching enable signal (27) '100', entering an upper computer data transmission state (34), and if the FIFO storage block of the download control signal (26) enters a read-empty state and the frame tail mark of FF55 is judged, entering a step (6);
(6) and (5) returning to the step (2) to perform the next round of judgment.
9. The FPGA-based multi-channel data acquisition and real-time hybrid transmission platform of claim 1, wherein: the image detector I (6) is an RC016B high-performance snapshot mode image detector, the image detector II (7) is a long-wave MSM image detector, and the image detector I (6) and the image detector II (7) can acquire image data under different frequency spectrums.
10. The FPGA-based multi-channel data acquisition and real-time hybrid transmission platform as claimed in claim 1, wherein the FPGA data processor (1) is provided with a source synchronous parallel interface, an Ethernet communication interface and a Serdes high-speed interface of T L K1501.
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