CN113079100A - NoC router for high-speed data acquisition - Google Patents
NoC router for high-speed data acquisition Download PDFInfo
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Abstract
The invention discloses a NoC router for high-speed data acquisition, which comprises a plurality of router bodies, wherein data interaction is formed between each router body and an external analog-to-digital conversion chip as well as between each router body and an upper computer; the router comprises router bodies, wherein input ports and output ports are arranged in the four directions of the south, the east and the north of each router body, local ports are arranged between the directions of the south, the west and the north of each router body, and the input ports, the output ports and the ports of each router body are connected with a switch through data links, so that the router specially designed for a high-speed data acquisition system is designed. The structure of the NoC router for high-speed data acquisition is simplified, the designed router has better time sequence and lower time delay, the defect that the NoC router for high-speed data acquisition cannot meet the requirement of high-speed data acquisition bandwidth is overcome, and the defects that the interface of the NoC router for high-speed data acquisition is poor in flexibility and expandability are overcome.
Description
Technical Field
The invention relates to the technical field of network on chip, in particular to a NoC router for high-speed data acquisition.
Background
With the development of scientific technology, the requirements of data acquisition on performance indexes such as sampling rate and resolution of Analog-to-Digital Converter (ADC) are higher and higher. However, under the limitation of process conditions, the improvement of the sampling rate and the resolution of the ADC is limited, and the prohibition of high-performance ADC chips is applied to China abroad, and the alternate collection of a plurality of ADCs becomes an effective method for improving the sampling rate. Most of the existing high-speed data acquisition systems adopt a bus-type time-interleaved sampling technology, and when acquisition nodes need to be expanded, global clock synchronization becomes very difficult.
Network-on-Chip (NoC) technology refers to and absorbs packet switching and routing technology in computer Network communication, so that communication efficiency is greatly improved. The reusability of the system is greatly enhanced by adopting a mode of separating an IP core from a communication network; by adopting Global Asynchronous and Local Synchronous (GALS) communication technology, the generation of huge clock trees is avoided, and the power consumption of a clock network is reduced.
The network-on-chip technology and the time alternative sampling technology are combined to realize high-speed data acquisition, the advantages of the network-on-chip are fully utilized, the communication bandwidth and the communication speed are expanded, and the expansion of resource nodes is more flexible. The router in the NoC plays an important role in the whole high-speed data acquisition system, however, in order to realize the acquisition of high-speed data through the NoC, a NoC router suitable for the NoC router is needed, the current NoC does not have a router specially designed for the high-speed data acquisition system, the router with low efficiency has poor time sequence, and the router has important influence on the data throughput rate, the data transmission delay and the system power consumption of the whole system; and the interface protocol between the routers is mostly self-defined, and has the defects of poor flexibility, poor expandability and the like, so the invention provides a NoC router design for high-speed data acquisition to solve the defects.
Disclosure of Invention
The invention aims to provide an NoC router for high-speed data acquisition, aiming at solving the problems that the NoC system in the prior art does not have a router specially designed for a high-speed data acquisition system, the router with low efficiency has poor time sequence, and the NoC router has important influence on the data throughput rate, the data transmission delay and the system power consumption of the whole system; and the interface protocol between the routers is mostly self-defined, and the technical problems of poor flexibility and poor expandability exist.
In order to achieve the above purpose, the NoC router for high-speed data acquisition adopted by the invention comprises a plurality of router bodies, wherein data interaction is formed between each router body and an external analog-to-digital conversion chip and between each router body and an upper computer;
the router comprises a router body, wherein the router body is provided with an input port and an output port in the four directions of the south, the east, the west and the north, a local port is arranged between the directions of the south, the west and the north of the router body, and the input port, the output port and the body port are connected with a switch through a data link;
the analog-to-digital conversion chip is used for acquiring data, performing analog-to-digital conversion on acquired data information to obtain data of resource nodes, and transmitting the data of the resource nodes to the corresponding input ports;
each input port is used for receiving the data of the resource node transmitted by the analog-to-digital conversion chip or the data sent by the router body at the upper stage, analyzing the data and outputting the data to the output port;
the output port is used for receiving the output data and sending the received data to the next level of router body or the upper computer;
and the upper computer is used for receiving the data output by the output port and analyzing and processing the data.
Each input port comprises an input module, a virtual channel module and a route decoding module, wherein the input module is respectively connected with the virtual channel module and the route decoding module, and the virtual channel module and the route decoding module are mutually connected;
the input module is used for receiving the microchip data and the microchip effective mark signals transmitted by the resource nodes or the router body at the upper stage from the analog-to-digital conversion chip, analyzing the microchip data and the microchip effective mark signals, transmitting the head microchip and the head microchip effective mark signals containing router address information to the routing decoding module, and simultaneously outputting the microchip data and the microchip effective mark signals to the virtual channel module;
the virtual channel module is used for receiving the flit data and the flit valid flag signal sent by the input module and caching the flit data and the flit valid flag signal into a virtual channel cache formed by FIFO;
the route decoding module is configured to perform path planning on the flit data and the flit valid flag signal input to the virtual channel module, determine to send to the switch according to a planned path, select, by using the switch, a request signal to be output in an east, south, west, north, or local direction, establish a link with the output port, and output the flit data;
and the output port is used for reading the flit data from the FIFO of the virtual channel cache in the corresponding virtual channel module according to the link of the exchange switch and sending the flit data to a resource node or the next-stage router body.
The input module comprises a first microchip effective mark signal receiving unit, a first microchip data receiving unit, a first microchip effective mark signal analyzing unit, a first head microchip data analyzing unit, a first microchip effective mark signal output unit and a first microchip data output unit;
the first microchip effective mark signal receiving unit is used for receiving a resource node transmitted by an analog-to-digital conversion chip or a microchip effective mark signal transmitted by the router body at the previous stage;
the first microchip data receiving unit is used for receiving the resource node transmitted by the analog-to-digital conversion chip or microchip data transmitted by the router body at the upper stage;
the first microchip effective mark signal analyzing unit is used for analyzing the microchip effective mark signals and sending the microchip effective mark signals to the routing decoding module;
the first head microchip data analysis unit is used for clamping the head microchip data according to the received microchip number counter and sending the head microchip data to the routing decoding module;
the first microchip effective mark signal output unit is used for outputting the microchip effective mark signal to the virtual channel module;
the first flit data output unit is used for outputting the flit data to the virtual channel module.
The virtual channel module comprises a second microchip effective mark signal receiving unit, a second microchip data receiving unit and a first microchip analyzing and receiving unit;
the second microchip effective mark signal receiving unit is used for receiving the microchip effective mark signals output by the first microchip effective mark signal output unit and caching the microchip effective mark signals into a virtual channel cache formed by FIFO;
the second flit data receiving unit is used for receiving the flit data output by the first flit data output unit and caching the flit data into a virtual channel cache formed by FIFO;
the first head microchip analysis receiving unit receives the mark signal which is transmitted by the routing decoding module and completes the channel head microchip analysis.
The routing decoding module comprises a router body address acquisition unit, a second microchip effective sign signal receiving unit, a second head microchip data receiving unit, a south direction output unit, a north direction output unit, a west direction output unit, an east direction output unit and a local direction output unit;
the router body address obtaining unit is used for obtaining the address of the router body at present;
the second microchip effective mark signal receiving unit is used for receiving the microchip effective mark signals analyzed by the first microchip effective mark signal analyzing unit;
the second head microchip data receiving unit is used for receiving the head microchip data sent by the first head microchip data analysis unit;
the south direction output unit is configured to compare the current router body address acquired by the router body address acquisition unit with an address resolved by the header flit, and if the current router body address and the address resolved by the header flit are the same, transmit the signal to the virtual channel module and the switch at the same time, output a request signal to the south direction, and complete a flag signal resolved by the header flit;
the north direction output unit is used for comparing the current router body address acquired by the router body address acquisition unit with the address resolved by the head microchip, if the current router body address acquired by the router body address acquisition unit is the same as the address resolved by the head microchip, the north direction output unit simultaneously transmits the signal to the virtual channel module and the exchange switch, outputs a request signal to the north direction, and completes the mark signal resolved by the head microchip;
the western direction output unit is configured to compare the current router body address acquired by the router body address acquisition unit with the address resolved by the header flit, and if the current router body address acquired by the router body address acquisition unit is the same as the address resolved by the header flit, transmit the signal to the virtual channel module and the switch at the same time, output a request signal to the western direction, and complete a flag signal resolved by the header flit;
the east direction output unit is used for comparing the current router body address acquired by the router body address acquisition unit with the address resolved by the head microchip, if the current router body address acquired by the router body address acquisition unit is the same as the address resolved by the head microchip, the signal is simultaneously transmitted to the virtual channel module and the exchange switch, and a request signal is output to the east direction to complete the mark signal resolved by the head microchip;
the local direction output unit is configured to compare the current router body address acquired by the router body address acquisition unit with the address resolved by the header flit, and if the current router body address acquired by the router body address acquisition unit is the same as the address resolved by the header flit, transmit the signal to the virtual channel module and the switch at the same time, output a request signal to a local direction, and complete a flag signal resolved by the header flit.
The invention has the beneficial effects that: through a plurality of router bodies, data interaction is formed between each router body and an external analog-to-digital conversion chip and between each router body and an upper computer; the router comprises router bodies, wherein input ports and output ports are arranged in the four directions of the south, the east and the north of each router body, local ports are arranged between the directions of the south, the west and the north of each router body, and the input ports, the output ports and the ports of each router body are connected with a switch through data links, so that the router specially designed for a high-speed data acquisition system is designed. The structure of the NoC router for high-speed data acquisition is simplified, the overall development difficulty and period of the NoC-based high-speed data acquisition system are reduced, the designed router has better time sequence and lower time delay, the defect that the NoC router for high-speed data acquisition cannot meet the requirement of high-speed data acquisition bandwidth is overcome, and the defects that the interface of the NoC router for high-speed data acquisition is poor in flexibility and expandability are overcome.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a NoC-based high-speed data acquisition system according to the present invention.
Fig. 2 is a schematic diagram of the internal structure of a single router body of the present invention.
Fig. 3 is an internal block diagram of a single directional input port and output port of the present invention.
Fig. 4 is a schematic diagram of the structure of the input module of the present invention.
Fig. 5 is a schematic diagram of the structure of the virtual channel module of the present invention.
Fig. 6 is a schematic diagram of the structure of the routing decoding module of the present invention.
Fig. 7 is a schematic diagram of the structure of the output port of the present invention.
The router comprises a router body 1, an analog-to-digital conversion chip 2, an input port 3, an output port 4, an upper computer 5, an input module 6, a virtual channel module 7 and a route decoding module 8.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the description of the present invention, it is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, and are used merely for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention. Further, in the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
The invention provides a NoC router for high-speed data acquisition, which comprises a plurality of router bodies 1, wherein data interaction is formed between each router body 1 and an external analog-to-digital conversion chip 2 and between each router body 1 and an upper computer 5;
an input port 3 and an output port 4 are arranged in the four directions of the south, the east and the north of each router body 1, a local port is arranged between the directions of the south, the west and the north of each router body 1, and each input port 3, each output port 4 and the body port are connected with a switch through a data link;
the analog-to-digital conversion chip 2 is used for acquiring data, performing analog-to-digital conversion on acquired data information to obtain data of resource nodes, and transmitting the data of the resource nodes to the corresponding input ports 3;
each input port 3 is configured to receive and analyze data of the resource node transmitted by the analog-to-digital conversion chip 2 or data sent by the router body 1 at the previous stage, and output data to the output port 4;
the output port 4 is used for receiving the output data and sending the received data to the next level of the router body 1 or the upper computer 5;
and the upper computer 5 is used for receiving the data output by the output port 4 and analyzing and processing the data.
In the present embodiment, as shown in fig. 1: taking a NoC system with a 3 x 3mesh architecture as an example, the structural relationship of data interaction between an external ADC and a router body 1, between the router body 1 and between the router body 1 and an upper computer 5 can be seen, and the position of the router body 1 in a high-speed data acquisition system based on the NoC; and interface protocols between routers are mostly self-defined, and there are technical problems of poor flexibility and poor expandability to carry out improved design on the internal structure of the router.
Further, each of the input ports 3 includes an input module 6, a virtual channel module 7 and a routing decoding module 8, the input module 6 is respectively connected to the virtual channel module 7 and the routing decoding module 8, and the virtual channel module 7 and the routing decoding module 8 are connected to each other;
the input module 6 is configured to receive the resource node transmitted by the analog-to-digital conversion chip 2 or the flit data and the flit valid flag signal transmitted by the router body 1 at the previous stage, analyze the flit data and the flit valid flag signal, transmit the analyzed header flit and header flit valid flag signal including router address information to the routing decoding module 8, and output the flit data and the flit valid flag signal to the virtual channel module 7;
the virtual channel module 7 is configured to receive the flit data and the flit valid flag signal sent by the input module 6, and buffer the flit data and the flit valid flag signal into a virtual channel buffer formed by an FIFO;
the route decoding module 8 is configured to perform path planning on the flit data and the flit valid flag signal input to the virtual channel module 7, determine to send to the switch according to a planned path, select to output a request signal in an east, south, west, north, or local direction by using the switch, establish a link with the output port 4, and output the flit data, where the route decoding module is configured to perform path planning on the flit data and the flit valid flag signal input to the virtual channel module 7, and the path planning implements path planning by using an XY deterministic routing algorithm.
The output port 4 is configured to read the flit data from the FIFO of the virtual channel cache in the corresponding virtual channel module 7 according to the link of the switch, and send the flit data to the resource node or the next-stage router body 1.
In this embodiment, as shown in fig. 2, the router body 1 is an internal structure of a single router body 1, and the router body 1 has five ports, which are in the east, west, south, north and local directions, respectively, and are configured to receive data of a previous router body 1 or a resource node connected to an ADC, and also to send data to a next router body 1 or a resource node connected to an upper computer 5, where each port has the same structure. The middle part is also provided with a switch which is responsible for connecting the data links of different ports together.
Fig. 3 shows the internal structure of a single-direction input port 3 and an output port 4, and each input port 3 or output port 4 adopts the same structure, so the western-direction port is taken as an example. Wherein the input port 3 includes: an input module 6, a virtual channel module 7 and a route decoding module 8; the output port 4 includes: and an output module. The interface protocols of the modules in the input port 3 and the output port 4 both use the AXI-Stream mode, so that the time delay caused by complex handshake signals is saved, and the structure of the module is simplified. The invention is exemplified by a router structure of one channel, which can increase the number of channels according to actual requirements, thereby enabling the router to have higher bandwidth.
Further, the input module 6 includes a first flit valid flag signal receiving unit, a first flit data receiving unit, a first flit valid flag signal analyzing unit, a first head flit data analyzing unit, a first flit valid flag signal output unit, and a first flit data output unit;
the first microchip effective mark signal receiving unit is used for receiving a resource node transmitted by the analog-to-digital conversion chip 2 or a microchip effective mark signal transmitted by the router body 1 at the previous stage;
the first microchip data receiving unit is used for receiving the resource node transmitted by the analog-to-digital conversion chip 2 or microchip data transmitted by the router body 1 at the previous stage;
the first microchip effective flag signal analyzing unit is configured to analyze the microchip effective flag signal and send the microchip effective flag signal to the routing decoding module 8;
the first head microchip data analysis unit is used for blocking the head microchip data according to the received number counter of the flits and sending the head flit data to the routing decoding module 8;
the first flit valid flag signal output unit is configured to output the flit valid flag signal to the virtual channel module 7;
the first flit data output unit is configured to output the flit data to the virtual channel module 7.
In this embodiment, as shown in fig. 4, the input module 6 is mainly responsible for receiving the data flit of the previous router, then parsing the flit, and sending the separated head flit to the routing decoding module 8 for parsing. The signal ports are explained in detail as follows:
router _ clk: the synchronized router clock.
rst _ n: the clock synchronization completion signal serves as a reset of the router.
The first flit valid flag signal receiving unit (s _ axi _ rx _ valid): the input flit is valid to mark signal. The flit data is transmitted from the resource node or the previous router.
The first flit data receiving unit (s _ axi _ rx _ flit [ n-1:0 ]): input flit data. The resource node or the previous router is transmitted along with the microchip valid flag signal.
The first flit valid flag signal parsing unit (head _ valid): the head microchip effectively marks the signal. The valid flag signal accompanying the parsed header flit data is transmitted to the routing decoding module 8.
The first head flit data parsing unit (head _ flit [ n-1:0 ]): and (4) according to the received microchip number, the counter clamps the data of the head microchip. And analyzing the flit data of the resource node or the previous-stage router, and transmitting the extracted head flit containing the router address information to the routing decoding module 8.
The first flit valid flag signal output unit (m _ axi _ tx _ valid): and outputting a microchip valid flag signal. The flag signal is passed to the virtual channel module 7 along with the flit data valid.
The first flit data output unit (m _ axi _ tx _ flit [ n-1:0 ]): and outputting the microchip data. The received microchip data is transferred to the virtual channel module 7.
The working process is as follows: the microchip data and the microchip data valid flag signal sent by the resource node or the previous-stage router enter the input module 6, then the microchip data is analyzed, the head microchip is analyzed and sent to the routing decoding module 8, and meanwhile, the microchip data and the microchip data valid flag signal are output to the virtual channel module 7.
Further, the virtual channel module 7 includes a second flit valid flag signal receiving unit, a second flit data receiving unit, and a first flit parsing receiving unit;
the second microchip effective mark signal receiving unit is used for receiving the microchip effective mark signals output by the first microchip effective mark signal output unit and caching the microchip effective mark signals into a virtual channel cache formed by FIFO;
the second flit data receiving unit is used for receiving the flit data output by the first flit data output unit and caching the flit data into a virtual channel cache formed by FIFO;
the first header microchip analysis receiving unit receives the flag signal for completing the channel header microchip analysis transmitted from the routing decoding module 8.
The virtual channel module 7 further includes a second read enable signal unit and a second virtual channel buffer read unit, where the second read enable signal unit reads the read enable signal of the virtual channel buffer FIFO.
And the second virtual channel cache reading unit is used for reading the flit data from the FIFO of the virtual channel cache.
In this embodiment, as shown in fig. 5, the virtual channel module 7 mainly functions to control when the flit data accesses the flit data into the virtual channel cache, and to cache the flit data input into the virtual channel. The signal ports are explained in detail as follows:
router _ clk: the synchronized router clock.
rst _ n: the clock synchronization completion signal serves as a reset of the router.
rd _ clk: the virtual channel caches a clock for reading the flit data.
The second flit valid flag signal receiving unit (s _ axi _ rx _ valid): and inputting the microchip valid flag signal buffered by the virtual channel. The input module 6 is accompanied by the microchip data.
The second flit data receiving unit (s _ axi _ rx _ flit [ n-1:0 ]): and inputting the flit data cached in the virtual channel. The input module 6 is accompanied by a microchip valid flag signal.
First header flit parsing receiving unit (req _ x _ s): the route decoding module 8 completes the mark signal of the channel head microchip analysis. And is transmitted by the routing decoding module 8.
Second read enable signal unit (m _ axi _ tx _ valid): a read enable signal for the virtual channel. Is also the read enable signal of the virtual channel buffer FIFO.
Second virtual channel cache read unit (m _ axi _ tx _ flit [ n-1:0 ]): and the virtual channel reads out the flit data. The virtual channel buffers the flit data read by the FIFO.
The working process is as follows: the router is responsible for receiving the flit data sent by the two channels of the input module 6, then storing the flit data into a virtual channel cache formed by FIFOs, wherein the depth of each FIFO is one frame of flit data, and the width of each FIFO is the bit width of one flit, and after receiving the decoding result of the routing decoding module 8, the router reads the flit data from the FIFOs and transmits the flit data to the switch.
Further, the routing decoding module 8 includes an address obtaining unit of the router body 1, a second flit valid flag signal receiving unit, a second head flit data receiving unit, a south direction output unit, a north direction output unit, a west direction output unit, an east direction output unit and a local direction output unit;
the router body 1 address obtaining unit is configured to obtain a current address of the router body 1;
the second microchip effective mark signal receiving unit is used for receiving the microchip effective mark signals analyzed by the first microchip effective mark signal analyzing unit;
the second head microchip data receiving unit is used for receiving the head microchip data sent by the first head microchip data analysis unit;
the south direction output unit is configured to compare the current address of the router body 1 acquired by the router body 1 address acquisition unit with the address resolved by the header microchip, and if the current address of the router body 1 acquired by the router body 1 address acquisition unit is the same as the address resolved by the header microchip, transmit the signal to the virtual channel module 7 and the switch at the same time, and output a request signal in the south direction to complete a flag signal for resolving the header microchip;
the north direction output unit is configured to compare the current address of the router body 1 acquired by the address acquisition unit of the router body 1 with the address resolved by the header microchip, and if the current address of the router body 1 and the address resolved by the header microchip are the same, transmit the signal to the virtual channel module 7 and the switch at the same time, output a request signal in the north direction, and complete a flag signal resolved by the header microchip;
the west direction output unit is configured to compare the current address of the router body 1 acquired by the address acquisition unit of the router body 1 with the address resolved by the header flit, and if the current address of the router body 1 and the address resolved by the header flit are the same, transmit the signal to the virtual channel module 7 and the switch at the same time, output a request signal to the west direction, and complete a flag signal for resolving the header flit;
the east direction output unit is used for comparing the current address of the router body 1 acquired by the router body 1 address acquisition unit with the address resolved by the head microchip, if the current address of the router body 1 and the address resolved by the head microchip are the same, the signal is simultaneously transmitted to the virtual channel module 7 and the exchange switch, and a request signal is output to the east direction to complete the mark signal resolved by the head microchip;
the local direction output unit is configured to compare the current address of the router body 1 acquired by the address acquisition unit of the router body 1 with the address resolved by the header microchip, and if the current address of the router body 1 and the address resolved by the header microchip are the same, transmit the signal to the virtual channel module 7 and the switch at the same time, output a request signal to the local direction, and complete a flag signal for resolving the header microchip.
In this embodiment, as shown in fig. 6, the routing decoding module 8 is responsible for performing path planning on data input into the virtual channel module 7, and adopts an XY deterministic routing algorithm to implement path planning. The signal ports are explained in detail as follows:
router _ clk: the synchronized router clock.
rst _ n: the clock synchronization completion signal serves as a reset of the router.
The router body 1 address acquisition unit (router _ addr [ m:0 ]): the address of the current router. For comparison with the address resolved by the header flit to determine the flow direction of the data.
Second flit valid flag signal pickup unit (head _ valid): the head microchip effectively marks the signal.
Second-head flit data receiving unit (head _ flit [ n-1:0 ]): head flit data. The address of the current router is compared after being analyzed and transmitted by the input module 6.
The south-direction output unit (req _ x _ s): the signal is sent to the exchange switch to output a request signal to the south, and is also a mark signal for completing the analysis of the head microchip. The address of the current router is compared with the address resolved by the head microchip, and if the addresses are the same, the signal is simultaneously transmitted to the virtual channel module 7 and the switch.
The north direction output unit (req _ x _ n): and sending a north direction output request signal to the exchange switch, wherein the north direction output request signal is also a mark signal for completing the analysis of the head microchip. The address of the current router is compared with the address resolved by the head microchip, and if the addresses are the same, the signal is simultaneously transmitted to the virtual channel module 7 and the switch.
The west direction output unit (req _ x _ w): and sending a request signal to the exchange switch for outputting in the western direction, wherein the request signal is also a mark signal for completing the analysis of the head microchip. The address of the current router is compared with the address resolved by the head microchip, and if the addresses are the same, the signal is simultaneously transmitted to the virtual channel module 7 and the switch.
The eastern direction output unit (req _ x _ e): the signal is sent to the exchange switch to output a request signal to the east direction, and is also a mark signal for completing the analysis of the head microchip. The address of the current router is compared with the address resolved by the head microchip, and if the addresses are the same, the signal is simultaneously transmitted to the virtual channel module 7 and the switch.
The local direction output unit (req _ x _ l): and sending the request signal to the cross switch to output the request signal to the local direction, wherein the request signal is also a mark signal for completing the analysis of the head microchip. The address of the current router is compared with the address resolved by the head microchip, and if the addresses are the same, the signal is simultaneously transmitted to the virtual channel module 7 and the switch.
The working process is as follows: and comparing the head micro data transmitted by the input module 6 with the address of the current router, determining which direction to output the request signal transmitted to the exchange switch module through an XY deterministic routing algorithm, and establishing a link with the output module to output the microchip data.
Furthermore, the output module comprises a flit valid flag signal receiving unit of a virtual channel cache, a flit data receiving unit of the virtual channel cache, a read enable signal unit of the virtual channel, and a flit data output unit read out by the virtual channel;
the microchip effective mark signal receiving unit of the virtual channel cache is used for receiving the microchip effective mark signals of the virtual channel cache;
the flit data receiving unit of the virtual channel cache is used for receiving the flit data of the virtual channel cache;
the read enabling signal unit of the virtual channel is used for outputting a read enabling signal of the virtual channel and transmitting the read enabling signal to a resource node or a next-stage router along with microchip data;
and the microchip data output unit read by the virtual channel is used for outputting the microchip data read by the virtual channel.
In this embodiment, as shown in fig. 7, the output module mainly functions to send flit data transmitted after the switch is linked to the resource node or the next-stage router. The signal ports are explained in detail as follows:
router _ clk: the synchronized router clock.
rst _ n: the clock synchronization completion signal serves as a reset of the router.
A flit valid flag signal receiving unit (s _ axi _ rx _ valid) of the virtual lane buffer: and inputting the microchip valid flag signal buffered by the virtual channel. The data of the flit is transmitted from the virtual channel module 7.
A flit data receiving unit (s _ axi _ rx _ flit [ n-1:0]) of the virtual channel buffer: and inputting the flit data cached in the virtual channel. And (4) caching the read micro-slice data in the virtual channel.
A read enable signal unit (m _ axi _ tx _ valid) of the dummy channel: a read enable signal for the virtual channel. With the microchip data being transmitted to the resource node or the next level router.
A flit data output unit (m _ axi _ tx _ flit [ n-1:0]) read out by the virtual channel: and the virtual channel reads out the flit data. And transmitting a flit data valid flag signal to the resource node or the next-stage router.
The working process is as follows: and reading the flit data from the FIFO of the virtual channel cache in the corresponding virtual channel module 7 according to the link of the switch, and sending the data to the resource node or the next-stage router.
In summary, the AXI-Stream bus protocol is used as an interface for communication between routers for the first time, and the static routing algorithm is used in the NoC router for high-speed data acquisition to improve performance, so that the design simplifies the structure of the NoC router for high-speed data acquisition, reduces the development difficulty and period of the whole NoC-based high-speed data acquisition system, and makes the designed router have better time sequence and lower delay; the defect that a NoC router for high-speed data acquisition cannot meet the requirement of high-speed data acquisition bandwidth is overcome; the defects of poor flexibility and poor expandability of the NoC router interface for high-speed data acquisition are overcome.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (5)
1. The NoC router for high-speed data acquisition is characterized by comprising a plurality of router bodies, wherein data interaction is formed between each router body and an external analog-to-digital conversion chip and between each router body and an upper computer;
the router comprises a router body, wherein the router body is provided with an input port and an output port in the four directions of the south, the east, the west and the north, a local port is arranged between the directions of the south, the west and the north of the router body, and the input port, the output port and the body port are connected with a switch through a data link;
the analog-to-digital conversion chip is used for acquiring data, performing analog-to-digital conversion on acquired data information to obtain data of resource nodes, and transmitting the data of the resource nodes to the corresponding input ports;
each input port is used for receiving the data of the resource node transmitted by the analog-to-digital conversion chip or the data sent by the router body at the upper stage, analyzing the data and outputting the data to the output port;
the output port is used for receiving the output data and sending the received data to the next level of router body or the upper computer;
and the upper computer is used for receiving the data output by the output port and analyzing and processing the data.
2. The NoC router for high-speed data acquisition of claim 1, wherein each of the input ports comprises an input module, a virtual channel module and a routing and decoding module, the input module is connected with the virtual channel module and the routing and decoding module respectively, and the virtual channel module and the routing and decoding module are connected with each other;
the input module is used for receiving the microchip data and the microchip effective mark signals transmitted by the resource nodes or the router body at the upper stage from the analog-to-digital conversion chip, analyzing the microchip data and the microchip effective mark signals, transmitting the head microchip and the head microchip effective mark signals containing router address information to the routing decoding module, and simultaneously outputting the microchip data and the microchip effective mark signals to the virtual channel module;
the virtual channel module is used for receiving the flit data and the flit valid flag signal sent by the input module and caching the flit data and the flit valid flag signal into a virtual channel cache formed by FIFO;
the route decoding module is configured to perform path planning on the flit data and the flit valid flag signal input to the virtual channel module, determine to send to the switch according to a planned path, select, by using the switch, a request signal to be output in an east, south, west, north, or local direction, establish a link with the output port, and output the flit data;
and the output port is used for reading the flit data from the FIFO of the virtual channel cache in the corresponding virtual channel module according to the link of the exchange switch and sending the flit data to a resource node or the next-stage router body.
3. The NoC router for high-speed data acquisition according to claim 2, wherein the input module includes a first flit valid flag signal receiving unit, a first flit data receiving unit, a first flit valid flag signal parsing unit, a first head flit data parsing unit, a first flit valid flag signal output unit, a first flit data output unit;
the first microchip effective mark signal receiving unit is used for receiving a resource node transmitted by an analog-to-digital conversion chip or a microchip effective mark signal transmitted by the router body at the previous stage;
the first microchip data receiving unit is used for receiving the resource node transmitted by the analog-to-digital conversion chip or microchip data transmitted by the router body at the upper stage;
the first microchip effective mark signal analyzing unit is used for analyzing the microchip effective mark signals and sending the microchip effective mark signals to the routing decoding module;
the first head microchip data analysis unit is used for clamping the head microchip data according to the received microchip number counter and sending the head microchip data to the routing decoding module;
the first microchip effective mark signal output unit is used for outputting the microchip effective mark signal to the virtual channel module;
the first flit data output unit is used for outputting the flit data to the virtual channel module.
4. The NoC router for high-speed data acquisition of claim 3, wherein the virtual channel module comprises a second flit valid flag signal receiving unit, a second flit data receiving unit, and a first header flit parsing receiving unit;
the second microchip effective mark signal receiving unit is used for receiving the microchip effective mark signals output by the first microchip effective mark signal output unit and caching the microchip effective mark signals into a virtual channel cache formed by FIFO;
the second flit data receiving unit is used for receiving the flit data output by the first flit data output unit and caching the flit data into a virtual channel cache formed by FIFO;
the first head microchip analysis receiving unit receives the mark signal which is transmitted by the routing decoding module and completes the channel head microchip analysis.
5. The NoC router for high-speed data acquisition of claim 4, wherein the routing decoding module comprises a router body address acquisition unit, a second flit valid flag signal acquisition unit, a second header flit data acquisition unit, a south direction output unit, a north direction output unit, a west direction output unit, an east direction output unit, and a local direction output unit;
the router body address obtaining unit is used for obtaining the address of the router body at present;
the second microchip effective mark signal receiving unit is used for receiving the microchip effective mark signals analyzed by the first microchip effective mark signal analyzing unit;
the second head microchip data receiving unit is used for receiving the head microchip data sent by the first head microchip data analysis unit;
the south direction output unit is configured to compare the current router body address acquired by the router body address acquisition unit with an address resolved by the header flit, and if the current router body address and the address resolved by the header flit are the same, transmit the signal to the virtual channel module and the switch at the same time, output a request signal to the south direction, and complete a flag signal resolved by the header flit;
the north direction output unit is used for comparing the current router body address acquired by the router body address acquisition unit with the address resolved by the head microchip, if the current router body address acquired by the router body address acquisition unit is the same as the address resolved by the head microchip, the north direction output unit simultaneously transmits the signal to the virtual channel module and the exchange switch, outputs a request signal to the north direction, and completes the mark signal resolved by the head microchip;
the western direction output unit is configured to compare the current router body address acquired by the router body address acquisition unit with the address resolved by the header flit, and if the current router body address acquired by the router body address acquisition unit is the same as the address resolved by the header flit, transmit the signal to the virtual channel module and the switch at the same time, output a request signal to the western direction, and complete a flag signal resolved by the header flit;
the east direction output unit is used for comparing the current router body address acquired by the router body address acquisition unit with the address resolved by the head microchip, if the current router body address acquired by the router body address acquisition unit is the same as the address resolved by the head microchip, the signal is simultaneously transmitted to the virtual channel module and the exchange switch, and a request signal is output to the east direction to complete the mark signal resolved by the head microchip;
the local direction output unit is configured to compare the current router body address acquired by the router body address acquisition unit with the address resolved by the header flit, and if the current router body address acquired by the router body address acquisition unit is the same as the address resolved by the header flit, transmit the signal to the virtual channel module and the switch at the same time, output a request signal to a local direction, and complete a flag signal resolved by the header flit.
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