CN102685017A - On-chip network router based on field programmable gate array (FPGA) - Google Patents
On-chip network router based on field programmable gate array (FPGA) Download PDFInfo
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Abstract
The invention discloses an on-chip network router based on a field programmable gate array (FPGA). Multiple routers are connected together through internet protocol (IP) multiplex to form a communication network. Each router mainly consists of an exchange switcher and port link modules in the n+1 directions, wherein the n represents the number of existing adjacent routers, and the port link module in each direction comprises an input virtual channel caching module, a virtual channel controller, a router decoder and a request arbiter. The on-chip network router based on the FPGA has the advantages of being simple in structure, low in resource using rate, low in power consumption and reusable, can form the communication network through the IP multiplex technology and is applied in an on-chip network system.
Description
Technical field
The present invention relates to the internuclear communication technical field of on-chip multi-processor, be specifically related to a kind of network-on-chip router based on FPGA.
Background technology
SOC(system on a chip) is comparatively ripe at present method of designing integrated circuit, and its design philosophy is the integral body from system, on single chip, accomplishes the function of whole system.Along with the continuous progress of semiconductor process techniques, chip also develops rapidly towards miniaturization, complicated direction.The further increase of SOC(system on a chip) scale makes that the quantity that is integrated in IP kernel on the one chip is more and more, needs higher bandwidth to satisfy the requirement of system.Yet reducing of metal live width and spacing, the increase that not only brings dead resistance on the line causes the increase of coupling capacitance between line simultaneously, has seriously limited bus bandwidth and power consumption is sharply increased.Make SOC(system on a chip) in design process, run into communication capacity and be difficult to satisfy problems such as system requirements, global clock are difficult to synchronously, restricted the scale and the quantity that are integrated in IP kernel on the one chip.
(Network-on-chip NoC) has used for reference the thought of computer network communication to network-on-chip, replaces traditional bus communication mode with route and packet-switch technology, forms to have the holonomic system of calculating, communication function.Simultaneously; Use Global Asynchronous local synchronization (Globally Asynchronous Locally Synchronous--GALS) mechanism; Each resource node all is operated in the clock zone of oneself; Then carry out asynchronous communication between the different resources node, solved bus-structured single clock stationary problem well, thereby thoroughly solved power consumption and area for cutting that huge clock trees is brought through OCN.
Routing node is responsible for the address according to source node and destination node as the significant components of network-on-chip, according to certain routing algorithm dispense path, realizes the data communication between source node and the destination node.Routing node is the basis that makes up network-on-chip, and the quality of its performance plays crucial effects to the design and the performance of SOC(system on a chip).Compare with parallel computer, internet and computer network; Network-on-chip has the strict power consumption and the restriction of resource, so want that project organization is simple, resource utilization is low, efficient, low-power consumption and reusable network-on-chip router be most important to the establishment network-on-a-chip.
Summary of the invention
Technical problem to be solved by this invention provides a kind of network-on-chip router based on FPGA; It has simple in structure, resource utilization is low, low-power consumption and reusable characteristics; And can form communication network through the IP reuse technology, be applied in the network-on-a-chip.
For addressing the above problem, a kind of network-on-chip router based on FPGA that the present invention designed links together a plurality of routers through IP reuse, forms communication network.Above-mentioned each router mainly is made up of the port link module of alteration switch and n+1 direction, and wherein n is the number with the current router neighboring router;
Alteration switch is responsible for the exchanges data between each port link module of router interior;
The port link module of each direction includes input Virtual Channel cache module, Virtual Channel controller, route decoder and request moderator; Wherein,
Input Virtual Channel cache module comprises that Virtual Channel write selector, Virtual Channel, Virtual Channel read selector; Virtual Channel write selector, the Virtual Channel that provides according to the Virtual Channel controller number are selected the Virtual Channel that will write; Virtual Channel is read selector, and the Virtual Channel that provides according to the route decoder number is selected the Virtual Channel that will read; Virtual Channel is attempted by the asynchronous first in first out data buffer that Virtual Channel write selector and Virtual Channel read between the selector by at least 2 to be formed, the data that forward in order to the last router of buffer memory;
The Virtual Channel controller behind the request signal that the adjacent direction request moderator of receiving last router sends, selects a Virtual Channel to give last router answer signal simultaneously according to the current network congestion condition;
The route decoder; When in Virtual Channel, data being arranged, the microplate information that selection is sent here by the Virtual Channel controller according to the Virtual Channel operating position is called the route computing function and is drawn the direction of next jumping; To sending request signal, set up the link of input and outbound course to the counterparty;
The request moderator; When same direction was sent out request signal, with the mode of poll, the request signal of selecting one of them direction was as final request signal as the route decoder of a plurality of directions; The right to use that has output channel, and to next router transmission application.
In the such scheme, said alteration switch selects 1 multidigit MUX to constitute by n+1 n.
In the such scheme, said Virtual Channel write selector and Virtual Channel are read selector and are preferably constituted by a multidiameter option switch.
In the such scheme, Virtual Channel preferably is attempted by the asynchronous first in first out data buffer that Virtual Channel write selector and Virtual Channel read between the selector by 4 and forms.
In the such scheme, it is that the 2D-Mesh topological structure interconnects that said a plurality of routers preferably adopt regular two-dimensional grid.
In the such scheme; With the number of current router neighboring router be 4 (n=4); Be that each router comprises that the port link module of 5 directions forms, the port link module of these 5 directions be respectively east to port link module, south to port link module, west to port link module, the north to port link module and local direction port link module.
The present invention adopts the 2D-Mesh topological structure of rule, realizes based on the worm hole data exchange ways and the deadlock-free certainty XY dimension routing algorithm of Virtual Channel technology.Each router comprises the port link module of an alteration switch and five directions.Each direction adopts identical circuit structure, promptly comprises: Virtual Channel controller, input Virtual Channel cache module, route decoder and request moderator.The Virtual Channel controller is responsible for distributing the use Virtual Channel and accomplishing to the input request responding one of each direction configuration according to the network congestion situation.The route decoder is used for selecting the direction of route, one of each direction configuration.The request moderator adopts the mode of poll to respond answer signal, and each direction is one of output channel configuration.The function of accomplishing each several part with hardware description language Verilog designs, and under the ModeSim simulation software, carries out functional simulation, and in the NoC system based on FPGA, has realized the function of router.
Compared with prior art, the present invention has following characteristics:
(1) uses deadlock-free certainty XY routing algorithm, simplified the circuit of route decoder, saved the use of resource;
(2) used the Virtual Channel technology, Virtual Channel is made up of four asynchronous FIFOs, has reduced the Congestion Level SPCC of network, has realized the GALS technology simultaneously;
(3) each Virtual Channel controller of input Virtual Channel configuration and route decoder; Output channel is not used buffer memory; Only need the configuring request moderator; Data are passed through alteration switch by the input Virtual Channel of a direction, are switched directly in the input Virtual Channel of next router, have reduced the use of buffer memory;
(4) adopt ASIC design cycle method,, realize the function design with the Verilog hardware description language, and on fpga chip, realize router, be applied in the network-on-a-chip, have certain practical significance the design of router sub-module.
Description of drawings
Fig. 1 is a kind of network-on-chip router structural model based on FPGA (adopt 3 * 3 network-on-chips of 2D-Mesh topological structure, among the figure: R representes routing node, and NI representes the resource network interface, and S representes resource node, IC inner passage, EC external channel).
Fig. 2 is the overall structure figure of a router.
Fig. 3 is data format figure.
Fig. 4 is that one of them direction port link module of router is formed structure.
Fig. 5 is the alteration switch sketch map.
Embodiment
A kind of network-on-chip router based on FPGA links together a plurality of routers through IP reuse, forms communication network.Can adopt two dimension or even three-dimensional topology structure between a plurality of routers, like grid type, honeycomb type, star-like or mixed type or the like.But in the present invention, said a plurality of router adopts regular two-dimensional grid topological structure to connect.A kind of network-on-chip router based on FPGA of present embodiment shown in Figure 1 adopts 3 * 3 network-on-chips of 2D-Mesh topological structure, and comprising 9 routers, each router feature is identical with circuit composition structure.In above-mentioned 9 routers, the router in the middle of having only all links to each other with 4 routers on every side, and other routers only need connect 2 or 3 routers, and remaining port can dispose, thus the saving chip area.
Fig. 2 is the structure chart of a router.Each router mainly is made up of the port link module of alteration switch and n+1 direction, and wherein n is the number with the current router neighboring router.Because present embodiment adopts the 2D-Mesh topological structure; Therefore the number of current router neighboring router is 4 (n=4); Be port link module promptly eastern (East), south (South), west (West), north (North), local (Local) 5 directions that each router includes alteration switch (crossbar) and 5 directions, the identical circuit structure of port link module employing of each direction.Local direction port link module and local resource node are accomplished the various forms of IP kernels of calculation task, are responsible for transmitting local resource node data that send and that receive; Other 4 direction port link module are that all directions 4 direction ports link module is connected with other router.
Alteration switch is responsible for the exchanges data between each port link module of router interior, and data are exchanged to the input buffering of another port link module from the input buffering of a port link module, to set up the link between the both direction.Said alteration switch selects 1 multidigit MUX to constitute by n+1 n.In the present embodiment, can think to select 1 multidigit MUX to form by 54.
The port link module of each direction includes input Virtual Channel cache module, Virtual Channel controller, route decoder and request moderator.Wherein,
Input Virtual Channel cache module comprises that Virtual Channel write selector, Virtual Channel, Virtual Channel read selector.Virtual Channel write selector and Virtual Channel are read selector and are constituted by a multidiameter option switch.Virtual Channel write selector, the Virtual Channel that provides according to the Virtual Channel controller number are selected the Virtual Channel that will write.Virtual Channel is read selector, and the Virtual Channel that provides according to the route decoder number is selected the Virtual Channel that will read.Virtual Channel is attempted by the asynchronous first in first out data buffer (asynchronous FIFO) that Virtual Channel write selector and Virtual Channel read between the selector by at least 2 and forms.Virtual Channel not only is used for the data that the last router of buffer memory forwards; And the reading and writing clock of asynchronous FIFO can be asynchronous; Just can use nonsynchronous clock between router and the router like this, resource node and router also can use nonsynchronous clock, realize the GALS technology.In the present embodiment, said Virtual Channel is attempted by the asynchronous first in first out data buffer that Virtual Channel write selector and Virtual Channel read between the selector by 4 and forms.
The Virtual Channel controller behind the request signal that the adjacent direction request moderator of receiving last router sends, selects a Virtual Channel to give last router answer signal simultaneously according to the current network congestion condition.All Virtual Channels on direction port link module are controlled by 1 Virtual Channel controller.Above-mentioned request signal is that the router adjacent with current router sends, such as first router links to each other with the secondary route device, the first router on the left side, and the secondary route device is on the right.So the two adjacent both direction be exactly first router east to the west of secondary route device to; The west of secondary route device to the request signal of Virtual Channel controller only possibly be the east of first router to sending, the east of same first router to request signal only possibly be that the west of secondary route device is to sending.
The effect of Virtual Channel controller has two among the present invention: the first, according to the current network congestion situation Virtual Channel of a free time of selection; The second, guarantee that a complete packet can out of order arrival destination node.After receiving the request signal that adjacent node request moderator sends, the Virtual Channel controller is selected the Virtual Channel that can write to be used for receiving last router data sent according to the current network congestion condition and is given the adjacent node answer signal simultaneously.The right to use that can compete physical path when Virtual Channel is shared physical path; And in the data packet delivery process; Could arrive destination node through a plurality of routing units possibly, so complete packet will be present in the buffer memory of a plurality of routing units with the microplate form.Meanwhile the microplate of other packets also may be sent out application to the Virtual Channel of this direction, when take place stopping up, when route computing unit receives data and do not know whether the frame of application belonged to same packet with last frame at present.If the frame destination node from two different pieces of information bags is consistent; The receiving terminal resource node can be handled these two frames by mistake as the data of same packet; So for the integrality present embodiment that guarantees packet adopts following processing mode: after the Virtual Channel controller is received the request signal that neighboring router sends; Whether the Frame of judging earlier current request belongs to same packet with the Frame that takes place to stop up; If from same packet, request failure is this time explained in the packet transmittance process obstruction has been taken place; If do not belong to same packet, provide answer signal, and select wherein that a Virtual Channel is used for receiving the adjacent node data sent.A plurality of frames that so just can guarantee a packet transmit in same Virtual Channel, and the frame of other packets transmits in other Virtual Channels when take place stopping up, and receiving terminal is received will be a complete packet and can not insert the frame of other packets again.Each direction port module is only controlled with a Virtual Channel controller, rather than each Virtual Channel all is with a controller, has simplified the complexity of circuit, has saved resource on the sheet.
The route decoder is the core component of each direction link port, is responsible for setting up input direction to the link between the outbound course.When in Virtual Channel, data being arranged, the microplate information that selection is sent here by the Virtual Channel controller according to the Virtual Channel operating position is called the route computing function, and is drawn the direction of next jumping, to sending request signal, sets up the link of input and outbound course to the counterparty.In the present embodiment, the route decoder comprises route calculating and controls two modules that computing module is responsible for decoding address information to confirm to want the direction of route; Control module is then sent request signal according to the address that computing module is confirmed to jumping to next, after obtaining answer signal, reads selector according to current Virtual Channel operating position control Virtual Channel, sets up the link between input and the output.Same each direction is only used a route decoder, has reduced the utilization rate of resource.
The request moderator; When same direction was sent out request signal, with the mode of poll, the request signal of selecting one of them direction was as final request signal as the route decoder of a plurality of directions; The right to use that has output channel, and to next router transmission application.
The present invention realizes on based on the FPGA hardware platform, so the basic design cycle of ASIC is taked in the design of router, uses top-down layout strategy.At first provide the functional definition of router and the division of submodule; Design with the Verilog hardware description language then; A complete direction port link module is formed in the correct back of functional verification, forms a complete router together by five port link module and alteration switch.Re-use the IP reuse technology, form communication network, and realized the function of network-on-chip data communication in the network-on-a-chip of on based on fpga chip, building with 9 routers.The generation of deadlock in the routing procedure, the present invention adopts worm hole route switching mode, and adds the Virtual Channel technology, to reduce the blocking probability of passage.Use the certainty source route algorithm-XY dimension preface routing algorithm of shortest path, can effectively reduce the complexity and the resource utilization of circuit.
A complete packet is divided into several microplates (flit), correctly arrives destination node in order to make packet, microplate is divided into 3 types, i.e. a microplate, data microplate and tail microplate.Microplate carries information such as source data packet address, destination address, data packet length.The tail microplate is being represented the termination of packet.The data microplate is present between the two, is the valid data that will transmit.Data structure diagram is as shown in Figure 3.The flow process of data in network is following: at first send to the resource network interface by data and some handshake that it is good that resource node will be packed; Interface adds head type information according to packet information to microplate, sends application to local direction then, after the Virtual Channel controller of local direction is received request signal; Whether determine response request according to current network conditions; Can receive data as if current, then feed back to the interface answer signal, make it that data are deposited in the asynchronous first in first out data buffer; Detect a decoder that data get into according to the address information of carrying in the microplate to the counterparty to the request moderator send request signal; After obtaining asking the answer signal of moderator, data are taken out from asynchronous first in first out data buffer, through alteration switch; Direction output port output by request; And then enter into the Virtual Channel of next router, accomplished once and be forwarded to another direction from a direction, just from a routers exchange to the next router.
The course of work of each module and principle are introduced as follows in detail:
When data get into some direction of a router; The course of work in a direction is following: in Fig. 4; After the Virtual Channel controller is received the request signal that adjacent node request moderator sends, judged whether that earlier obstruction has taken place packet in current router, if stop up; Whether the Frame of judging current request belongs to same packet with the Frame that takes place to stop up; If from same packet, request failure is this time explained in the packet transmittance process obstruction has been taken place; If taking place to stop up perhaps, the Frame of current request does not belong to same packet with the Frame that takes place to stop up; Provide answer signal; And select wherein that the Virtual Channel of a sky is used for receiving the adjacent node data sent, receive the adjacent node data sent by the control of Virtual Channel write selector.When taking place to stop up, can not replied from the follow-up data of same packet; Data from different packets can be replied; A plurality of frames that so just can guarantee a packet transmit in same Virtual Channel; The frame of other packets transmits in other Virtual Channels when take place stopping up, and receiving terminal is received will be a complete packet and can not insert the frame of other packets again.After providing answer signal and Virtual Channel and selecting number, save the data in this router by the Virtual Channel cache module.
The Virtual Channel write selector is a multidiameter option switch; After receiving the signal that the Virtual Channel controller sends; Input is promptly write enabler flags from the data and the FIFO of a last joint router; According to the associated control signal that the Virtual Channel controller provides, assignment is given corresponding Virtual Channel, makes data sequentially write certain asynchronous first in first out data buffer.
When having detected readable Virtual Channel; The route decoder microplate information that selection is sent here by the Virtual Channel controller according to the Virtual Channel operating position is called the route computing function, the direction that judgement will be transmitted; Send request signal to this direction request moderator; The signal in case meet with a response, decoder control Virtual Channel is read selector and is read the data of Virtual Channel and deliver to alteration switch, thereby sets up link; If can not get answer signal or input Virtual Channel when reading sky, other non-NULLs discrepancy Virtual Channels that link and select that break off with alteration switch carry out transfer of data.The false code of route computing function is following:
The request moderator will receive the request signal from local other 4 directions of route decoder; But the same time can only be given a direction answer signal; So adopt the mechanism of poll to handle the request signal of four direction, select the request signal of a direction and send application, after meeting with a response to next route; Permit answer signal for the route decoder of this direction, treat the request signal of other directions of request signal disappearance continued poll.
The function of alteration switch is that data are exchanged in the input buffering of another port from the input buffering of a port.Internal structure can be thought to select 1 MUX to form by 54; Its structure chart is as shown in Figure 5; When data get into a certain direction port of alteration switch; By the passage of selector according to the selection of the selection signal between several directions output, make input and output port set up link, data forwarding is gone out to another direction.Several selectors can be worked simultaneously, and just router interior can be carried out the data forwarding between a plurality of directions simultaneously.
Can accomplish the process of data according to said process from a routing forwarding to next route, thus the purpose that the network of forming through router between the completion resource node carries out data communication.The routing algorithm that the present invention adopts is prone to realize, forms simple in structurely, and it is few to take resource, and can be applied in the NoC system based on FPGA.
Claims (6)
1. network-on-chip router based on FPGA; Comprise a plurality of routers that link together; It is characterized in that: each router mainly is made up of the port link module of alteration switch and n+1 direction, and wherein n is the router number adjacent with current router;
Alteration switch is responsible for the exchanges data between each port link module of router interior;
The port link module of each direction includes input Virtual Channel cache module, Virtual Channel controller, route decoder and request moderator; Wherein,
Input Virtual Channel cache module comprises that Virtual Channel write selector, Virtual Channel, Virtual Channel read selector; Virtual Channel write selector, the Virtual Channel that provides according to the Virtual Channel controller number are selected the Virtual Channel that will write; Virtual Channel is read selector, and the Virtual Channel that provides according to the route decoder number is selected the Virtual Channel that will read; Virtual Channel is attempted by the asynchronous first in first out data buffer that Virtual Channel write selector and Virtual Channel read between the selector by at least 2 to be formed, the data that forward in order to the last router of buffer memory;
The Virtual Channel controller behind the request signal that the adjacent direction request moderator of receiving last router sends, selects a Virtual Channel to give last router answer signal simultaneously according to the current network congestion condition;
The route decoder; When in Virtual Channel, data being arranged, the microplate information that selection is sent here by the Virtual Channel controller according to the Virtual Channel operating position is called the route computing function and is drawn the direction of next jumping; To sending request signal, set up the link of input and outbound course to the counterparty;
The request moderator; When same direction was sent out request signal, with the mode of poll, the request signal of selecting one of them direction was as final request signal as the route decoder of a plurality of directions; The right to use that has output channel, and to next router transmission application.
2. a kind of network-on-chip router based on FPGA according to claim 1 is characterized in that: said alteration switch selects 1 multidigit MUX to constitute by n+1 n.
3. a kind of network-on-chip router based on FPGA according to claim 1 is characterized in that: said Virtual Channel write selector and Virtual Channel are read selector and are constituted by a multidiameter option switch.
4. a kind of network-on-chip router based on FPGA according to claim 1 is characterized in that: said Virtual Channel is attempted by the asynchronous first in first out data buffer that Virtual Channel write selector and Virtual Channel read between the selector by 4 and forms.
5. according to the described a kind of network-on-chip router based on FPGA of claim 1～4, it is characterized in that: said a plurality of routers adopt regular two-dimensional grid topological structure to connect.
6. a kind of network-on-chip router according to claim 5 based on FPGA; It is characterized in that: with number n=4 of current router neighboring router; Be that each router comprises that the port link module of 5 directions forms, the port link module of these 5 directions be respectively east to port link module, south to port link module, west to port link module, the north to port link module and local direction port link module.
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