CN114647602B - Cross-chip access control method, device, equipment and medium - Google Patents
Cross-chip access control method, device, equipment and medium Download PDFInfo
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- CN114647602B CN114647602B CN202210565747.6A CN202210565747A CN114647602B CN 114647602 B CN114647602 B CN 114647602B CN 202210565747 A CN202210565747 A CN 202210565747A CN 114647602 B CN114647602 B CN 114647602B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a method, a device, equipment and a medium for cross-chip access control, which belong to the field of chips, and the method comprises the following steps: a sending chip receives a register access request; the sending chip packs the register access request into a data packet according to a preset packing rule; the sending chip writes the data packet into a memory access path of the bus interface so that the data packet can be sent to a preset address of the receiving chip through the memory access path; the receiving chip acquires a data packet from a preset address; the receiving chip unpacks the data packet to obtain a register access request; the receiving chip writes the register access information into the register bus so as to facilitate the register in the receiving chip to receive the register access request; and after receiving the register response data, the receiving chip packs the response data and returns the response data through the memory access path to complete one-time complete register access. The invention can omit the arrangement of the register passage crossing the chip, save the occupied area of the chip and reduce the power consumption.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a method, an apparatus, a device, and a medium for cross-chip access control.
Background
Chip-to-chip interconnection techniques are often used in large computing chips, especially in server products. In chip interconnection, there are usually 2 paths required for cross-chip operation, one is a register path for transferring register access information between registers of a chip, and the other is a memory access path for transferring data information between chips.
The memory access path is used for moving large data and has high bandwidth requirement; the register path is mainly used for intermittently transmitting control information between chips, so that the requirements on bandwidth and real-time performance of the register path are much smaller than those of a memory access path.
In the implementation of cross-chip interconnection, each path needs to be physically connected through a PCIe phy (physical layer) and a controller (control layer), but the PCIe phy and the controller corresponding to the register path and the memory access path occupy a large area in a chip and consume large power consumption. Therefore, it is wasteful for the register path whose data amount is not large.
In the prior art, there is a technical scheme for performing simple arbitration and combination on a register access and a memory access, so that although the arrangement of one path (register access) can be omitted, the register access occupies a long time (especially, a read operation needs to wait for response data), thereby seriously affecting the large data transmission performance of the memory access.
Disclosure of Invention
Aiming at the problems that register channels in interconnected chips occupy larger chips in the chips and consume larger power consumption in the prior art, the invention aims to provide a cross-chip access control method, a device, equipment and a medium.
In order to achieve the purpose, the technical scheme of the invention is as follows:
in a first aspect, the present invention provides a cross-chip access control method, which is applied to communication between a sending chip and a receiving chip interconnected through a bus interface, where a physical link of the bus interface includes a memory access path for transmitting data information, and the method includes the following steps:
a sending chip receives a register access request, wherein the register access request carries access information which needs to be transmitted to a register in a receiving chip;
the sending chip packs the register access request into a data packet according to a preset packing rule;
writing the data packet into a memory access path of the bus interface by a sending chip so that the data packet is sent to a preset address of the receiving chip through the memory access path;
the receiving chip acquires the data packet from a preset address of the receiving chip;
the receiving chip unpacks the data packet according to a preset unpacking rule to obtain the register access request;
and the receiving chip writes the register access information into a register bus so that a register in the receiving chip receives the register access request.
Further, the method comprises the following steps:
the receiving chip generates response information;
the receiving chip packages the response information into a response data packet according to the preset packaging rule;
the receiving chip writes the response data packet into a memory access path of the bus interface so that the response data packet is sent to a preset address of the sending chip through the memory access path;
the sending chip acquires the response data packet from a preset address of the sending chip;
and the sending chip unpacks the response data packet according to the preset unpacking rule to obtain the response information.
Preferably, the sending chip and the receiving chip are interconnected through a PCIe bus interface.
In a second aspect, the present invention further provides a device for cross-chip access control, where the device is applied to communication between a sending chip and a receiving chip interconnected through a bus interface, a physical link of the bus interface includes a memory access path for transmitting data information, and the device includes a routing module;
on one side of a sending chip, the routing module is used for receiving a register access request, and the register access request carries access information which needs to be transmitted to a register in a receiving chip; the routing module is further configured to pack the register access request into a data packet according to a preset packing rule, and write the data packet into a memory access path of the bus interface so that the data packet is sent to a preset address of a receiving chip through the memory access path;
on one side of the receiving chip, the routing module is used for acquiring a data packet from a preset address of the receiving chip, unpacking the data packet according to a preset unpacking rule, thereby acquiring a register access request sent by the sending chip, and sending the acquired register access request to a register in the receiving chip.
Further, the system also comprises a response module;
on one side of the receiving chip, the response module is configured to generate response information and send the response information to the routing module after the routing module sends the acquired register access request to a register in the receiving chip, and the routing module is further configured to package the response information into a response packet according to a preset packaging rule, and write the response packet into a memory access path of the bus interface so that the response packet is sent to a preset address of the sending chip through the memory access path;
on one side of the sending chip, the routing module is further configured to obtain a response data packet from a preset address of the chip, and unpack the response data packet according to a preset unpacking rule, so as to obtain response information sent by the receiving chip.
Preferably, the routing module includes:
the receiving unit is used for receiving a register access request, and the register access request carries access information which needs to be transmitted to a register in a receiving chip;
the packing unit is used for packing the register access request into a data packet according to a preset packing rule;
the write-in unit is used for writing the data packet into a memory access path of the bus interface so that the data packet is sent to a preset address of a receiving chip through the memory access path;
the device comprises an acquisition unit, a processing unit and a control unit, wherein the acquisition unit is used for acquiring a data packet from a preset address of a chip;
the unpacking unit is used for unpacking the data packet according to a preset unpacking rule so as to obtain a register access request sent by the receiving chip;
and the sending unit is used for sending the acquired register access request to the register.
Preferably, the routing module sends the register access request to a corresponding register through a register bus.
Preferably, the register bus is an AXI bus protocol.
In a third aspect, the present invention further provides a server cluster with interconnected multiple chips, including multiple nodes interconnected through a bus interface, where a physical link of the bus interface includes a memory access path for transmitting data information, and at least one path is provided between any two of the nodes, and the server cluster is characterized in that: any two of the nodes perform data transmission by the method described above.
Preferably, when at least two paths exist between any two of the nodes, the memory access path for transmitting data information and the memory access path for transmitting register access information between any two of the nodes are respectively established on two different paths.
In a fourth aspect, the present invention further provides an electronic device, including a register, a processor, and a memory, where the electronic device is further provided with a bus interface for communicating with another electronic device, a physical link of the bus interface includes a memory access path for transmitting data information, the memory stores an executable program code, and when the processor calls the executable program code, the method is executed.
In a fifth aspect, the present invention also provides a computer-readable storage medium, in which a computer program is stored, which computer program, when executed by a processor, performs the method as described above.
By adopting the technical scheme, the invention has the beneficial effects that:
1. because the register access request carrying the register access information is transmitted to another chip by the memory access path in a data packet packing mode, the register access request can be obtained by the other chip only by unpacking the received data packet, so that the arrangement of a physical link for realizing the register access between the chips can be saved, and the effective use area of the chips is increased;
2. the method provided by the invention converts the read operation into the full-write operation during cross-chip access, thereby improving the access efficiency; since the read operation needs to wait for the reply of the receiving end, the subsequent access is easily blocked, and the write operation can continue the subsequent operation after sending the write request, thereby effectively improving the cross-chip access efficiency;
3. in the server cluster provided by the invention, when a complex topological connection structure exists between nodes and different paths exist between the two nodes, under the condition that a register path and a memory access path are combined, the interconnection resources of the topology can be greatly saved, and the more complex the topology is, the more obvious the effect is; thus, although the physical link is shared, the routing strategies of the register access path and the memory access path are different, so that the register access path and the memory access path can still take different paths under the same physical topological connection, and the efficiency is optimized.
Drawings
Fig. 1 is a schematic structural diagram of a cross-chip access control apparatus according to the present invention.
Fig. 2 is another schematic structural diagram of a cross-chip access control apparatus according to the present invention.
Fig. 3 is a schematic diagram of the interconnection structure between two chips.
FIG. 4 is a flowchart of a cross-chip access control method according to the present invention.
Fig. 5 is a flowchart of a response information return flow included in the cross-chip access control method according to the present invention.
Fig. 6 is a schematic diagram of a topological connection of a server cluster composed of four chips.
Detailed Description
The following description of the embodiments of the present invention will be made with reference to the accompanying drawings. It should be noted that the description of the embodiments is provided to help understanding of the present invention, and is not intended to limit the present invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
It should be noted that in the description of the present invention, the terms "upper", "lower", "left", "right", "front", "rear", and the like indicate orientations or positional relationships based on structures shown in the drawings, and are only used for convenience in describing the present invention, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the technical scheme, the terms "first" and "second" are only used for referring to the same or similar structures or corresponding structures with similar functions, and are not used for ranking the importance of the structures, or comparing the sizes or other meanings.
In addition, unless expressly stated or limited otherwise, the terms "mounted" and "connected" are to be construed broadly, e.g., the connection may be a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two structures can be directly connected or indirectly connected through an intermediate medium, and the two structures can be communicated with each other. To those skilled in the art, the specific meanings of the above terms in the present invention can be understood in light of the context of the present application, along with the general concepts of the invention.
Example one
A cross-chip access control device is applied to communication among chips which are interconnected through a bus interface, the number of the interconnected chips is usually two, the two chips comprise a sending chip used for sending information and a receiving chip used for receiving information, and it is understood that in practical application, a certain chip can be a sending chip and a receiving chip. The physical link of the bus interface includes a memory access path for transmitting data information, for example, if the bus interface is a PCIe bus interface, a phy and a controller for PCIe are disposed on two interconnected chips, so as to facilitate physical connection.
As shown in fig. 1, the apparatus specifically includes a routing module, which is arranged in chips that are interconnected.
On one side of the sending chip, for example, when a certain chip is used as a sending chip for sending information, the routing module is configured to receive a register access request, where the register access request is input to the sending chip by an external input device, and the register access request carries access information to be transmitted to a register in the receiving chip, so that the receiving chip performs corresponding function control and adjustment according to the access information. Meanwhile, the routing module is further configured to pack the register access request into a data packet according to a preset packing rule, and write the data packet into a memory access path of the bus interface, so that the data packet is sent to a preset address of the receiving chip through the memory access path.
The final format of the data packet conforms to the data sending mode of the memory access path, the memory access path corresponds to storage addresses for storing data in the two interconnected chips, and only a part of specific addresses are required to be separated from the storage addresses and are specially used for storing the data packet, so that the specific addresses are the preset addresses of the chips. And the two chips interconnected through the bus interface are provided with the preset address, so that the two interconnected chips can receive the data packet transmitted by the other side.
On the receiving chip side, that is, when a certain chip is used as a receiving chip for receiving information, the routing module is configured to obtain a data packet from a preset address of the receiving chip, unpack the data packet according to a preset unpacking rule, thereby obtaining a register access request sent by the sending chip, and send the obtained register access request to a register in the receiving chip.
And the preset unpacking rule is matched with the preset packing rule. In addition, the routing module sends the register access request to the register bus in a manner conforming to the register bus protocol, so that the register in the receiving chip obtains the required register access request, and the register bus is preferably the AXI bus protocol.
Therefore, the register access request is transmitted between the interconnected chips once. In addition, the arrangement of a pci phy and a controller for register path transmission in the traditional technical scheme is omitted in the chip, so that the area and the operation power consumption in the chip are saved.
Corresponding to the function of the routing module, this embodiment specifically sets that the routing module includes:
the receiving unit is used for receiving a register access request, and the register access request carries access information which needs to be transmitted to a register in a receiving chip;
the packing unit is used for packing the register access request into a data packet according to a preset packing rule;
the write-in unit is used for writing the data packet into a memory access path of the bus interface so that the data packet can be sent to a preset address of a receiving chip through the memory access path;
the acquisition unit is used for acquiring a data packet from a preset address of the chip;
the unpacking unit is used for unpacking the data packet according to a preset unpacking rule so as to obtain a register access request sent by the receiving chip;
and the sending unit is used for sending the acquired register access request to the register.
In a preferred embodiment, as shown in fig. 2, the apparatus for setting cross-chip access control further comprises a response module.
On the receiving chip side, that is, when a chip is used as a receiving chip for receiving information, the response module is configured to generate response information and send the response information to the routing module after the routing module sends the obtained register access request to the register in the receiving chip, and the routing module is further configured to package the response information into a response packet according to a preset packaging rule, and the routing module continues to write the response packet into the memory access path of the bus interface, so that the response packet is sent to the preset address of the sending chip through the memory access path.
On the transmitting chip side, that is, when a chip is used as a transmitting chip for transmitting information, the routing module is further configured to obtain a response packet sent by an interconnected receiving chip from a preset address of the transmitting chip, and unpack the response packet according to a preset unpacking rule, so as to obtain response information sent by the receiving chip. Thus, one complete register access request cross-chip operation is completed among the interconnected chips.
It can be understood that, since a chip can be used as both a sending chip and a receiving chip, for a single chip, the functions of the routing module and the response module carried by the chip are complete, and when a specific chip interconnection operation is performed, the chips participating in interconnection perform the corresponding functions of the routing module and the response module according to the roles played by the chips.
As shown in fig. 3, which specifically shows a structural schematic diagram of interconnection between two chips, it can be seen that two chips are connected through only one physical link, and in the same chip, register access information is transferred between a register path (register path) and a memory access path (data path) through a routing module and a response module built in the chip, and the register access information is transferred between the two chips by means of the physical link.
Example two
A cross-chip access control method is applied to communication between chips interconnected through a bus interface, where a physical link of the bus interface includes a memory access path for transmitting data information, where the interconnected chips at least include a sending chip and a receiving chip, as shown in fig. 4, and the method includes the following steps:
s1, the sending chip receives the register access request, the register access request carries the access information which needs to be transmitted to the register in the receiving chip;
s2, the sending chip packs the register access request into a data packet according to a preset packing rule;
s3, the sending chip writes the data packet into the memory access path of the bus interface, so that the data packet is sent to the preset address of the receiving chip through the memory access path;
s4, the receiving chip obtains the data packet from the preset address;
s5, unpacking the data packet by the receiving chip according to a preset unpacking rule to obtain a register access request;
s6, the accepting chip writes the register access information into the register bus so that the register in the accepting chip receives the register access request.
In addition, as shown in fig. 5, the method further includes the steps of:
s7, receiving the chip generation response information;
s8, the receiving chip packages the response information into a response data packet according to a preset packaging rule;
s9, the receiving chip writes the response data packet into the memory access path of the bus interface, so that the response data packet is sent to the preset address of the sending chip through the memory access path;
s10, the sending chip obtains the response data packet from the preset address;
and S11, unpacking the response data packet by the sending chip according to a preset unpacking rule to obtain response information.
EXAMPLE III
A server cluster with interconnected multiple chips comprises a plurality of nodes which are interconnected through a bus interface, a physical link of the bus interface comprises a memory access path used for transmitting data information, at least one path is arranged between any two nodes, and the data is transmitted by any two nodes through the method provided by the second embodiment. As shown in fig. 6, a schematic diagram of the topological connection of four chips, two of which are interconnected.
When at least two paths exist between any two nodes, a memory access path for transmitting data information and a memory access path for transmitting register access information between any two nodes are respectively established on two different paths. For example, in FIG. 6, between the S0 chip and the S2 chip, the memory access path for transferring data information may be the path S0-S2, and the memory access path for transferring register access information may be the path S0-S1-S2.
Example four
An electronic device, in particular to a chip, includes a register, a processor and a memory, the electronic device is further provided with a bus interface for communicating with another electronic device, a physical link of the bus interface includes a memory access path for transmitting data information, the memory stores executable program codes, and when the processor calls the executable program codes, the method disclosed in the second embodiment is executed.
EXAMPLE five
A computer storage medium having a computer program stored thereon, the computer program, when executed by a processor, performing the method disclosed in embodiment two.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It will be apparent to those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, and the scope of protection is still within the scope of the invention.
Claims (10)
1. A cross-chip access control method is applied to communication between a sending chip and a receiving chip which are interconnected through a bus interface, a physical link of the bus interface comprises a memory access path used for transmitting data information, and the method is characterized in that: the method comprises the following steps:
a sending chip receives a register access request, wherein the register access request carries access information which needs to be transmitted to a register in a receiving chip;
the sending chip packs the register access request into a data packet according to a preset packing rule;
writing the data packet into a memory access path of the bus interface by a sending chip so that the data packet is sent to a preset address of the receiving chip through the memory access path;
the receiving chip obtains the data packet from a preset address of the receiving chip;
the receiving chip unpacks the data packet according to a preset unpacking rule to obtain the register access request;
the receiving chip writes the register access information into a register bus so that a register in the receiving chip receives the register access request;
wherein the method further comprises the steps of:
the receiving chip generates response information;
the receiving chip packages the response information into a response data packet according to the preset packaging rule;
the receiving chip writes the response data packet into a memory access path of the bus interface so that the response data packet is sent to a preset address of the sending chip through the memory access path;
the sending chip acquires the response data packet from a preset address of the sending chip;
and the sending chip unpacks the response data packet according to the preset unpacking rule to obtain the response information.
2. The method of claim 1, wherein: the sending chip and the receiving chip are interconnected through a PCIe bus interface.
3. A cross-chip access control apparatus, the apparatus being applied to communication between a sending chip and a receiving chip interconnected via a bus interface, a physical link of the bus interface including a memory access path for transmitting data information, the apparatus comprising: the apparatus comprises a routing module;
on one side of a sending chip, the routing module is used for receiving a register access request, and the register access request carries access information which needs to be transmitted to a register in a receiving chip; the routing module is further configured to package the register access request into a data packet according to a preset packaging rule, and write the data packet into a memory access path of the bus interface so that the data packet is sent to a preset address of a receiving chip through the memory access path;
on one side of the receiving chip, the routing module is used for acquiring a data packet from a preset address of the receiving chip, unpacking the data packet according to a preset unpacking rule so as to acquire a register access request sent by the sending chip, and sending the acquired register access request to a register in the receiving chip;
the system also comprises a response module;
on one side of the receiving chip, the response module is configured to generate response information and send the response information to the routing module after the routing module sends the obtained register access request to a register in the receiving chip, and the routing module is further configured to package the response information into a response data packet according to a preset packaging rule, and write the response data packet into a memory access path of the bus interface so that the response data packet is sent to a preset address of the sending chip through the memory access path;
on one side of the sending chip, the routing module is further configured to obtain a response data packet from a preset address of the chip, and unpack the response data packet according to a preset unpacking rule, so as to obtain response information sent by the receiving chip.
4. The apparatus of claim 3, wherein: the routing module comprises:
the receiving unit is used for receiving a register access request, and the register access request carries access information which needs to be transmitted to a register in a receiving chip;
the packing unit is used for packing the register access request into a data packet according to a preset packing rule;
the write-in unit is used for writing the data packet into a memory access path of the bus interface so that the data packet is sent to a preset address of a receiving chip through the memory access path;
the device comprises an acquisition unit, a processing unit and a control unit, wherein the acquisition unit is used for acquiring a data packet from a preset address of a chip;
the unpacking unit is used for unpacking the data packet according to a preset unpacking rule so as to obtain a register access request sent by the receiving chip;
and the sending unit is used for sending the acquired register access request to the register.
5. The apparatus of claim 3, wherein: and the routing module sends the register access request to a corresponding register through a register bus.
6. The apparatus of claim 5, wherein: the register bus is an AXI bus protocol.
7. A server cluster interconnected by multiple chips comprises a plurality of nodes interconnected by bus interfaces, a physical link of each bus interface comprises a memory access path for transmitting data information, and at least one path is arranged between any two nodes, and the server cluster is characterized in that: any two of the nodes perform data transmission by the method according to any one of claims 1-3.
8. The server cluster of claim 7, wherein: when at least two paths exist between any two nodes, a memory access path for transmitting data information and a memory access path for transmitting register access information between any two nodes are respectively established on two different paths.
9. An electronic device comprising a processor and a memory, characterized in that: the memory stores executable program code and the processor, when calling the executable program code, performs the method of any of claims 1-2.
10. A computer-readable storage medium storing a computer program, characterized in that: the computer program, when executed by a processor, performs the method of any of claims 1-2.
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| CN117033270B (en) * | 2023-10-08 | 2024-01-26 | 腾讯科技（深圳）有限公司 | Chip, device and data processing method |
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