CN100547572C - Dynamically set up the method and system of direct memory access path - Google Patents
Dynamically set up the method and system of direct memory access path Download PDFInfo
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Abstract
The invention provides a kind of method and system of dynamically setting up the direct memory access path, particularly a kind of method of dynamically setting up the direct memory access path comprises: detecting one direct memory access passage uses request; Dispose a path control register and a path transmission register, to set up a direct memory access passage; Judge whether to send corresponding to the direct memory access transmission requests of this path; If have, then, carry out data transmission according to the parameter of described path control register and described path transmission register; And judge whether described path finishes using, if then discharge the path transmission register and the path control register of described path correspondence.The present invention can dynamically dispose the direct memory access path according to behaviour in service by configuration path control register and path transmission register.
Description
Technical field
The invention relates to direct memory access (Direct memory access, DMA), particularly relevant for a kind of direct memory access system for transmitting of supporting.
Background technology
(Direct memory access is a kind of technology that is directly realized data transmission by hardware DMA) to direct memory access, and does not need the intervention of microprocessor (CPU) in the data transmission procedure.The direct memory access controller is usually located between peripherals and the system bus, and the direct memory access that is used between control peripheral devices and the memory bank transmits.Along with the development of technology, the external unit that computer system connected is more and more, thereby needs to be provided with corresponding access path in the direct memory access controller, to be reached for the purpose of a plurality of peripherals services.
Figure 1 shows that the synoptic diagram of traditional computer system that the transmission of multi-path direct memory access is provided.As shown in the figure, computer system 100 comprises microprocessor 10, memory bank 11, equipment 12 and direct memory access controller 13.Wherein, equipment 12 is made up of a plurality of peripherals.Hypothesis has four peripherals herein, and label is 121,122,123 and 124 respectively.Peripherals 121～124 is connected to dma controller 13 by corresponding D MA request line, with the transmission of the DMA between realization and the memory bank 11 operation.Dma controller 13 comprises one first transmission interface 130, second transmission interface 131, moderator 132, path control 133 and data working storage 136.Path control 133 comprises four path steering logics 1341～1344, and is corresponding with peripherals 121～124 respectively, in order to handle the DMA transmission requests that corresponding peripheral device 121～124 is sent.Be provided with a parameter register group 1351～1354 in each path steering logic 1341～1344, be used to write down every transmission parameter of this path.Data in the parameter register group 1351～1354 were preset by CPU before path uses, and the transmission parameter that it write down comprises information such as the data transfer length, memory address of respective channels.Moderator 132 is used for the DMA transmission requests that priority is the highest and exports path control 133 to.For instance, suppose that peripherals 121 sends a DMA transmission requests to dma controller 13, so that data are write in the memory bank 11.Suppose that this moment priority of the DMA transmission requests sent of peripherals 121 is the highest, then moderator 132 can transfer to path control 133 with this DMA transmission requests, and sends a response signal to peripherals 121.The data that peripherals 121 will need to transmit according to this response signal export second transmission interface 131 of dma controller 13 to.Can carry out the DMA transmission according to the transmission parameter of storing in the parameter register group with peripherals 121 corresponding path steering logics 1341 in the path control 133.Specifically, path steering logic 1341 can be according to transmission parameter, control data storage that second transmission interface 131 will need to transmit in data working storage 136, control first transmission interface 130 then the data in the data working storage 136 are written in the memory bank 11.After finishing the pairing DMA transmission of this DMA transmission requests, path steering logic 1341 also can be according to the transmission parameter in the status update parameter register group of current data storage.
Obviously, in the computer system shown in Figure 1, peripherals and DMA path are one to one, and after system finished configuration, the number of the supported DMA path of dma controller was fixed.Thereby if need to connect new peripherals, also needing in the dma controller increases respective via steering logic and parameter register group, makes the area of dma controller and complex circuit designs degree increase.
Given this, we wish to provide a kind of can be according to the computer system of behaviour in service dynamic-configuration DMA path.
Summary of the invention
The object of the present invention is to provide a kind of can be according to the system of behaviour in service dynamic-configuration DMA path.
The invention provides a kind of support direct memory access system for transmitting, it comprises: a microprocessor; One memory bank has a plurality of path transmission registers by described microprocessor configuration, and described path transmission register is respectively applied for the transmission parameter of the corresponding direct memory access path of storage; An and direct internal storage access controller.The direct memory access controller comprises: a plurality of path control registers, the controlled variable of storing the corresponding direct memory access path that described microprocessor writes respectively; One moderator is used for the controlled variable that the described path control register of foundation is stored, the priority of the direct memory access transmission requests that ruling receives, and export an arbitration result; An and path control, arbitration result according to described moderator, control corresponding direct memory access path and to the corresponding path transmission register of described memory bank, read described path transmission parameter, and carry out data transfer operation according to the path transmission parameter that reads.
The invention provides a kind of method of dynamically setting up the direct memory access path, it comprises: detecting one direct memory access passage uses request; Dispose a path control register and a path transmission register, be respectively applied for controlled variable and the transmission parameter of storage, to set up this direct memory access path corresponding to a direct memory access passage; Judge whether to send corresponding to the direct memory access transmission requests of this this direct memory access path; If have, then carry out data transmission according to the controlled variable of described path control register storage and the transmission parameter of described path transmission register storage; And judge whether described this direct memory access path finishes using, if then discharge the path transmission register and the path control register of described this direct memory access path correspondence.
System of the present invention can dynamically dispose the direct memory access path according to behaviour in service by configuration path control register and path transmission register.
Description of drawings
By the description of carrying out below in conjunction with the accompanying drawing that an example exemplarily is shown, above-mentioned and other purposes of the present invention and characteristics will become apparent, wherein:
Fig. 1 is the synoptic diagram of the computer system of a plurality of direct memory access paths of the support of prior art;
Fig. 2 is for supporting the synoptic diagram of the system of a plurality of direct memory access paths according to an embodiment of the invention;
Fig. 3 is the synoptic diagram according to the system of a plurality of direct memory access paths of the support of further embodiment of this invention;
Fig. 4 is for arbitrating the process flow diagram of the method for direct memory access transmission requests priority according to an embodiment of the invention; And
Fig. 5 is for dynamically setting up the process flow diagram of direct memory access path according to an embodiment of the invention.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below.
Fig. 2 is for supporting direct memory access (Directmemory access, DMA) synoptic diagram of the computer system of path according to an embodiment of the invention.As shown in the figure, the computer system 200 of one embodiment of the invention comprises a microprocessor 1, memory bank 2, equipment 3 and dma controller 4.Equipment 3 is made up of n the peripherals of label 3_1～3_n.Peripherals 3_1～3_n is connected to dma controller 4 by DMA request line L1～Ln respectively, to see through the data transmission between dma controller 4 realizations and the memory bank 2.Dma controller 4 comprises first transmission interface 40, second transmission interface 41, moderator 42, path control 43 and data working storage 44.First transmission interface 40 is provided with the parameter storage unit 400 by microprocessor 1 configuration, in order to each parameter of storage dma controller 4.Further, parameter storage unit 400 comprises overall control register 401 and path control register CCR1～CCRn.Overall situation control register 401 is used to store the configuration parameter of dma controller 4, for example parameter informations such as the base address of the quantity of path, parameter memory block 20, status information, interrupt control.Each path control register CCR1～CCRn is that (double word DW), is used to store the controlled variable of individual channel to 1 double word, for example transmission direction, transmission length information such as (burst length).The priority of the DMA transmission requests that moderator 42 ruling are received, and send a response signal to corresponding peripheral device (for example peripherals 31) and an arbitration result to path control 43.The arbitration result of moderator 42 outputs comprises path (channel_id), transmission data length (data count) and the transmission direction that will carry out the DMA transmission.Path control 43 comprises a function circuit 430 and a general-purpose register 431, is used for carrying out DMA transmission operation according to the arbitration result of moderator 42 outputs.Data working storage 44 is used for temporary data of carrying out the DMA transmission.In present embodiment, before the use path carried out data transmission, microprocessor 1 had disposed a parameter memory block 20 in memory bank 2, and this parameter memory block 20 is made up of the continuous path transmission register CR1～CRn in address.The size of each path transmission register CR1～CRn is 8DW, is used to store the transmission parameter of individual channel, for example information such as descriptor address, address data memory.Hence one can see that, the computer system 200 of present embodiment is the DMA path that peripherals 3_1～3_n has set up n bar correspondence, i.e. CH1～CHn by DMA request line L1～Ln, path control register CCR1～CCRn, path transmission register CR1～CRn, dma controller 43 and data working storage 44.For instance, if peripherals 3_1 need write data in the memory bank 2, can ask line L 1 to send a DMA transmission requests by DMA to dma controller 4.The priority of supposing this DMA transmission requests is the highest, and then moderator 42 can send response signal and give peripherals 3_1, and arbitration result is delivered to path control 43.Peripherals 3_1 exports second transmission interface 41 to according to the data that this response signal will need to transmit, and path control 43 is controlled data storage that second transmission interface 41 will need to transmit in data working storage 44 according to transmission parameter.The function circuit 430 of path control 43 is according to the base address of arbitration result and parameter memory block 20, see through first transmission interface 40 and to memory bank 2, read the path transmission register CR1 corresponding, and the parameter that reads is deposited in the general-purpose register 431 with path CH1.Function circuit 430 is controlled first transmission interface 40 with the destination address of the data transmission in the data working storage 44 to memory bank 2 according to transmission parameter in the general-purpose register 431 and arbitration result subsequently.After finishing a DMA transmission, function circuit 430 also needs according to the parameter information in the current data memory state renewal general-purpose register 431, and the parameter after will upgrading writes among the path transmission register CR1 of memory bank 2.
Need to prove, the number of the peripherals that the number of the actual path of setting up is connected with system in present embodiment not necessarily equates, because have only when peripherals need carry out data transmission in the mode of DMA by dma controller 4, microprocessor 1 just can dispose the respective via transmission register in the parameter memory block 20 of memory bank 2, configuration respective via control register in first transmission interface 40 is to set up and the corresponding path of this peripherals.In other words, the number of the path of system is to come dynamic-configuration according to the virtual condition of peripherals in the present embodiment.For instance, suppose that peripherals 3_n-1 is a printer, but be not activated, thereby microprocessor 1 can't dispose path control register CCRn-1 and path transmission register CRn-1 when configuration dma controller 4.Having only as peripherals 3_n-1 has when carrying out the needing of DMA transmission, and microprocessor 1 just can carry out the configuration of corresponding registers, to set up the path CHn-1 corresponding to peripherals 3_n-1.In fact, present embodiment computer system 200 also can be set up a plurality of DMA paths corresponding to software, the i.e. DMA transmission requests of sending according to software, parameter in configuration path transmission register, path control register and the overall control register 401 is to set up the DMA path corresponding to this software.For example, can in the path register, increase a DMA request discrimination bit and an access port discrimination bit.When DMA request discrimination bit is 1 ' b 1, represent that this DMA transmission requests sent by software.When DMA request discrimination bit was 1 ' b1, the access port discrimination bit was effective, and the DMA transmission requests that this software of its value representation sends by which path is handled.
In addition, be provided in a side of in the memory bank 2 owing to take the path transmission register CR1～CRn of big storage space, thereby computer system 200 can increase the number of supported DMA path under the situation of the area that does not increase dma controller 4.Moreover, as is known to the person skilled in the art, can be provided with the two or more data working storages 44 and the general-purpose register 431 of respective numbers in the dma controller 4, to realize the parallel transmission of a plurality of paths.For example, utilize first transmission interface 40 will be stored in the data in the data working storage when writing the destination address of memory bank 2 at path CH1, the data that path CH2 can utilize second transmission interface 41 that peripherals 3_2 is sent deposit in another data working storage.
Fig. 3 is for supporting the synoptic diagram of the computer system of a plurality of DMA paths according to another embodiment of the present invention.The computer system 300 of present embodiment comprises a microprocessor 1, memory bank 2, equipment 3 and dma controller 4.Equipment 3 is made up of n the peripherals of label 3_1～3_n.Peripherals 3_1～3_n is connected to dma controller 4 by DMA request line L1～Ln respectively, to see through the data transmission between dma controller 4 realizations and the memory bank 2.Microprocessor 1 has disposed a parameter memory block 20 in memory bank 2, this parameter memory block 20 is made up of the continuous path transmission register CR1～CRn in address.The size of each path transmission register CR1～CRn is 8DW, is used to store the transmission parameter of individual channel, for example information such as descriptor address, address data memory.Dma controller 4 comprises first transmission interface 40, second transmission interface 41, moderator 42 ', path control 43 and data working storage 44.First transmission interface 40 is provided with overall control register 401 and path control register CCR1～CCRn.Overall situation control register 401 is used to store the configuration parameter of dma controller 4, for example parameter informations such as the base address of the quantity of path, parameter memory block 20, status information, interrupt control.Each path control register CCR_1～CCR_n is 1DW, is used to store the controlled variable of individual channel, for example transmission direction, transmission length (burst length), priority group number information such as (group_id).Wherein, when the priority group number is the parameters of microprocessor 1 configuration DMA path, the grouping foundation that provides according to the Data Transmission Feature of each peripherals.For instance, suppose that peripherals 3_1 is that portable hard drive, peripherals 3_2 are that video player, peripherals 3_3 are that sound pick-up outfit and peripherals 3_4 are mouse.Obviously, recording and video playback all need time delay of data transmission little, during the copying data of video playback and portable hard drive, all the larger data amount can be arranged, and the data transmission of mouse can have certain time-delay with respect to recording, and data volume is less.Thereby when configuration, peripherals 3_1～3_4 corresponding priorities group number is respectively: 10,01,00,11, and promptly the priority of sound pick-up outfit is the highest, and the priority of mouse is minimum, and the priority of video playback is lower than sound pick-up outfit, but is higher than portable hard drive.
Moderator 42 ' is used for the priority of the received DMA transmission requests of ruling, and send a response signal to corresponding peripheral device (for example peripherals 3_1) and an arbitration result to path control 43.The arbitration result of moderator 42 ' output comprises path (channel_id), transmission data length (datacount) and the transmission direction that will carry out the DMA transmission.In present embodiment, moderator 42 ' comprises task manager 420, task location 423, arbitration unit 424 and timer 425,426.Task location 423 is made up of 4 formations, i.e. Q1～Q4.Wherein, formation Q1 is used for the DMA transmission requests of memory priority level group number for " 00 "; Formation Q2 is used for the DMA transmission requests of memory priority level group number for " 01 "; Formation Q3 is used for the DMA transmission requests of memory priority level group number for " 10 "; Formation Q4 is used for the DMA transmission requests of memory priority level group number for " 11 ".Task manager 420 receives a plurality of DMA transmission requests that peripherals 3_1～3_n sends by transmission requests line L1～Ln, and sends the DMA transmission requests that receives to corresponding formation Q1～Q4 according to the priority group number among respective channels control register CCR_1～CCR_n.Timer 425 is used for the timing of formation Q2 output DMA transmission requests.Timer 426 is used for the timing of formation Q4 output DMA transmission requests.Set in advance by microprocessor 1 time-count cycle of timer 425,426.Arbitration unit 424 comprises arbitration result generation unit 4241, formation control module 4242 and timing control module 4243.In present embodiment, arbitration result generation unit 4241 is according to the timing situation of timer 425 with timer 426, and is the highest according to the priority of which DMA transmission requests in certain top four DMA transmission requests of algorithm ruling dequeue Q1～Q4 (being the longest transmission requests of stand-by period in each formation).Timing control module 4243 is controlled timer 425,426 zero clearings or is continued timing according to the arbitration result of arbitration result generation unit 4241 outputs.4242 of formation control modules by taking out among corresponding formation Q1～Q4, and export path control 43 to according to arbitration result DMA transmission requests that priority is the highest.Especially, as previously mentioned,, thereby can divide several DMA transmission cycles to finish the DMA transmission requests according to transmission length (burst length) because formation 2 need be transmitted lot of data with the DMA transmission requests in the formation 4.For example say, suppose that video player sends a DMA transmission requests reading the 8DW data, and the transmission length corresponding to the path of video player of microprocessor 1 configuration is 4DW.In this case, this DMA transmission requests need divide two DMA transmission cycles to finish, and 4242 of formation control modules can upgrade information such as desired data length of this DMA transmission requests among the formation Q2 according to arbitration result.
Fig. 4 is the process flow diagram of the method for moderator 42 ' ruling DMA transmission requests priority shown in Figure 3.At first, in step S401, receive the DMA transmission requests that peripherals sends.Subsequently, in step S402, the DMA transmission requests that receives is deposited among corresponding queues Q1～Q4 according to the priority group number, with the DMA transmission requests according to the priority packet that sets in advance.Then, in step S403, judge whether timer 426 expires (time out), to avoid the overlong time of the DMA transmission requests wait among the minimum formation Q4 of timer 426 corresponding priorities.If, the top DMA transmission requests priority the highest (step S404) among the ruling formation Q4 then, and make timer 426 beginning reclockings (step S405).Whether if in step S403, timer 426 does not expire, and then execution in step S406 judges whether timer 425 expires, in time handled to determine to require the less but DMA transmission requests among the formation Q2 that data volume is bigger of time delay.If timer 426 expiration, top DMA transmission requests priority the highest (step S407) among the ruling formation Q2 then, and make timer 425 beginning reclockings (step S408).If timer 426 does not expire, promptly timer 425 and all not expirations of timer 426 are then carried out top DMA transmission requests among formation Q1～Q4 in proper order according to the priority group number.Specifically, at first execution in step S409 judges whether formation Q1 is empty.If formation Q1 non-NULL, then top DMA transmission requests priority the highest (step S410) among the ruling formation Q1.If formation Q1 is empty, judge then then whether formation Q2 is empty (step S411), if, top DMA transmission requests priority the highest (step S412) among the ruling formation Q2 then, and make timer 425 reclockings (step S413).If formation Q2 is empty, then enter step S414, judge whether formation Q3 is empty.If formation Q3 non-NULL, then top DMA transmission requests priority the highest (step S415) among the ruling formation Q3.If formation Q3 is empty, judge then whether formation Q4 is empty (step S416).If formation Q4 non-NULL, top DMA transmission requests priority the highest (step S417) among the ruling formation Q4 then, and make timer 426 reclockings (step S4418).If formation Q4 also is empty, promptly all there is not the DMA transmission requests among formation Q1～Q4, then finish priority ruling flow process.
Owing to after receiving the DMA transmission requests, can the DMA transmission requests be divided into four priority groups, and when the priority of arbitration DMA transmission requests, can further adjust priority orders according to the value of timer 425,426 according to the characteristic of peripherals.Thereby the priority arbitration method of the DMA transmission requests of present embodiment can each priority of balance stand-by period of DMA transmission requests, reach the purpose of optimization system performance.In fact, in this example, the DMA transmission requests is done 4 priority groups by branch and is deposited in the corresponding formation, and is provided with two timers that correspond respectively to formation Q2 and Q4 and adjusts priority orders.Yet, as is known to the person skilled in the art, the DMA transmission requests can be divided into according to actual needs and is lower than 4 or more than 4 priority groups, also can be for each formation is provided with a timer, and by adjusting the priority of controlling the DMA transmission requests time-count cycle of timer.
Figure 5 shows that the process flow diagram of dynamically setting up the DMA path according to one embodiment of the invention.
Computer system is after having set up corresponding D MA path according to the peripherals that has started, send the request (step S 501) of using the DMA path if detect new peripherals, then upgrade the path number in the overall control register, and configuration and corresponding path control register of this peripherals and path transmission register, to set up DMA path (step S502) corresponding to this peripherals.Next, this DMA path can be in idle condition (step S503), and judges whether this peripherals sends DMA transmission requests (step S504).If there is not the DMA transmission requests to send, then return step S503, promptly path maintains idle condition.If in step S504, there is the DMA transmission requests to send, then arbitrate the priority (step S505) of DMA transmission requests according to referee method shown in Figure 4.In step S506, when the priority of this DMA transmission requests is the highest, read and the corresponding path transmission register of this DMA transmission requests according to arbitration result.Then, carry out DMA transmission operation (step S507) according to the parameter information that reads.At step S508, judge whether to finish data transmission corresponding to this DMA transmission requests.If finish, then upgrade the parameters value (step S509) of the path transmission register of this path.Then, in step S510, judge whether this path finishes using, judge promptly whether corresponding peripherals also needs to carry out data transmission with the mode of DMA.If do not need, then produce a look-at-me to microprocessor (step S511), make microprocessor discharge (release) resource for the DMA path distribution of this peripherals.If also need to carry out the DMA transmission by this passage, then return step S504, wait pending new DMA transmission requests.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Claims (17)
1. support the direct memory access system for transmitting for one kind, it is characterized in that, comprising:
One microprocessor;
One memory bank has a plurality of path transmission registers by described microprocessor configuration, and described path transmission register is respectively applied for the transmission parameter of the corresponding direct memory access path of storage;
One direct internal storage access controller comprises:
A plurality of path control registers, the controlled variable of storing the corresponding direct memory access path of described microprocessor configuration respectively;
One moderator is used for the controlled variable that the described path control register of foundation is stored, the priority of the direct memory access transmission requests that ruling receives, and export an arbitration result; And
One path control, arbitration result according to described moderator, control corresponding direct memory access path and to the corresponding path transmission register of described memory bank, read described path transmission parameter, and carry out data transfer operation according to the path transmission parameter that reads.
2. support direct memory access system for transmitting according to claim 1 is characterized in that described moderator comprises:
One task manager, the controlled variable according to storing in the pairing path control register of direct memory access transmission requests that receives exports described direct memory access transmission requests to corresponding formation;
The direct memory access transmission requests that described task manager is exported is stored in a plurality of formations; And
One arbitration unit is used for the priority of the top a plurality of direct memory access transmission requests of the described a plurality of formations of ruling, and exports described arbitration result.
3. support direct memory access system for transmitting according to claim 2, it is characterized in that, the controlled variable of storing in described each path control register comprises a priority group number, described task manager exports described direct memory access transmission requests to corresponding formation according to the priority group number of storing in the pairing path control register of described direct memory access transmission requests.
4. support direct memory access system for transmitting according to claim 2 is characterized in that described moderator also comprises a timer, is used to adjust the priority of described direct memory access transmission requests.
5. support direct memory access system for transmitting according to claim 4 is characterized in that described arbitration unit comprises:
One arbitration result generation unit is according to the output of described timer, the priority of top a plurality of direct memory access transmission requests in the described a plurality of formations of ruling;
One timing control module according to the output of described arbitration result generation unit, is controlled the timing operation of described timer; And
One formation control module, according to the output of described arbitration result generation unit, the direct memory access transmission requests that described a plurality of formation medium priorities are the highest is as the arbitration result output of described arbitration unit.
6. support direct memory access system for transmitting according to claim 5, it is characterized in that, described timer is corresponding to a formation in described a plurality of formations, if described timer expiration, the priority of top direct memory access transmission requests is the highest in the described timer corresponding queues of then described arbitration result generation unit ruling.
7. support direct memory access system for transmitting according to claim 6, it is characterized in that, if the priority of the direct memory access transmission requests in the described timer corresponding queues is the highest, then described timing control module makes described timer begin reclocking.
8. support direct memory access system for transmitting according to claim 1 is characterized in that described direct memory access controller also comprises a data working storage, is used for the data of temporary direct memory access transmission.
9. support direct memory access system for transmitting according to claim 1 is characterized in that, the transmission parameter of storing in described each path transmission register comprises descriptor address, address data memory at least.
10. a method of dynamically setting up the direct memory access path is characterized in that, comprising:
Detecting one direct memory access passage uses request;
Dispose a path control register and a path transmission register, be respectively applied for controlled variable and the transmission parameter of storage, to set up this direct memory access path corresponding to a direct memory access passage;
Judge whether to send corresponding to the direct memory access transmission requests of this direct memory access path;
If have, then carry out data transmission according to the controlled variable of described path control register storage and the transmission parameter of described path transmission register storage; And
Judge whether described this direct memory access path finishes using, if then discharge the path transmission register and the path control register of described this direct memory access path correspondence.
11. the method for dynamically setting up the direct memory access path according to claim 10, it is characterized in that also comprising step: after finishing data transmission, upgrade the transmission parameter values of storing in the described path transmission register according to described direct memory access transmission requests.
12. the method for dynamically setting up the direct memory access path according to claim 10, it is characterized in that, also comprise step: before the transmission parameter of storing according to the controlled variable and the described path transmission register of described path control register storage carries out data transmission, arbitrate the priority of described direct memory access transmission requests according to the controlled variable of storing in the described path control register.
13. the method for dynamically setting up the direct memory access path according to claim 12 is characterized in that, the step of arbitrating the priority of described direct memory access transmission requests comprises:
Receive the direct memory access transmission requests;
Deposit described direct memory access transmission requests in corresponding formation according to a priority group number;
According to a timer, the priority of the described direct memory access transmission requests of ruling; Wherein
If described timer does not expire, the priority of the direct memory access transmission requests that then ruling priority group number is the highest is the highest.
14. the method for dynamically setting up the direct memory access path according to claim 13 is characterized in that: described timer is corresponding to the minimum formation of priority group number.
15. the method for dynamically setting up the direct memory access path according to claim 13 is characterized in that, the step of the priority of the described direct memory access transmission requests of ruling also comprises:
Judge whether described timer expires, if then in the described timer corresponding queues of ruling, it is the highest to come top direct memory access transmission requests priority; And
Make described timer begin reclocking.
16. the method for dynamically setting up the direct memory access path according to claim 13 is characterized in that, described priority group number is stored in the path control register.
17. the method for dynamically setting up the direct memory access path according to claim 10 is characterized in that, the transmission parameter of storing in described each path transmission register comprises descriptor address, address data memory at least.
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| US9934185B2 (en) * | 2015-01-12 | 2018-04-03 | Xilinx, Inc. | Processing system network controller with interface to programmable logic |
| CN104536921A (en) * | 2015-01-19 | 2015-04-22 | 浪潮电子信息产业股份有限公司 | Design method for separating type parallel data channels of EDMA controller |
| KR102395541B1 (en) * | 2015-07-09 | 2022-05-11 | 에스케이하이닉스 주식회사 | Memory control unit and data storage device including the same |
| CN106851706B (en) * | 2017-02-23 | 2020-05-15 | 成都米风感知科技有限公司 | Register configuration method based on multichannel communication receiving system |
| CN114647602B (en) * | 2022-05-24 | 2022-08-19 | 沐曦集成电路(上海)有限公司 | Cross-chip access control method, device, equipment and medium |
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|---|---|---|---|---|
| CN1552028A (en) * | 2001-09-07 | 2004-12-01 | ض� | Method and apparatus for distributed direct memory access for systems on chip |
| CN1474568A (en) * | 2002-08-06 | 2004-02-11 | 华为技术有限公司 | Direct internal storage access system and method of multiple path data |
| CN101030183A (en) * | 2007-04-03 | 2007-09-05 | 北京中星微电子有限公司 | Direct memory access controller and method for realizing memory batch processing |
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