CN1474568A - Direct internal storage access system and method of multiple path data - Google Patents
Direct internal storage access system and method of multiple path data Download PDFInfo
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- CN1474568A CN1474568A CNA021287090A CN02128709A CN1474568A CN 1474568 A CN1474568 A CN 1474568A CN A021287090 A CNA021287090 A CN A021287090A CN 02128709 A CN02128709 A CN 02128709A CN 1474568 A CN1474568 A CN 1474568A
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Abstract
This invention relates to a multichannel data direct internal memory access system and a method of a digital information transmission which receives data of every channel discontinuously with a DMA receive module utilizing data structure information of idle array descriptors and finished array descriptors, when numbers of the idle array descriptors are less than a set threshold in FREE-FIFO, a module is controlled from the idle array outside the chip by the bus interface control module according to the internal read-idle array pointer timely regulated. When sending DMA module, the array descriptor and arranged RAM, and the data structure information of the data packet descriptor to be sent is sent by a DMA module to multichannel.
Description
Technical field
The present invention relates to the transmission of digital information, relate in particular to a kind of multi-channel data direct memory access system and method.
Background technology
In the prior art, do not have the method that multi-channel data is directly visited between the outer main memory of chip internal and sheet, produce obstruction for single channel visit lifting for equipment performance in broadband application of adopting data between chip internal and the outer main memory of sheet.
Summary of the invention
The object of the present invention is to provide a kind of multi-channel data direct memory access system and method for realizing that the multichannel discrete date is directly visited between chip internal and the outer main memory of sheet.
The technical solution adopted in the present invention is: this multi-channel data direct memory access system, and it is characterized in that: it comprises direct access process module, this direct access process module comprises and receives dma module and send dma module; In receiving dma module, have FREE_FIFO memory, DONE_FIFO memory and configuration RAM memory, and the control logic that is used for access control, the FREE_FIFO memory is used to deposit idle queues descriptor Free Queue Descriptor, and the DONE_FIFO memory is used to deposit finishes formation descriptor Done Queue Descriptor; In sending dma module, have PENDING_FIFO memory, DONE_FIFO memory and configuration RAM memory, and the control logic that is used for access control, the PENDING_FIFO memory is used to deposit formation descriptor to be sent, and the DONE_FIFO memory is used to deposit and is sent completely the formation descriptor;
Configuration is used to deposit the data fifo memory of idle queues descriptor in the described reception dma module (21).
This multi-channel data direct memory access method that is used for above-mentioned multi-channel data direct memory access system is characterized in that:
When receiving data, the data of each passage are after the normal process of data processing module, and the bag data are sent to the reception dma module; The position of bag data description main memory sheet outside of information that receives the idle data buffer area address in the outer main memory of sheet that dma module provides according to idle queues descriptor Free QueueDescriptor and be used for describing this buffer area at last deposits data in sheet main memory outward through bus interface module by the sheet external bus; When sending data, the data of bag chain to be sent are passed through bus interface module through the sheet external bus, be sent completely the formation descriptor in the generation of transmission dma module, CPU will need the data that send to write in the bag data description subqueue to be sent and formation to be sent in the outer main memory of sheet by the form of bag descriptor to be sent and formation descriptor to be sent, upgrade the pointer that sends the formation descriptor to be sent in the dma module, send the information of dma module according to formation descriptor to be sent and bag data description to be sent, revise the information of bag data description to be sent and configuration RAM, bag data catena to be sent with CPU will send reaches corresponding passage from data processing module;
The data structure of described bag data description comprises:
Data Buffer Address: the initial address of data buffer area;
Next Descriptor Pointer: the sub-pointer of bag data description of the next data buffer area of packet;
Length: the data length of this data buffer area;
Buffer Status: the metadata cache zone state, in order to represent the data of filling out in this data buffer area be this packet beginning partly or mid portion, perhaps decline;
Channel: which passage channel number, data belong to;
Described reception dma module is used to complete after formation descriptor Done Queue Descriptor reflection receives dma module data are filled out the idle data buffer area, the information that CPU need use when handling fills out the complete or non-complete packet in the main memory; The configuration RAM memory that receives in the dma module is pressed the passage piecemeal, is used for depositing the reception dma module and is receiving the various information such as relevant bag data description that each channel data process produces according to control logic from data processing module; Receive dma module when data packet length surpasses the capacity of a data buffer area,, a plurality of data buffer area are linked deposit a complete packet by wrapping data description and the information of finishing the formation descriptor; Receive dma module by interrupting telling CPU to have data to handle, CPU is by finishing receiving the sub-pointer of bag data description of first data buffer zone in the formation descriptor, find bag data description of first data buffer area, find first data buffer area according to wherein data buffer area start address, after handling the data of first data buffer area, find bag data description of second data buffer area according to the information in bag data description of first data buffer area ... the rest may be inferred, until this packet or data to be processed are all disposed.
Described transmission dma module receives the information of CPU, notify a bag chain to be sent of certain passage, send dma module and deposit formation descriptor to be sent, formation descriptor to be sent reflects which passage bag data description and this bag chain to be sent of first data buffer area correspondence of bag chain to be sent belong to, and formation descriptor correspondence to be sent is waited data description of giving out a contract for a project accordingly; By bus interface module, generation is sent completely the formation descriptor to the data of bag chain to be sent according to corresponding control logic by sending the DM module, is stored in the inner DONE_FIFO memory through the sheet external bus; CPU will need the data that send to write in the bag data description subqueue to be sent and formation to be sent in the outer main memory of sheet by the form of bag descriptor to be sent and formation descriptor to be sent, upgrade the pointer that sends the formation descriptor to be sent in the dma module, send dma module and read formation descriptor to be sent; Send the information of dma module according to formation descriptor to be sent and bag data description to be sent, revise the information of bag data description to be sent and configuration RAM, the bag data catena to be sent that CPU will be sent, bag data according to passage under the bag data to be sent send situation, producing correct state information is placed among the configuration RAM, the request of the bag of response data module application simultaneously data reaches corresponding passage from data processing module.
Described data processing module is when sending the data of certain passage of dma module application, send channel number sense data processing module from configuration RAM memory that dma module brings according to data processing module and want the information of the passage applied for, from main memory, read and wait data description of giving out a contract for a project accordingly, give data processing module, the remaining data amount of the current data of successively decreasing buffering area according to the data buffer zone sense data of information from main memory wherein.
If described data processing module does not also wait and sends dma module and will the data of current data buffer zone of reading all read and give data processing module just because inside is former thereby stop to receive data, requirement stops current transmission, send dma module and stop, current read data buffer address being write in the corresponding information of this channel part of configuration RAM memory from the data buffer area read data; The pending data processing module is when it has the ability to receive the data of this passage, to the data that send this passage of dma module application, send the information that dma module is read this passage from configuration RAM memory, find to the data buffer zone read data give data processing module, the remaining data amount of the data buffer zone of successively decreasing.
In the described reception dma module, finish formation descriptor Done Queue Descriptor and mainly comprise: packet that needs are handled or data belong to data complete packet whether of the sub-pointer of the pairing bag data description of first buffer area, the needs processing of the shared several data buffer area of packet that packet that passage, needs handle or data have accounted for several data buffer area, needs processing or data; Its data structure comprises:
Descriptor Pointer: or point to the pointer that packet wraps bag data description of first shared data buffer area of data;
Channel: which passage is data belong to;
Buffers: packet that waiting for CPU is handled or data occupancy several data buffer area;
Packet Status: the bag data mode is recorded in the type that makes a mistake in the receiving course;
EOF: the end-of-packet symbol, represent that a packet finishes;
In receiving dma module, configuration RAM memory press the passage piecemeal, be used for depositing reception DAM and receiving some average informations that each channel data process produces from data processing module, and CPU is to the configuration information of each passage, and its data structure comprises:
Current Data Buufer Address: the data buffer area current address writes by receiving dma module (21);
Current Descriptor Pointer: the sub-pointer of bag data description of current data buffer area writes by receiving dma module (21);
Start Descriptor Pointer:CPU wants the sub-pointer of bag data description of first data buffer area of deal with data, writes by receiving dma module;
Threshold: control reception dma module generates one and finishes receiving the formation descriptor after having filled out several data buffer area, write by CPU;
Data Number: the data volume of data buffer area writes zero setting during the CPU initialization by receiving dma module;
Threshold Count: the real data buffer area number that current data packet is shared writes zero setting during the CPU initialization by receiving dma module;
Buffer Size: the size of this channel data buffer area is write by CPU;
Receive dma module when data packet length surpasses the capacity of a data buffer area,, a plurality of data buffer area are linked deposit a complete packet by Next Descriptor Pointer and EOF position;
Configuration data FIFO memory in the described reception dma module, when the idle queues descriptor number in the FREE_FIFO memory is less than the thresholding of certain setting, read the idle queues pointer by bus interface control module idle queues the main memory outside sheet according to what its inside was adjusted in real time: deposit the buffer area of idle queues descriptor, read abundant idle queues descriptor the FREE_FIFO memory is filled up; Receive dma module and receive data processing module to the request that receives dma module, from data processing module reception data fill out data fifo memory on one side, from configuration RAM memory, the information of this passage is read simultaneously.
Beneficial effect of the present invention is: in the present invention, in receiving dma module, has the FREE_FIFO memory, DONE_FIFO memory and configuration RAM memory, and the control logic that is used for access control, the FREE_FIFO memory is used to deposit the idle queues descriptor, the DONE_FIFO memory is used to deposit finishes the formation descriptor, utilize the idle queues descriptor, finish the formation descriptor, configuration RAM, data structure information such as bag data description, receive the data that dma module receives each passage discontinuously with one, configuration data FIFO memory in receiving dma module, when the idle queues descriptor number in the FREE_FIFO memory is less than the thresholding of certain setting, read the idle queues pointer by bus interface control module idle queues the main memory outside sheet according to what its inside was adjusted in real time, to read abundant idle queues descriptor the FREEFIFO memory is filled up, receive dma module and receive data processing module to the request that receives dma module, receiving data from data processing module on one side fills out the data fifo memory, from configuration RAM memory, the information of this passage is read simultaneously, can speed up processing; In sending dma module, has the PENDING_FIFO memory, DONE_FIFO memory and configuration RAM memory, and the control logic that is used for access control, the PENDING_FIFO memory is used to deposit formation descriptor to be sent, the DONE_FIFO memory is used to deposit and is sent completely the formation descriptor, utilize formation descriptor to be sent, be sent completely the formation descriptor, configuration RAM, the data structure information of data description of waiting to give out a contract for a project sends dma module with one and sends multi-channel data discontinuously, when chip internal carries out discrete date outside by sheet external bus and sheet between the main memory when transmitting, with the continuous data of each passage tram the main memory and notify CPU to deal with outside chip internal is write sheet, can stop current ongoing data-moving as required at any time, the continuous data of each passage in main memory correctly sent to each passage; The present invention can be economical, intelligence, the discrete date of multi-channel data is moved between process chip inside and the outer main memory of sheet efficiently, realizes outside chip internal and the sheet that the multichannel discrete date is directly visited between the main memory.
Description of drawings
Fig. 1 is a general structure schematic diagram of the present invention;
Fig. 2 is for receiving the dma module structural representation;
Fig. 3 is for receiving configuration RAM memory data structural representation in the dma module;
Fig. 4 is for receiving the handling process schematic diagram;
Fig. 5 is the schematic diagram that concerns that finishes receiving between formation descriptor, bag data description, the data buffer area;
Fig. 6 is for sending the dma module structural representation;
Fig. 7 is the example schematic diagram that formation descriptor to be sent points to a packet to be sent of passage;
Fig. 8 is the example schematic diagram that formation descriptor to be sent points to two packets to be sent of passage;
Fig. 9 is for sending configuration RAM memory data structural representation in the dma module;
Figure 10 is for sending dma module catena schematic flow sheet;
Figure 11 is for sending dma module catena structural representation;
Figure 12 sends the data flow schematic diagram for sending dma module.
Embodiment
With embodiment the present invention is described in further detail with reference to the accompanying drawings below:
According to Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11 and Figure 12:
In the present invention, as Fig. 1, Fig. 2 and shown in Figure 6, directly the access process module comprises reception dma module 21 and sends dma module 22; In receiving dma module 21, have FREE_FIFO memory, DONE_FIFO memory and configuration RAM memory, and the control logic that is used for access control, the FREE_FIFO memory is used to deposit idle queues descriptor Free QueueDescriptor, and the DONE_FIFO memory is used to deposit finishes the formation descriptor;
In sending dma module 22, have PENDING_FIFO memory, DONE_FIFO memory and configuration RAM memory, and the control logic that is used for access control, the PENDING_FIFO memory is used to deposit formation descriptor to be sent, and the DONE_FIFO memory is used to deposit and is sent completely the formation descriptor;
As depicted in figs. 1 and 2, the data of each passage are after the normal process of data processing module 1, and the bag data are sent to and received dma module 21; The position of bag data description main memory sheet outside of information that receives the idle data buffer area address in the outer main memory of sheet that dma module 21 provides according to idle queues descriptor FreeQueue Descriptor and be used for describing this buffer area at last deposits data in sheet main memory outward through bus interface module 3 by the sheet external bus; The data structure of idle queues descriptor FreeQueue Descriptor is as shown in table 1:
| ??Free??Data??Buffer?Address | ????Free?Packet?Descriptor?Pointer |
Table 1 is wherein:
Free Data Buffer Address: the initial address of idle data buffer area in the outer main memory of sheet;
Free Packet Descriptor Pointer: bag data description sub-pointer, point to the position of bag data description of the information that is used for describing this data buffer area at main memory.
As shown in table 2, the data structure of bag data description comprises:
Data Buffer Address: the initial address of data buffer area;
Next Descriptor Pointer: the sub-pointer of bag data description of the next data buffer area of packet;
Length: the data length of this data buffer area;
Buffer Status: the metadata cache zone state, in order to represent the data of filling out in this data buffer area be this packet beginning partly or mid portion, perhaps decline;
Wherein: first data buffer area of 000 representative data bag;
The intermediate data buffer area of 010 representative data bag;
Last data buffer area of 100 representative data bags;
Channel: which passage channel number, data belong to;
| ????Data?Buffer?Address |
| ?Channel | ????Buffer??Status | ????Length | ????Next??Descriptor ????Pointer |
Table 2
Receive dma module 21 and be used to complete formation descriptor Done Queue Descriptor reflection reception dma module 21 after data being filled out one or more idle data buffer areas, after perhaps a packet all being filled out the idle data buffer area of the outer main memory of sheet, the information that CPU need use when handling fills out the complete or non-complete packet in the main memory;
As shown in table 3, in receiving dma module 21, finish formation descriptor Done QueueDescriptor and mainly comprise: packet that needs are handled or data belong to data complete packet whether of the sub-pointer of the pairing bag data description of first buffer area, the needs processing of the shared several data buffer area of packet that packet that passage, needs handle or data have accounted for several data buffer area, needs processing or data; Its data structure comprises:
Descriptor Pointer: or point to the pointer that packet wraps bag data description of first shared data buffer area of data;
Channel: which passage is data belong to;
Buffers: packet that waiting for CPU is handled or data occupancy several data buffer area;
Packet Status: the bag data mode is recorded in the type that makes a mistake in the receiving course;
EOF: the end-of-packet symbol, represent that a packet finishes.
| ????EOF | ????Packet??Status | ????Buffers | ????Channel | ??Descriptor??Pointer |
Table 3
The configuration RAM feram memory that receives in the dma module 21 is pressed the passage piecemeal, be used for depositing and receive dma module 21 in the various information such as relevant bag data description that produce according to control logic from data processing module 1 each channel data process of reception, the information of utilization bag data description subrecord data buffer area and CPU know processed data when handling information;
As shown in Figure 3, in receiving dma module 21, configuration RAM memory is pressed the passage piecemeal, is used for depositing receiving DAM in some average informations that produce from data processing module 1 each channel data process of reception, and CPU is to the configuration information of each passage, and its data structure comprises:
Current Data Buufer Address: the data buffer area current address writes by receiving dma module 21;
Current Descriptor Pointer: the sub-pointer of bag data description of current data buffer area writes by receiving dma module 21;
Start Descriptor Pointer:CPU wants bag data description of first data buffer area of deal with data, writes by receiving dma module 21;
Threshold: control reception dma module 21 generates one and finishes receiving the formation descriptor after having filled out several data buffer area, write by CPU;
Data Number: the data volume of data buffer area writes zero setting during the CPU initialization by receiving dma module 21;
Threshold Count: the real data buffer area number that current data packet is shared writes zero setting during the CPU initialization by receiving dma module 21;
Buffer Size: the size of this channel data buffer area is write by CPU;
Receive dma module 21 when data packet length surpasses the capacity of a data buffer area,, a plurality of data buffer area are linked deposit a complete packet by wrapping data description and the information of finishing the formation descriptor; Receive dma module 21 when data packet length surpasses the capacity of a data buffer area,, a plurality of data buffer area are linked deposit a complete packet by Next Descriptor Pointer and EOF position; Receive configuration data FIFO memory in the dma module 21, when the idle queues descriptor number in the FREE_FIFO memory is less than the thresholding of certain setting, read the idle queues pointer by bus interface control module idle queues the main memory outside sheet according to what its inside was adjusted in real time: deposit the buffer area of idle queues descriptor, read abundant idle queues descriptor FREE_FIFO is filled up; Receive dma module 21 and receive data processing module 1 to the request that receives dma module 21, from data processing module 1 reception data fill out data fifo memory on one side, from configuration RAM memory, the information of this passage is read simultaneously.
According to Fig. 1, Fig. 2, as shown in Figure 4 and Figure 5, if Threshold Count and Data Number in the configuration RAM memory are " 0 ", expression has just begun to receive the data of deserving prepass, or receive dma module 21 just receives this passage up to now after the data of notifying CPU to handle the reception in the past of this passage data, data need be filled out a new data buffer zone, receive dma module 21 and read an idle queues descriptor from the FREE_FIFO memory, to wrap data according to idle data buffer area address Free Data Buffer Address wherein and insert data buffer area, data volume in the while incremental data buffering area, adjust the address of write data buffer area in real time, upgrade the Current Descriptor of configuration RAM memory simultaneously with the sub-pointer of the bag data description of bag data description that points to this data buffer zone;
If the data deficiencies that receives from data processing module 1 is to fill up a data buffer area, or also do not receive a complete packet, receive dma module 21 when data fifo memory is sky, end is filled out the operation of data by bus interface module 3 to the data buffer zone, upgrades Data Number in the configuration RAM memory with the current data amount in this data buffer area, upgrade the Current Data BufferAddress that disposes in the RAM memory with the write data buffer zone address, several data buffer area that this packet has taken in the outer main memory of sheet are at present upgraded the Threshold Count that disposes in the RAM memory;
Receive dma module 21 when data processing module 1 receives the data of this passage once more, find that Data Number or Threshold Count in the configuration RAM memory are not " 0 ", then the data buffer area of not filling up last time is inserted with data in the address of and then filling out last time by interface control module according to the Current Data Buffer Address in the configuration RAM memory, increases progressively actual amount of data, the adjustment write data buffer area address filled out in this data buffer area;
Receiving dma module 21 is filling in the data procedures to data buffer area, find that the data volume of having filled out data buffer area has reached the Buffer Size that disposes in the RAM memory, the maximum cacheable data volumes in data buffer zone that CPU is provided with for this passage, judge and filled up a data buffering area, the data buffer area that this packet is taken adds one, simultaneously according to finding that this packet does not finish the data that receive from data processing module 1, then a new idle queues descriptor of reading from the FREE_FIFO memory finds next idle data buffer area, write the Next Descriptor Pointer territory that disposes in bag data description that Current DescriptorPointer points in the RAM memory with the sub-pointer of bag data description in the new idle queues descriptor then, initial address with the current data buffer area that is filled, passage under the data, the data volume of this data buffer zone, the state of this data buffer zone in current data packet, first data buffer zone in several data buffer zones that this packet data takies, one of the centre of several data buffer area that this packet data takies, last data buffer zone of several data buffer zones that this packet data takies, write the corresponding field of bag data description, upgrade the CurrentDescriptor Pointer that disposes in the RAM memory with the Free Packet Descriptor Pointer in the idle queues descriptor of newly reading:
If find that current data packet is all completed or filled up the current data buffering area, and the data buffer zone number that current this packet takies has reached Threshold value in the configuration RAM memory, be that predefined what the data buffering areas of filling out of CPU generate one and finish the formation descriptor, then with passage under current data packet or the data, Threshold Count in the configuration RAM memory, it is the data buffer area number that packet or data have taken at present, Start Descriptor Pointer in the configuration RAM memory, it is the sub-pointer of the pairing bag data description of first buffer area of the shared several data buffer area of packet or data, the end-of-packet symbol, promptly the data that need to handle in order to expression are a complete packet or a part of data of packet, write the DONE_FIFO memory as finishing the formation descriptor, with Threshold Count and the Data Number zero clearing in the configuration RAM memory;
Receive dma module 21 in the DONE_FIFO memory, had some finish receiving the formation descriptor time, finish queue pointer according to writing of adjusting in real time of its inside the formation descriptor that finishes receiving in the DONE_FIFO memory is write the formation that finishes receiving in the main memory in order: deposit the spatial cache that finishes receiving the formation descriptor, and, this packet or data to be processed are all disposed by interrupting telling CPU to have data to handle.
Like this, receive dma module 21 by interrupting telling CPU to have data to handle, CPU is by finishing receiving the sub-pointer of bag data description of first data buffer zone in the formation descriptor, find bag data description of first data buffer area, find first data buffer area according to wherein data buffer area start address, after handling the data of first data buffer area, find bag data description of second data buffer area according to the information in bag data description of first data buffer area, find second data buffer area according to data buffer area start address in bag data description again, handle bag data description that finds the 3rd data buffering area behind second data buffer area again according to the information in bag data description of second data buffering area ... the rest may be inferred, until this packet or data to be processed are all disposed;
According to Fig. 1, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11 and shown in Figure 12, in sending dma module 22, the CPU notice sends a bag chain to be sent of dma module 22 certain passage, send dma module 22 and deposit formation descriptor to be sent, formation descriptor to be sent reflects which passage bag data description and this bag chain to be sent of first data buffer area correspondence of bag chain to be sent belong to, and formation descriptor correspondence to be sent is waited data description of giving out a contract for a project accordingly;
As shown in table 4, formation descriptor data structure to be sent:
| ????Channel | ????Descriptor?Pointer |
Table 4
Wherein:
Descriptor Pointer: the descriptor pointer, point to bag data description of first data buffer area correspondence of bag chain to be sent.
Channel: channel number shows which passage bag chain to be sent belongs to.
In sending dma module 22, the data structure of data description of waiting to give out a contract for a project is as shown in table 5:
| ????Data?Buffer??Address | ||||
| ??EOF | ??CV | ??Length | ????Next??Descriptor??Pointer | |
| ??PV | ?Channel | ????Next??Pending??Descriptor??Pointer | ||
Table 5
Wherein: Data Buffer Address: data buffer area initial address to be sent is write by CPU;
Next Descriptor Poitner: next bag data description to be sent, point to bag data description of the next data buffer area to be sent of this packet to be sent when " 0 " at EOF.When EOF and CV are " 1 ", point to next packet to be sent bag data description of first data buffer area to be sent, write by CPU;
Length: data length, the data volume of data buffer area to be sent is write by CPU;
CV: chain effectively identifies (Chain Valid), and this position acts on when introducing Next DescriptorPointer and introduced, and is write by CPU;
EOF: frame end is represented (End Of Frame), for the current pending data buffer area of " 1 " expression has been last data buffer area to be sent of this packet to be sent, is write by CPU;
Next Pengding Descriptor Pointer: effective when PV is " 1 ", send dma module 22 inside and only deposit two bag chains to be sent, if certain passage has a plurality of bag chains to be sent, send dma module 22 by writing this territory, and put PV for " 1 ", a plurality of bag chains to be sent are stringed together, then in the transmission data procedures, by reading the pointer in PV and this territory, all data in the bag chain to be sent of a passage are correctly sent.
Channel: channel number is write by CPU;
PV: next queue pointer to be sent effectively identifies Pending Descriptor Valid, and is effective for " 1 " expression Next Pending Descriptor Pointer, writes by sending dma module 22;
The data structure of formation descriptor to be sent comprises:
Descriptor Pointer: the descriptor pointer, point to bag data description of first data buffer area correspondence of bag chain to be sent.
Channel: channel number shows which passage bag chain to be sent belongs to.
The data of bag chain to be sent are passed through bus interface module 3 through the sheet external bus, be sent to data processing module 1 by sending dma module 22 according to corresponding control logic, be sent completely the formation descriptor in 22 generations of transmission dma module, be stored in the inner DONE_FIFO memory, the number of queues that is sent completely in the DONE_FIFO memory surpasses on it in limited time, the formation that is sent completely of writing automatically in the outer main memory of sheet is interrupted to CPU with Times, and this is sent completely formation descriptor record and sends the information that dma module 22 writes down in the data that distribute a data buffer zone to be sent or complete process data packet to be sent; For example: whole packet by the data of first data buffer zone to be sent of complete transmission, packet to be sent be sent out, the data of certain data buffer area to be sent of centre of packet to be sent are sent out, the data of last data buffer zone to be sent of packet to be sent are sent out, if wrong generation, then misregistration phenomenon or reason in sending data procedures.
As shown in table 6, the data structure that is sent completely the formation descriptor is as follows:
| ??EOF | ??Stauts | ??Channel | ????Descriptor??Pointer |
Table 6
Wherein:
Descriptor Pointer: the sub-pointer of bag data description, be used in reference to bag data description, or point to bag data description of the buffer area to be sent that is sent out away to first data buffer area to be sent of the bag to be sent that is sent out away.
Channel: channel number, be sent out data and belong to which passage, write by sending dma module 22;
Status: state, essential record are sent out the position of data in bag to be sent, and are recorded in the error situation that sends in the data procedures.
EOF: frame end sign, End Of Frame.
In sending dma module 22, configuration RAM memory press the passage piecemeal, deposits to send dma module 22 and need the average information used and the CPU configuration information to this passage in the data procedures sending to wrap; As shown in Figure 9, its data structure comprises:
Current Data Buffer Address: the current address of data buffer zone to be sent, write by sending dma module 22, CPU is read-only;
DQS: if be " 0 ", send 22 of dma modules and just write later on and finish the formation descriptor having sent a packet, if be " 1 ", transmission dma module 22 is write after the data that distribute a data buffer area to be sent and is finished the formation descriptor; Write by CPU;
Length Left: the remaining data amount of current data buffer area to be sent writes by sending dma module 22; Zero setting during the CPU initialization;
EOF: the same with the EOF in bag data description of current data buffer area to be sent, write zero setting during the CPU initialization by sending dma module 22;
CV: the same with the CV in bag data description of current data buffer area to be sent, write zero setting during the CPU initialization by sending dma module 22;
PENDST: be used for representing to dispose the state of RAM memory Next Dscriptor, Next PendingDescriptor, write by sending dma module 22, zero setting during the CPU initialization, as follows:
PENDST??Next?Descriptor?Pointer??Next?Pending?Descriptor?Pointer
000 is invalid
100 is invalid
101 effectively
111 effectively
Wherein being up to of PENDST " 0 " represented the data that this passage does not have it at present and can send, for " 1 " expression has.
Next Descriptor Pointer: the sub-pointer of bag data description of next data buffer area to be sent
Start Descriptor Pointer: the sub-pointer of bag data description of first of current packet to be sent data buffer area to be sent.
Next Pending Descriptor Pointer: the sub-pointer of bag data description of first data buffer area to be sent of next bag chain to be sent.
Last Pending Descriptor Pointer: the sub-pointer of bag data description of first data buffer area to be sent of last bag chain to be sent.
CPU will need the data that send to write in the bag data description subqueue to be sent and formation to be sent in the outer main memory of sheet by the form of bag descriptor to be sent and formation descriptor to be sent, upgrade the pointer that sends the formation descriptor to be sent in the dma module 22, send dma module 22 and read formation descriptor to be sent; Send the information of dma module 22 according to formation descriptor to be sent and bag data description to be sent, revise the information of bag data description to be sent and configuration RAM, the bag data catena to be sent that CPU will be sent, bag data according to passage under the bag data to be sent send situation, producing correct state information is placed among the configuration RAM, the request of the bag of response data module application simultaneously data reaches corresponding passage from data processing module 1;
In sending dma module 22, as shown in figure 10, the detailed process of catena data is:
1, when PENDING_FIFO memory non-NULL, from the PENDING_FIFO memory, reads formation descriptor to be sent, find that PENDST is " 3 ' b000 " if cease according to the letter worker of this passage of reading from configuration RAM memory this moment, represent the packet chain that current this passage will not send, then write the Start Descriptor territory of configuration RAM memory with the sub-pointer of bag data description in the formation descriptor to be sent, and to revise PENDST be 3 ' b100, represents that this passage has a bag chain to be sent.
2, if and then from the PENDING_FIFO memory, read the formation descriptor to be sent of this passage once more, this moment is according to finding that PENDST is " 3 ' b100 " by passage from the information that configuration RAM memory is read, represent that this passage has a bag chain to be sent, then the sub-pointer of bag data description in the formation descriptor of reading for the second time to be sent is write Next Pending Descriptor Pointer and the LastPending Descriptor Pointer territory of this passage in configuration RAM memory, and to put PENDST be 3 ' b101, represents that this passage has had two bag chains to be sent at least.
3, if the formation descriptor of and then reading from the PENDING_FIFO memory to be sent still belongs to this passage, then according to the PENDST value of this passage of from configuration RAM memory, reading, find that it is " 3 ' b101 ", represent that this passage has two bag chains to be sent at present at least, this moment is except upgrading the Last Pending Descriptor Pointer in this channel arrangement RAM memory with the transmit queue descriptor of reading specifically, and it is write Next Pending Descriptor Pointer territory in this passage bag data description that Next Pending Descriptor Pointer points in configuration RAM memory, will wrap the PV set in data description simultaneously.
If 4 these passages also have a plurality of bag chains to be sent, be embodied in the formation descriptor a plurality of to be sent of in the PENDING_FIFO memory, reading this passage, send dma module 22 if according to shown in top 3 like that, just that this passage is all transmission bag chains have been gone here and there.
5, send dma module 22 by top step 1, step 2, step 3, the described operation of step 4, the current all bag chains to be sent of each port are pressed the port string together, as shown in figure 11, the catena structure of video data.
When data processing module 1 when sending the data of dma module 22 certain passage of application, send channel number sense data processing module 1 from configuration RAM memory that dma module 22 brings according to data processing module 1 and want the information of the passage applied for, from main memory, read and wait data description of giving out a contract for a project accordingly, give data processing module 1, the remaining data amount of the current data of successively decreasing buffering area according to the data buffer zone sense data of information from main memory wherein;
If data processing module 1 does not also wait and sends dma module 22 and will the data of current data buffer zone of reading all read and give data processing module 1 just because inside is former thereby stop to receive data, requirement stops current transmission, send dma module 22 and stop, current read data buffer address being write in the corresponding information of this channel part of configuration RAM memory from the data buffer area read data; Pending data processing module 1 is when it has the ability to receive the data of this passage, to the data that send dma module 22 these passages of application, send the information that dma module 22 is read this passage from configuration RAM memory, find to the data buffer zone read data give data processing module 1, the remaining data amount of the data buffer zone of successively decreasing.
As shown in figure 12, when data processing module 1 when sending the data of dma module 22 certain passage of application:
If 1 PENDST is " 3 ' b000 ", represent that this passage does not have bag chain to be sent at present, send dma module 22 to 1 end data transmission signals of data processing module, represent current this end of transmission;
2, if the highest order of PENDST " 1 ", the value that is PENDST is " 3 ' b1xx ", the value of low two of PENDST is not considered in expression, and the Length Left that reads from configuration RAM memory is " 0 ", expression did not also send the data of this passage at present, then from main memory, read bag data description that Start Descriptor Pointer points to according to the value of the Start Descriptor Pointer of this passage in configuration RAM memory, according to Data Buffer Address wherein, data buffer zone sense data from main memory is given data processing module 1, the remaining data amount of the current data of successively decreasing buffering area, if simultaneously the EOF in bag data description that points to of Start Descriptor Pointer is that " 0 " or EOF and CV are " 1 ", then the Next Descriptor Pointer in bag data description that Start DescriptorPointer is pointed to writes the Next Descriptor Pointer territory of this passage in configuration RAM memory, with highest order among the PENDST and time high-order set, represent that the Next Descriptor Pointer in this channel arrangement RAM memory is effective simultaneously;
If 3 data processing modules 1 also do not wait and send dma module 22 and will the data of current data buffer zone of reading all read and give data processing module 1 just because inside is former thereby stop to receive data, requirement stops current transmission, sending dma module 22 stops from the data buffer area read data, the Current Data Buffer Address that disposes this channel part of RAM memory is write in current read data buffer address, data buffer zone remaining data amount is write the Length Left territory of this channel part of configuration RAM memory.
4, data processing module 1 is when it has the ability to receive the data of this passage, to the data that send dma module 22 these passages of application, send the information that dma module 22 is read this passage from configuration RAM memory, find that Length Left territory is not " 0 ", expression does not also send the data of a data buffering area, according to the Current Data Buffer Address in the configuration RAM memory to the data buffer zone read data give data processing module 1, the remaining data amount of the data buffer zone of successively decreasing.
5, send dma module 22 and all give data processing module 1 data of data buffer zone after, the remaining data amount of data buffer zone is " 0 ", see whether the inferior high position among the PENDST that disposes this passage in the RAM memory is " 1 ", if be " 1 ", send dma module 22 and read corresponding bag data description from main memory according to the Next Descriptor Pointer in the configuration RAM memory:
If the EOF in a bag data description is that " 0 " or EOF and CV are " 1 ", upgrade the Next Descriptor Pointer that disposes in the RAM memory with the Next Descripotor Pointer in bag data description, put the highest order of the PENDST in the configuration RAM memory and time high-order be " 1 ", 3 ' b11X represents that this packet chain to be sent is made up of the data of two data buffering areas at least;
If the EOF in b bag data description is that " 1 " and CV are " 0 ", a time high position of putting in the configuration RAM memory is " 0 ", and 3 ' b10X represents that this data buffer zone is the data of last data buffer zone of packet chain to be sent;
If c data processing module 1 this moment can continue to receive the data of this passage, send dma module 22 and give data processing module 1 by the data buffer zone read data of interface control module from outside main memory, the remaining data amount in the data buffer zone of successively decreasing according to the Data Buffer Address in bag data description;
If d data processing module 1 this moment can not continue to receive the data of this passage, require to finish this transmission, the Data Buffer Address in transmission dma module 22 usefulness bag data description upgrades the CurrentData Buffer Address in the configuration RAM memory; Length in bag data description upgrades the value of the Length Left in the configuration RAM memory, can continue when like this, by the time data processing module is applied for this channel data 1 next time again data to be sent are read from the data buffer zone and give data processing module 1;
6, send dma module 22 after packet chain to be sent distributes with one, that is: the remaining data amount of this data buffer zone is zero; And this moment, time high position of PENDST was " 0 ", if the lowest order among the PENDST is " 1 ", represent that the Next Pending Descriptor Pointer territory in this channel arrangement RAM memory is effective, the Next Pending Descriptor Pointer that sends in the dma module 22 usefulness configuration RAM memory upgrades the value that disposes Start Descriptor in the RAM memory, like this, if this moment, data processing module 1 requirement stopped this data transfer, also can intactly give data processing module 1 when data processing module is applied for this channel data 1 next time more by the time, from main memory, read bag data description that Next PendingDescripotr Pointer points to the data to be sent of this passage:
If the PV in a bag data description is " 1 ", with the Next Pending Descriptor Pointer in the Next Pending Descriptor Pointer replacement configuration RAM memory in bag data description, and will dispose PENDST highest order and lowest order set in the RAM memory, 3 ' b1X1 represents that current this passage has at least data of two bag chains to be sent etc. to be sent;
If the PV in b bag data description is " 0 ", the PENDST lowest order of putting in the configuration RAM memory is " 0 ", and 3 ' b1X0 represents that current this transmission bag chain is last bag chain to be sent of this passage;
If the EOF in c bag data description is that " 0 " or EOF and CV are " 1 ", upgrade the Next Descriptor Pointer that disposes in the RAM memory with the Next Descripotor Pointer in bag data description, put the highest order of the PENDST in the configuration RAM memory and time high-order be " 1 ", 3 ' b11X represents that this packet chain to be sent is made up of the data of two data buffering areas at least;
If the EOF in d bag data description is that " 1 " and CV are " 0 ", a time high position of putting in the configuration RAM memory is " 0 ", and 3 ' b10X represents that this data buffer zone is the data of last data buffer zone of packet chain to be sent;
7, send dma module 22 and equally give data processing module 1 the pairing data of other bag chains to be sent of this passage by top step 2 to the ground of description shown in the step 6, after sending dma module 22 data of the corresponding data buffer zone of last bag data description give data processing module 1 in last packet chain of this passage, find PENDST time high-order and minimum for all being " 0 " in the configuration RAM memory, data that do not have bag chain to be sent of representing this passage etc. are to be sent, then will dispose the PENDST zero clearing in the RAM memory, the data of representing all bag chains to be sent of this passage all have been sent out and have finished, and will dispose the Length Left zero clearing in the RAM memory;
8, sending dma module 22 gives data processing module 1 processing according to top step 1 to the data to be sent with each passage shown in the step 7, after having sent the data of a data buffering area to data processing module 1, the DQS value that is provided with according to CPU in the configuration RAM memory judges whether that needs generate one and finish the formation descriptor;
If the value of 9 DQS is " 1 ", send dma module 22 usefulness and point to the sub-pointer of bag data description of bag data description of this data buffer area, and one of the state that writes down in the data procedures that sends data buffer zone generation is sent completely the formation descriptor and writes in the DONE_FIFO memory;
If the value of 10 DQS is " 0 ", Start Descriptor Pointer in the transmission dma module 22 usefulness configuration RAM memory and one of the state generation of writing down in the data procedures that sends the data buffer zone are sent completely the formation descriptor and write the DONE_FIFO memory;
11, send dma module 22 in the DONE_FIFO memory, had some be sent completely the formation descriptor time, be sent completely queue pointer according to writing of adjusting in real time of its inside the formation descriptor that is sent completely in the DONE_FIFO memory is write the formation that is sent completely in the main memory in order: deposit the spatial cache that is sent completely the formation descriptor, which data of each passage of notice CPU have been sent out.
Claims (10)
1. multi-channel data direct memory access system is characterized in that:
It comprises direct access process module, and this direct access process module comprises reception dma module (21) and sends dma module (22);
In receiving dma module (21), have FREE FIFO memory, DONE_FIFO memory and configuration RAM memory, and the control logic that is used for access control, the FREE_FIFO memory is used to deposit idle queues descriptor (Free QueueDescriptor), and the DONE_FIFO memory is used to deposit finishes formation descriptor (DoneQueue Descriptor);
In sending dma module (22), have PENDING_FIFO memory, DONE_FIFO memory and configuration RAM memory, and the control logic that is used for access control, the PENDING_FIFO memory is used to deposit formation descriptor to be sent, and the DONE_FIFO memory is used to deposit and is sent completely the formation descriptor.
2. multi-channel data direct memory access according to claim 1 system is characterized in that: configuration is used to deposit the data fifo memory of idle queues descriptor in the described reception dma module (21).
3. multi-channel data direct memory access method that is used for the described multi-channel data direct memory access of claim 1 system is characterized in that:
When receiving data, the data of each passage are after the normal process of data processing module (1), and the bag data are sent to and received dma module (21); The position of bag data description main memory sheet outside of information that receives the idle data buffer area address in the outer main memory of sheet that dma module (21) provides according to idle queues descriptor (Free Queue Descriptor) and be used for describing this buffer area at last deposits data in sheet main memory outward through bus interface module (3) by the sheet external bus;
When sending data, the data of bag chain to be sent are passed through bus interface module (3) through the sheet external bus, be sent completely the formation descriptor in transmission dma module (22) generation, CPU will need the data that send to write in the bag data description subqueue to be sent and formation to be sent in the outer main memory of sheet by the form of bag descriptor to be sent and formation descriptor to be sent, upgrade the pointer that sends the formation descriptor to be sent in the dma module (22), send the information of dma module (22) according to formation descriptor to be sent and bag data description to be sent, revise the information of bag data description to be sent and configuration RAM, bag data catena to be sent with CPU will send reaches corresponding passage from data processing module (1).
4. multi-channel data direct memory access method according to claim 3 is characterized in that:
The data structure of described bag data description comprises:
Data Buffer Address: the initial address of data buffer area;
Next Descriptor Pointer: the sub-pointer of bag data description of the next data buffer area of packet;
Length: the data length of this data buffer area;
Buffer Status: the metadata cache zone state, in order to represent the data of filling out in this data buffer area be this packet beginning partly or mid portion, perhaps decline;
Channel: which passage channel number, data belong to;
5. multi-channel data direct memory access method according to claim 3 is characterized in that:
1) described reception dma module (21) is used to complete after formation descriptor (Done QueueDescriptor) reflection receives dma module (21) data are filled out the idle data buffer area, the information that CPU need use when handling fills out the complete or non-complete packet in the main memory;
2) the configuration RAM memory that receives in the dma module (21) is pressed the passage piecemeal, is used for depositing reception dma module (21) and is receiving the various information such as relevant bag data description that each channel data process produces according to control logic from data processing module (1);
3) receive dma module (21) when data packet length surpasses the capacity of a data buffer area,, a plurality of data buffer area are linked deposit a complete packet by wrapping data description and the information of finishing the formation descriptor;
4) receive dma module (21) by interrupting telling CPU to have data to handle, CPU is by finishing receiving the sub-pointer of bag data description of first data buffer zone in the formation descriptor, find bag data description of first data buffer area, find first data buffer area according to wherein data buffer area start address, after handling the data of first data buffer area, find bag data description of second data buffer area according to the information in bag data description of first data buffer area ... the rest may be inferred, until this packet or data to be processed are all disposed.
6. multi-channel data direct memory access method according to claim 3 is characterized in that:
1) described transmission dma module (22) receives the information of CPU, notify a bag chain to be sent of certain passage, send dma module (22) and deposit formation descriptor to be sent, formation descriptor to be sent reflects which passage bag data description and this bag chain to be sent of first data buffer area correspondence of bag chain to be sent belong to, and formation descriptor correspondence to be sent is waited data description of giving out a contract for a project accordingly;
2) by bus interface module (3), generation is sent completely the formation descriptor to the data of bag chain to be sent according to corresponding control logic by sending dma module (22), is stored in the inner DONE_FIFO memory through the sheet external bus;
3) CPU will need the data that send to write in the bag data description subqueue to be sent and formation to be sent in the outer main memory of sheet by the form of bag descriptor to be sent and formation descriptor to be sent, upgrade the pointer that sends the formation descriptor to be sent in the dma module (22), send dma module (22) and read formation descriptor to be sent; Send the information of dma module (22) according to formation descriptor to be sent and bag data description to be sent, revise the information of bag data description to be sent and configuration RAM, the bag data catena to be sent that CPU will be sent, bag data according to passage under the bag data to be sent send situation, producing correct state information is placed among the configuration RAM, the request of the bag of response data module application simultaneously data reaches corresponding passage from data processing module (1).
7. multi-channel data direct memory access method according to claim 6, it is characterized in that: when described data processing module (1) is applied for the data of certain passage to transmission dma module (22), send channel number sense data processing module (1) from configuration RAM memory that dma module (22) brings according to data processing module (1) and want the information of the passage applied for, from main memory, read and wait data description of giving out a contract for a project accordingly, give data processing module (1), the remaining data amount of the current data of successively decreasing buffering area according to the data buffer zone sense data of information from main memory wherein.
8. multi-channel data direct memory access method according to claim 7, it is characterized in that: described data processing module (1) if also do not wait sends dma module (22) and will the data of current data buffer zone of reading all reads and give data processing module (1) just because inside is former thereby stop to receive data, requirement stops current transmission, send dma module (22) and stop, current read data buffer address being write in the corresponding information of this channel part of configuration RAM memory from the data buffer area read data; Pending data processing module (1) is when it has the ability to receive the data of this passage, to sending the data that dma module (22) is applied for this passage, send the information that dma module (22) is read this passage from configuration RAM memory, find to give the remaining data amount of data processing module (1), the data buffer zone of successively decreasing to the data buffer zone read data.
9. multi-channel data direct memory access method according to claim 5 is characterized in that:
1), in the described reception dma module (21), finish formation descriptor (Done QueueDescriptor) and mainly comprise: packet that needs are handled or data belong to data complete packet whether of the sub-pointer of the pairing bag data description of first buffer area, the needs processing of the shared several data buffer area of packet that packet that passage, needs handle or data have accounted for several data buffer area, needs processing or data; Its data structure comprises:
Descriptor Pointer: or point to the pointer that packet wraps bag data description of first shared data buffer area of data;
Channel: which passage is data belong to;
Buffers: packet that waiting for CPU is handled or data occupancy several data buffer area;
Packet Status: the bag data mode is recorded in the type that makes a mistake in the receiving course;
EOF: the end-of-packet symbol, represent that a packet finishes;
2), in receiving dma module (21), configuration RAM memory is pressed the passage piecemeal, be used for depositing and receive DAM and receiving some average informations that each channel data process produces from data processing module (1), and CPU is to the configuration information of each passage, its data structure comprises:
Current Data Buufer Address: the data buffer area current address writes by receiving dma module (21);
Current Descriptor Pointer: the sub-pointer of bag data description of current data buffer area writes by receiving dma module (21);
Start Descriptor Pointer:CPU wants the sub-pointer of bag data description of first data buffer area of deal with data, writes by receiving dma module (21);
Threshold: control reception dma module (21) generates one and finishes receiving the formation descriptor after having filled out several data buffer area, write by CPU;
Data Number: the data volume of data buffer area writes zero setting during the CPU initialization by receiving dma module (21);
Threshold Count: the real data buffer area number that current data packet is shared; , write zero setting during the CPU initialization by receiving dma module (21);
Buffer Size: the size of this channel data buffer area is write by CPU;
3), receive dma module (21) when data packet length surpasses the capacity of a data buffer area, by Next Descriptor Pointer and EOF position, a plurality of data buffer area are linked deposit a complete packet.
10. according to claim 3 or 5 or 9 described multi-channel data direct memory access methods, it is characterized in that: configuration data FIFO memory in the described reception dma module (21), when the idle queues descriptor number in the FREE_FIFO memory is less than the thresholding of certain setting, read the idle queues pointer by bus interface control module idle queues the main memory outside sheet according to what its inside was adjusted in real time: deposit the buffer area of idle queues descriptor, read abundant idle queues descriptor the FREE_FIFO memory is filled up; Receive dma module (21) and receive data processing module (1) to the request that receives dma module (21), from data processing module (1) reception data fill out data fifo memory on one side, from configuration RAM memory, the information of this passage is read simultaneously.
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| CN100394723C (en) * | 2006-08-14 | 2008-06-11 | 江苏中科龙梦科技有限公司 | Double reception FIFO method based on Ethernet receiving controller |
| CN100428670C (en) * | 2006-12-01 | 2008-10-22 | 清华大学 | User-level communication method for stream media server |
| CN100547572C (en) * | 2007-10-22 | 2009-10-07 | 威盛电子股份有限公司 | Dynamically set up the method and system of direct memory access path |
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| CN102822808A (en) * | 2010-02-05 | 2012-12-12 | 诺基亚公司 | Channel controller for multi-channel cache |
| CN103064807A (en) * | 2012-12-17 | 2013-04-24 | 福建星网锐捷网络有限公司 | Multi-channel direct memory access controller |
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