CN110134630A - A kind of transmission cache controller design method of multiple input single output - Google Patents
A kind of transmission cache controller design method of multiple input single output Download PDFInfo
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- CN110134630A CN110134630A CN201910446393.1A CN201910446393A CN110134630A CN 110134630 A CN110134630 A CN 110134630A CN 201910446393 A CN201910446393 A CN 201910446393A CN 110134630 A CN110134630 A CN 110134630A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
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Abstract
The present invention relates to a kind of transmission cache controller design methods of multiple input single output, and FPGA software external interface time flow control data bag transmission in current signal processor is changed to packet parameter control data bag and is sent.This method can effectively simplify FPGA software interface data flow and send design, especially suitable for needing the signal processing system of frequent switching data flow transmission rate.
Description
Technical field
The invention belongs to signal processing technology fields, are related to a kind of transmission cache controller design side of multiple input single output
Method.This method can be used in the design of FPGA external interface, and internal data source rate is greater than under conditions of external interface, realize hair
Sending end rate control.Especially suitable for large-scale the Digital Phased Array antenna system, mass data transmission and variable rate transmission are needed
Occasion.
Background technique
Progress mass data transmission is usually required in massive phased array antenna system to summarize.FPGA is handled in some cases
The instantaneous data rate that device is externally sent can be greater than interface data rate, it is necessary to which then caching to the advanced row of data could send.?
Signal processor front end works in different modes in some cases, and the data transfer rate externally sent is needed with variation.At these
Not only it needs to send buffering reduction of speed, but also in the signal processing system for needing transmission rate variable, generally passes through time stream process at present
Thinking, control parameter needs change over time, control send data rate, data flow inside FPGA temporally beat carry out
Pattern switching.When system both of which processing time difference is different larger, control parameter is changed over time, and software design is more multiple
It is miscellaneous.For this purpose, then the present invention is pressed the complete data elder generation composition data packet of FPGA inter-process using the thinking of Data Stream Processing
Packet parameter is sent.This method can effectively simplify FPGA Software Interface Design, versatile.Especially suitable for large-scale phase
The signal processor system application of a variety of transmission rate switchings is needed in control array antenna system.
Summary of the invention
Technical problems to be solved
In order to avoid in place of the deficiencies in the prior art: FPGA internal data rate is greater than interface data rate, and needs variable Rate
It sends, the present invention proposes a kind of transmission cache controller design method of multiple input single output.
Technical solution
A kind of transmission cache controller design method of multiple input single output, it is characterised in that steps are as follows:
Step 1: sending cache controller includes sending buffer area, write-in control logic, reading three parts of control logic；
It wherein sends buffer area and sends data for caching, include N number of piecemeal, each piecemeal can store a complete data packet, data
Bao Zhongying includes to send length and transmission rate information；Control logic is written to be used to receiving M port into the N number of transmission of data write-in
Buffer area piecemeal；Control logic is read for reading data from the piecemeal of N number of transmission buffer area；
Step 2: 5 global variables of design: port idle state Ks, port free time variable Kn, reception pointer variable R p, hair
Pointer variable Tp, variable blocked Rn to be sent are sent, sends buffer state for describing；
Port idle state Ks value range { 0,1 }, for describing whether currently transmitted caching is sending data；Initially
Change or reading control logic runs through a data packet and sets 1 state, otherwise reads control logic starting one data packet of reading and set 0 shape
State；
Port free time variable Kn value range [0, Knm], for describing when sending caching idle state time, Knm is indicated
Maximum value；
Reception pointer variable R p value range [0, N-1], the buffer area piecemeal position for describing currently to prepare reception data
It sets；Initialization or Kn==Knm-1 moment, Rp setting 0；Otherwise whenever receiving effective data packets, Rp adds 1 by mould of N；
It sends pointer variable Tp value range [0, N-1], the buffer area piecemeal position for describing currently to be ready for sending data
It sets, initialization or Kn==Knm-1 moment, Tp setting 0；Otherwise whenever having sent a data packet, then Tp adds 1 by mould of N；
Variable blocked Rn value range [0, N+1] to be sent, for describing there is Rn piecemeal to need to send out in current buffer
It send, initialization or Kn==Knm-1 moment, Rn setting 0；Otherwise buffer area then Rn+1 is reached when certain moment only has data；It is no
Then then Rn-1 is distributed from buffer area when certain moment only has data；
Step 3: write-in control logic design is as follows, determines input port quantity M as needed, it is desirable that M < N；Whenever having one
It is effective that a port receives data packet, then according to current reception pointer variable R p, writes the data packet the Rp buffer area piecemeal；
Step 4: transmission Buffer Design is as follows, and sending buffer area includes N number of piecemeal；Each piecemeal is by a dual port RAM
Composition, one of port are written for data, another port is read for data；
Step 5: reading control logic design is as follows, setting data packet transmission spacing parameter Kni, Kni value range (0,
Knm-2)；If Rn > 0&&Kn > Kni&&Ks==1, is first distinguished from buffering and read data packet length and transmission rate in block Tp
Information, and according to data packet length and transmission rate information, complete data packet is read, output port is sent to.
Beneficial effect
A kind of transmission cache controller design method of multiple input single output proposed by the present invention,
Using packet parameter control rate transmission rate and length, current sending module is controlled from time flow control and is changed to
Data flow control.
The present invention compared with prior art, has a characteristic that
1. simplifying the design of transmitting terminal rate control.
2. versatile.
Detailed description of the invention
Fig. 1 function composition of the present invention
The port Fig. 2 free time variable Kn more new technological process
Specific embodiment
Now in conjunction with embodiment, attached drawing, the invention will be further described:
Referring to Fig. 1, sends cache controller and specifically include that transmission buffer area, write-in control logic, read control logic three
A part.It wherein sends buffer area and sends data for caching, include N number of piecemeal, each piecemeal can store a partial data
It wraps, it should be comprising sending length and transmission rate information in data packet.Control logic is written to be used to receiving M port into data write-in
N number of transmission buffer area piecemeal.Control logic is read for reading data from the piecemeal of N number of transmission buffer area.
It designs 5 global variables: port idle state Ks, port free time variable Kn, reception pointer variable R p, sending pointer
Variable Tp, variable blocked Rn to be sent send buffer state for describing.
Port idle state Ks value range { 0,1 }, for describing whether currently transmitted caching is sending data.Initially
Change or reading control logic runs through a data packet and sets 1 state, otherwise reads control logic starting one data packet of reading and set 0 shape
State.
Port free time variable Kn value range [0, Knm], for describing when sending caching idle state time, Knm is indicated
Maximum value.Port free time variable Kn more new technological process such as Fig. 2.
Reception pointer variable R p value range [0, N-1], the buffer area piecemeal position for describing currently to prepare reception data
It sets.Initialization or Kn==Knm-1 moment, Rp setting 0；Otherwise whenever receiving effective data packets, Rp adds 1 by mould of N.
It sends pointer variable Tp value range [0, N-1], the buffer area piecemeal position for describing currently to be ready for sending data
It sets, initialization or Kn==Knm-1 moment, Tp setting 0；Otherwise whenever having sent a data packet, then Tp adds 1 by mould of N.
Variable blocked Rn value range [0, N+1] to be sent, for describing there is Rn piecemeal to need to send out in current buffer
It send, initialization or Kn==Knm-1 moment, Rn setting 0；Otherwise buffer area then Rn+1 is reached when certain moment only has data；It is no
Then then Rn-1 is distributed from buffer area when certain moment only has data.
It is as follows that control logic design is written, determines input port quantity M as needed, it is desirable that M < N.Whenever there is a port
It is effective to receive data packet, then according to current reception pointer variable R p, writes the data packet the Rp buffer area piecemeal.
It is as follows to send Buffer Design, sending buffer area includes N number of piecemeal.Each piecemeal is by a simple dual port RAM group
At one of port is written for data, another port is read for data.
It is as follows to read control logic design, setting data packet sends spacing parameter Kni, Kni value range (0, Knm-2).
If Rn > 0&&Kn > Kni&&Ks==1, is first distinguished from buffering and read data packet length and transmission rate information in block Tp, and
According to data packet length and transmission rate information, complete data packet is read, output port is sent to.
The features of the present invention:
With M data flow input port and a data flow output port.Wherein sending buffer area has N number of piecemeal,
N number of transmission data packet can be stored.
Data, which are sent, to be needed to be sent according to port idle state log-on data, and caching output number can be sent according to parameter setting
Interval is sent according to packet.
It can be controlled according to data pack protocol and send caching output data packet transmission length and transmission rate, realize transmitting terminal speed
Rate control.
Claims (1)
1. a kind of transmission cache controller design method of multiple input single output, it is characterised in that steps are as follows:
Step 1: sending cache controller includes sending buffer area, write-in control logic, reading three parts of control logic；Wherein
It sends buffer area and sends data for caching, include N number of piecemeal, each piecemeal can store a complete data packet, in data packet
It should be comprising sending length and transmission rate information；Control logic is written and is used to receive M port the N number of transmission buffering of data write-in
Distinguish block；Control logic is read for reading data from the piecemeal of N number of transmission buffer area；
Step 2: 5 global variables of design: port idle state Ks, port free time variable Kn, reception pointer variable R p, transmission refer to
Needle variable Tp, variable blocked Rn to be sent send buffer state for describing；
Port idle state Ks value range { 0,1 }, for describing whether currently transmitted caching is sending data；Initialization or
Person's reading control logic runs through a data packet and sets 1 state, otherwise reads control logic starting one data packet of reading and sets 0 state；
Port free time variable Kn value range [0, Knm], for describing when sending caching idle state time, Knm indicates maximum
Value；
Reception pointer variable R p value range [0, N-1], the buffer area piecemeal position for describing currently to prepare reception data；Just
Beginningization or Kn==Knm-1 moment, Rp setting 0；Otherwise whenever receiving effective data packets, Rp adds 1 by mould of N；
It sends pointer variable Tp value range [0, N-1], the buffer area piecemeal position for describing currently to be ready for sending data, just
Beginningization or Kn==Knm-1 moment, Tp setting 0；Otherwise whenever having sent a data packet, then Tp adds 1 by mould of N；
Variable blocked Rn value range [0, N+1] to be sent, for describing there is Rn piecemeal to need to send in current buffer, just
Beginningization or Kn==Knm-1 moment, Rn setting 0；Otherwise buffer area then Rn+1 is reached when certain moment only has data；Otherwise when certain
Moment only has data and distributes then Rn-1 from buffer area；
Step 3: write-in control logic design is as follows, determines input port quantity M as needed, it is desirable that M < N；Whenever there is an end
It is effective that mouth receives data packet, then according to current reception pointer variable R p, writes the data packet the Rp buffer area piecemeal；
Step 4: transmission Buffer Design is as follows, and sending buffer area includes N number of piecemeal；Each piecemeal is made of a dual port RAM,
One of port is written for data, another port is read for data；
Step 5: reading control logic and design as follows, setting data packet transmission spacing parameter Kni, Kni value range (0, Knm-
2)；If Rn > 0&&Kn > Kni&&Ks==1, is first distinguished from buffering and read data packet length and transmission rate letter in block Tp
Breath, and according to data packet length and transmission rate information, complete data packet is read, output port is sent to.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112953683A (en) * | 2021-03-04 | 2021-06-11 | 西安电子工程研究所 | Adaptive rate SRIO interface data transmission method |
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