CN106970842A - A kind of dynamic reconfigurable real time signal processing load balance system - Google Patents
A kind of dynamic reconfigurable real time signal processing load balance system Download PDFInfo
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- CN106970842A CN106970842A CN201710190942.4A CN201710190942A CN106970842A CN 106970842 A CN106970842 A CN 106970842A CN 201710190942 A CN201710190942 A CN 201710190942A CN 106970842 A CN106970842 A CN 106970842A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
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Abstract
It is that rear end polycaryon processor array distributes calculating data in real time the present invention relates to the A/D real-time sampling data streams that a kind of dynamic reconfigurable real time signal processing load balance system, receiving front-end are sent.The system includes reconfigurable control module, receives and parsing reconstruct configuration information, control busy；Data cache module, corresponding data FIFO is cached to by control table with ad data according to the configuration information；Data transmission blocks, calculate first address, the purpose ID of each sendaisle, and control table and ad data are transferred into correct receiving terminal according to SRIO agreements according to the purpose ID；Arbitration modules are sent, the multiple data transmitting channels of data transmission blocks are arbitrated and exported.It is embodied as the real-time dynamically distributes of rear end polycaryon processor array and calculates data, and supports a variety of data to merge under modes, and a variety of wave numbers data function such as storage in order in end memory is received.
Description
Technical field
The invention belongs to signal processing system field, it is related to a kind of dynamic reconfigurable real time signal processing load balance system
System.
Background technology
As signal processing system working environment becomes increasingly complex, its functional requirement also becomes more diversified therewith.Cause
This, One function is easy to the signal processing method of reconstruct, and to meeting, different functional requirements is significant.With traditional reality
When digital signal processing appts compare, FPGA has the advantages that small volume, speed are fast, and its dynamic reconfigurable characteristic being capable of basis
Need to change functions of modules in real time, to adapt to varying environment, improve the flexibility of system.
The content of the invention
Present invention aims at Real-time Reconstruction control is carried out, there is provided a kind of dynamic reconfigurable real time signal processing load balance
System, is specifically realized by following technical scheme：
The dynamic reconfigurable real time signal processing load balance system, the A/D real-time sampling datas that receiving front-end is sent
Stream, is that rear end polycaryon processor array distributes calculating data in real time, including
Reconfigurable control module, is received and parsing reconstruct configuration information, control busy, and complete system reconfiguration and distribution in real time
Data purpose ID；
Data cache module, data FIFO is cached to by control table and ad data according to the configuration information；
Data transmission blocks, calculate first address, the purpose ID of each sendaisle, according to the purpose ID by control table with
Ad data are transferred to correct receiving terminal according to SRIO agreements, and according to control table, ad data, Yi Jibo in end memory is received
Number sequential storage；
Arbitration modules are sent, the multiple data transmitting channels of data transmission blocks are arbitrated and exported.
The further design of the dynamic reconfigurable real time signal processing load balance system is, the configuration information bag
Include processing number of clusters, No. ID of SRIO mesh, wave number, the first location of purpose, data volume and collocation channel number.
The further design of the dynamic reconfigurable real time signal processing load balance system is, reconfigurable control module control
Busy processed is by the way of poll adds busy.
The further design of the dynamic reconfigurable real time signal processing load balance system is, the data buffer storage mould
Block is cached the collocation channel number of the ad data in configuration information.
The further design of the dynamic reconfigurable real time signal processing load balance system is that data cache module is common
Including 36 data buffer storage FIFO, wherein fifo0~fifo3 be control table FIFO, fifo4~fifo11, fifo12~
Fifo19, fifo20~fifo27, fifo28~fifo35 are that 4 groups of ad data FIFO, 4 groups of ad data FIFO will be per frame numbers
According to dividing and cache according to wave number.
The further design of the dynamic reconfigurable real time signal processing load balance system is that the data send mould
Root tuber is according to the first location of the purpose, collocation channel number and data volume, for every road SRIO groups bag distribution first address, and according to described
No. ID, busy-idle condition of SRIO mesh, for every road SRIO groups bag distribution purpose ID.
The further design of the dynamic reconfigurable real time signal processing load balance system is, described to send arbitration mould
36 circuit-switched datas are sent and arbitrated by block using 2 grades of crossbar, and are collected for 1 road SRIO outputs.
The further design of the dynamic reconfigurable real time signal processing load balance system is, described to send arbitration mould
36 road AXI data are merged into and sent after 1 road AXI data to 1 SRIO core by block by 3 crossbar.
The further design of the dynamic reconfigurable real time signal processing load balance system is that the data send mould
Between block and transmission arbitration modules timing optimization is realized by inserting 1 grade of AXI FIFO.
Advantages of the present invention is as follows：
The dynamic reconfigurable real time signal processing load balance system that the present invention is provided, rear end can be matched somebody with somebody by sending SRIO
Bag and doorbell are put, dynamic configuration is carried out to the system, configurable part includes：Optical fiber merges mode, first address, purpose ID, ripple
Number and busy-idle condition.It is embodied as the real-time dynamically distributes of rear end polycaryon processor array and calculates data, supports a variety of data merging sides
Under formula, and a variety of wave numbers data receive end memory in order storage etc. function.
Brief description of the drawings
Fig. 1 is the structured flowchart of dynamic reconfigurable real time signal processing load balance system.
Fig. 2 is SRIO group bag state machines.
Fig. 3 is that SRIO sends state machine.
Embodiment
The present invention program is described in detail below in conjunction with the accompanying drawings.
The dynamic reconfigurable real time signal processing load balance system that the present embodiment is provided, the A/D that receiving front-end is sent is real
When sampled data stream, be that rear end polycaryon processor array distributes calculating data in real time.As shown in figure 1, the dynamic of this implementation can be weighed
Structure real time signal processing load balance system includes reconfigurable control module, data cache module, data transmission blocks and transmission
Arbitration modules.Wherein, reconfigurable control module, is responsible for receiving and parsing reconstruct configuration information, control busy, and complete system in real time
Reconstruct and distribution data purpose ID.Data cache module, data are cached to by control table and ad data according to the configuration information
FIFO.Data transmission blocks, are responsible for calculating first address, the purpose ID of each sendaisle, according to the purpose ID by control table
Be transferred to correct receiving terminal according to SRIO agreements with ad data, and in end memory is received according to control table, ad data and
Wave number sequential storage.Arbitration modules are sent, the multiple data transmitting channels of data transmission blocks are arbitrated and exported.
Wherein reconfigurable control is divided into reconfigurable configuration information and received and busy control, main to be responsible for according to matching somebody with somebody that rear end is sent
Put bag and idle doorbell, address and ID that whether control data sends and be sent to.Reconfigurable configuration information module receives 256B
SRIO packets, packet information is as shown in table 1.
Table 1
Reconfigurable configuration information module include processing number of clusters, No. ID of 29 groups of SRIO mesh, merging patterns, wave number and first ground
Location.Busy control creates busy-idle map according to processing number of clusters first, and the ID being sent to hereafter is controlled by the way of poll adds busy.Example
Number of clusters is such as handled for 29, it is idle busy-idle condition register to create 29, the first run is all idle before sending, then from the 1st cluster according to
Secondary transmission is to the 29th cluster, and the cluster being transmitted across is set to busy, until SRIO receives doorbell busy clearly, then the cluster is put back into idle condition.
Hereafter from the 1st cluster to the 29th cluster order poll, it is polled to free cluster and sends toward the cluster.
Wherein data cache module includes 36 data buffer storage FIFO altogether, and wherein fifo0~fifo3 is control table FIFO
(writing 256bit, read 64bit)；Fifo4~fifo11, fifo12~fifo19, fifo20~fifo27, fifo28~fifo35
For 4 groups of ad data FIFO (read-write 64bit), mainly it is responsible for divide and caching according to wave number per frame data.Receive every time busy
After the frame_group_start signals that not busy control unit is sent, start to read DDR 256bit data, read according to data length
1 frame data.Preceding 8KB data per frame are control table, while writing 4 control table FIFO.Remainder data is ad data, 256bit
DDR reads data and is divided into the parallel 64bit data in 4 tunnels, and correspondence writes 4 groups of ad data FIFO, and to ad data based on wave number circulation
Number, will be per the corresponding ad data FIFO of road 64bit ad data deposit count value.
Wherein data transmission blocks are divided into address and produced and ID distribution and SRIO group bag two parts, main to be responsible for controlling on 4 tunnels
Tabulation and 32 road ad data are transferred to correct receiving terminal ID according to SRIO agreements, and in end memory is received according to control table,
Ad data, and wave number sequential storage.Sending module is reconstructed in real time to realize, the corresponding data of every optical fiber send first address
And ID distribution is as shown in table 2.
Table 2
Wherein ID0~ID3 is sent to the unit by busy control unit when frame_group_start signals arrive,
This 4 ID are corresponded to distribute to 4 control table FIFO, and 4 groups of ad data FIFO respectively.Merge mode not according to 4 fiber datas
Together, corresponding first address is distributed, wherein addr_ini is that first address, the tab_len reconstructed in control information table is that control table is long
Degree, ad_len are ad data lengths, and the address listed in table 2 is respectively allocated to 4 tunnel control tables and the 1st, 9,17,25 road ad numbers
According to.2nd~8,10~16,18~24,26~32 tunnel address computation methods are：addr_ch0+ad_len/beam、addr_ch0+
Ad_len/beam*2 ... addr_ch0+ad_len/beam*7, wherein addr_ch0 are the 1st, 9,17,25 road first address,
Beam is the wave number that control table is parsed.SRIO groups packet portion example has changed 36 group bag modules, and each group bag module needs to provide
The first location of data volume, wave number, purpose, purpose ID, doorbell information etc., are responsible for that NW bags will be sent according to SRIO agreements per frame data and tie
Shu Menling.Send state machine as shown in Figure 2,3.Frame head, data, the order of doorbell is first according to be stored in data to be sent
FIFO, as shown in Figure 2；Data are divided into parcel, insertion frame head and doorbell by SRIO host-host protocols again, as shown in Figure 3.
Arbitration modules are wherein sent mainly to be responsible for 36 road AXI data are merged into 1 road AXI data being sent to 1 SRIO core.
Using 2 grades, totally 3 crossbar complete this function.As shown in figure 1, wherein between data transmission blocks and transmission arbitration modules
It is for Improving Working Timing to insert 1 grade of AXI FIFO.
The dynamic reconfigurable real time signal processing load balance system that the present embodiment is provided, rear end can be by sending SRIO
Configuration bag and doorbell, dynamic configuration is carried out to the system.Configurable part includes：Optical fiber merge mode, first address, purpose ID,
Wave number and busy-idle condition, are embodied as the real-time dynamically distributes of rear end polycaryon processor array and calculate data, support a variety of data to merge
Under mode, and a variety of wave numbers data receive end memory in order storage etc. function.
Detailed Jie has been carried out to a kind of dynamic reconfigurable real time signal processing load balance system that the present invention is provided above
Continue, in order to understand the present invention and its core concept., in the specific implementation, can basis for those of ordinary skill in the art
The core concept of the present invention carries out a variety of modifications and deduction.In summary, this specification is not construed as limitation of the present invention.
Claims (9)
1. a kind of dynamic reconfigurable real time signal processing load balance system, the A/D real-time sampling data streams that receiving front-end is sent,
Calculating data are distributed in real time for rear end polycaryon processor array, it is characterised in that including
Reconfigurable control module, is received and parsing reconstruct configuration information, control busy, and complete system reconfiguration and distribution data in real time
Purpose ID；
Data cache module, data FIFO is cached to by control table and ad data according to the configuration information；
Data transmission blocks, calculate first address, the purpose ID of each sendaisle, according to the purpose ID by control table and ad numbers
Correct receiving terminal is transferred to according to according to SRIO agreements, and it is suitable according to control table, ad data and wave number in end memory is received
Sequence is stored；
Arbitration modules are sent, the multiple data transmitting channels of data transmission blocks are arbitrated and exported.
2. dynamic reconfigurable real time signal processing load balance system according to claim 1, it is characterised in that described to match somebody with somebody
Confidence breath include handling number of clusters, No. ID of SRIO mesh, wave number order, purpose head locations, data volume and collocation channel number.
3. dynamic reconfigurable real time signal processing load balance system according to claim 1, it is characterised in that reconstruct control
Molding block controls busy by the way of poll adds busy.
4. dynamic reconfigurable real time signal processing load balance system according to claim 2, it is characterised in that the number
The collocation channel number of the ad data in configuration information is cached according to cache module.
5. dynamic reconfigurable real time signal processing load balance system according to claim 4, it is characterised in that data are delayed
Storing module includes 36 data buffer storage FIFO altogether, wherein fifo0 ~ fifo3 be control table FIFO, fifo4 ~ fifo11, fifo12 ~
Fifo19, fifo20 ~ fifo27, fifo28 ~ fifo35 are that 4 groups of ad data FIFO, 4 groups of ad data FIFO will be per frame data
Divide and cache according to wave number.
6. dynamic reconfigurable real time signal processing load balance system according to claim 2, it is characterised in that the number
According to sending module according to the first location of the purpose, collocation channel number and data volume, for every road SRIO groups bag distribution first address, and
According to No. ID of the SRIO mesh, busy-idle condition, for every road SRIO groups bag distribution purpose ID.
7. dynamic reconfigurable real time signal processing load balance system according to claim 1, it is characterised in that the hair
Arbitration modules are sent, 36 circuit-switched datas are sent using 2 grades of crossbar and arbitrated, and are collected for 1 road SRIO outputs.
8. dynamic reconfigurable real time signal processing load balance system according to claim 1, it is characterised in that the hair
Send arbitration modules to merge into 36 road AXI data by 3 crossbar to send after 1 road AXI data to 1 SRIO core.
9. dynamic reconfigurable real time signal processing load balance system according to claim 1, it is characterised in that the number
According to sending module and send arbitration modules between by insert 1 grade of AXI FIFO realize timing optimization.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107577636A (en) * | 2017-09-12 | 2018-01-12 | 天津津航技术物理研究所 | A kind of AXI bus interface datas Transmission system and transmission method based on SOC |
| CN109062684A (en) * | 2018-07-04 | 2018-12-21 | 南京南大光电工程研究院有限公司 | A kind of real-time dynamic self-adapting dynamic load balancing method of release of the hardware of multi-core processor |
| CN110096474A (en) * | 2019-04-28 | 2019-08-06 | 北京超维度计算科技有限公司 | A kind of high-performance elastic computing architecture and method based on Reconfigurable Computation |
| CN113641605A (en) * | 2021-07-16 | 2021-11-12 | 南京大学 | Polling arbiter suitable for asynchronous circuit and method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107577636A (en) * | 2017-09-12 | 2018-01-12 | 天津津航技术物理研究所 | A kind of AXI bus interface datas Transmission system and transmission method based on SOC |
| CN109062684A (en) * | 2018-07-04 | 2018-12-21 | 南京南大光电工程研究院有限公司 | A kind of real-time dynamic self-adapting dynamic load balancing method of release of the hardware of multi-core processor |
| CN110096474A (en) * | 2019-04-28 | 2019-08-06 | 北京超维度计算科技有限公司 | A kind of high-performance elastic computing architecture and method based on Reconfigurable Computation |
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