CN110958189A - Multi-core FPGA network processor - Google Patents
Multi-core FPGA network processor Download PDFInfo
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- CN110958189A CN110958189A CN201911233649.7A CN201911233649A CN110958189A CN 110958189 A CN110958189 A CN 110958189A CN 201911233649 A CN201911233649 A CN 201911233649A CN 110958189 A CN110958189 A CN 110958189A
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- H—ELECTRICITY
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- H04L49/00—Packet switching elements
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- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
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Abstract
The invention discloses a multi-core FPGA network processor, and belongs to the technical field of microelectronics. The FPGA comprises a PS processing system and a PL programmable logic part, wherein the PS processing system is connected with the PL programmable logic part through a PS-PL connection interface part; the PL programmable logic part is used for realizing a network hardware accelerator and finishing data hardware processing, and specifically comprises a scheduling management module, a message analysis and forwarding module, a cache management module, a queue management module and a message modification module. The invention uses the general multi-core network processor to complete the multi-core SOC function design and the performance verification, combines the flexibility of the programmable device with a plurality of high-performance core processors, and can accelerate the design realization.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a multi-core FPGA network processor.
Background
With the rapid development of the internet, the demands for the line speed processing and manageability of network devices are continuously strengthened, and the network devices are required to have rapid service upgrade capability and high-performance processing capability. In the current stage, the network processor adopts a multi-kernel and parallel hardware processing structure to improve the network capacity and realize parallel exchange, and the design mode is advanced.
At present, the integration degree of the network processors on the chip based on the FPGA proposed in many documents is low. For example, chinese patent publication No. CN 110086752 a discloses a hardware platform for processing an FPGA based on a multi-core network, and the platform uses a way of splicing FPGAs, and has a relatively low rate. Chinese patent publication No. CN 108365996 a discloses a network-on-chip simulation platform based on FPGA + ARM architecture, which lacks independence and functions.
Disclosure of Invention
In view of this, an object of the present invention is to provide a multi-core FPGA network processor, which uses a general multi-core network processor to complete multi-core SOC function design and performance verification, and combines the flexibility of a programmable device with a plurality of high-performance core processors, so as to accelerate the design implementation.
In order to achieve the purpose, the invention adopts the following technical scheme:
a multi-core FPGA network processor comprises an MPSoC on-chip multi-core processor FPGA, wherein the FPGA comprises a PS processing system and a PL programmable logic part, the PS processing system and the PL programmable logic part are connected through a PS-PL connection interface part, the PL programmable logic part is also connected with an input/output interface, and the PS processing system runs with a Petaliinux system; the PL programmable logic part is used for realizing a network hardware accelerator and finishing data hardware processing, and specifically comprises the following modules:
the scheduling management module is used for multiplexing the content of the input port cache message into a data bus and then writing the content into a global message cache, realizing packet header separation and simultaneously generating the flow synchronization control of each forwarding engine, coordinating each forwarding engine to analyze the message and acquiring the output interface of the message;
the message analyzing and forwarding module is used for completing message analyzing and forwarding, forwarding service and user-defined protocol messages and simultaneously performing multicast copying on the messages;
the buffer management module is used for discarding the message according to the port, the queue buffer filling state and the discarding strategy configured by the user;
the queue management module is used for establishing a buffer pointer, distributing a buffer for an input message and recovering the buffer after the message is read from the buffer;
the message modification module is used for modifying the content of the message according to the descriptor of the message and reflecting the processing of the message content to the output message;
the input and output interface is used for receiving and transmitting network port data, the Petalinx system of the PS processing system receives an instruction of an upper computer, compiles instruction configuration information, configures the network hardware accelerator through the PS-PL connection interface part, processes the network port data according to a configuration mode by the network hardware accelerator, and interacts data information with the Petalinx system through the PS-PL connection interface part.
Furthermore, the message analyzing and forwarding module adopts a scheduling structure with symmetrical input and output, and realizes parallel forwarding according to needs; when the analysis message forwarding module forwards the message, the message content is not forwarded, only intermediate results of various forwarding processes are transmitted, and the message is scheduled to be output to a port by adopting a distributed message cache array structure.
Further, the FPGA is a ZU19EG chip.
The invention adopts the technical scheme and has the beneficial effects that:
1. the invention adopts a general CPU as an inner core, adds a network processing hardware accelerator suitable for parallel, and carries a Petaliinux operating system, and the whole design completion degree is high.
2. The invention adopts the multi-core processor, assists various hardware acceleration engines, realizes the high-speed interconnection of the CPU core, various hardware acceleration engines and the storage unit by designing the internal resource interconnection network, improves the high-speed network processing capability and has the capability of flexibly increasing various services.
3. The invention designs the high-speed hardware accelerator suitable for parallel, can load the operating system, and has more independent and perfect functions.
Drawings
Fig. 1 is a schematic structural diagram of a multi-core FPGA network processor in the embodiment of the present invention.
FIG. 2 is a schematic diagram of the PL hardware accelerator of FIG. 1.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1 and 2, a multi-core FPGA network processor includes an MPSoC on-chip multi-core processor FPGA, where the FPGA includes a PS processing system and a PL programmable logic part, the PS processing system and the PL programmable logic part are connected through a PS-PL connection interface part, the PL programmable logic part is further connected with an input/output interface, and the PS processing system runs with a Petalinux system; the PL programmable logic part is used for realizing a network hardware accelerator and finishing data hardware processing, and specifically comprises the following modules:
the scheduling management module is used for multiplexing the content of the input port cache message into a data bus and then writing the content into a global message cache, realizing packet header separation and simultaneously generating the flow synchronization control of each forwarding engine, coordinating each forwarding engine to analyze the message and acquiring the output interface of the message;
the message analyzing and forwarding module is used for completing message analyzing and forwarding, forwarding service and user-defined protocol messages and simultaneously performing multicast copying on the messages;
the buffer management module is used for discarding the message according to the port, the queue buffer filling state and the discarding strategy configured by the user;
the queue management module is used for establishing a buffer pointer, distributing a buffer for an input message and recovering the buffer after the message is read from the buffer;
the message modification module is used for modifying the content of the message according to the descriptor of the message and reflecting the processing of the message content to the output message;
the input and output interface is used for receiving and transmitting network port data, the Petalinx system of the PS processing system receives an instruction of an upper computer, compiles instruction configuration information, configures the network hardware accelerator through the PS-PL connection interface part, processes the network port data according to a configuration mode by the network hardware accelerator, and interacts data information with the Petalinx system through the PS-PL connection interface part.
The message analyzing and forwarding module adopts a scheduling structure with symmetrical input and output, and realizes parallel forwarding according to requirements; when the analysis message forwarding module forwards the message, the message content is not forwarded, only intermediate results of various forwarding processes are transmitted, and the message is scheduled to be output to a port by adopting a distributed message cache array structure.
The invention can be realized by adopting a Zynq series MPSoC development board which is a high-performance SOC platform, wherein the Petalinx is an embedded Linux development tool specially aiming at an FPGA SOC development board of Xilinx company, and a Petalinx running environment, a creation project and a cross compiling environment are required to be built at the early stage.
During specific implementation, the peripheral equipment of the PS can be selected according to design requirements, projects are generated, peripheral equipment parameters are determined, a user-defined IP core can be used for the PS-PL interface, and a Gigabit Ethernet controller (GEM) can be used for configuring and generating a corresponding interface for the input and output interfaces.
Specifically, the PS-PL connection interface part is mainly divided into two functional modules, namely register read-write and message read-write. Wherein the content of the first and second substances,
reading and writing a register: the PS part is used as a Master to configure a module in a mode of configuring a register through AXI-lite and interacts with other modules through ports; adjusting data format and transmitting to hardware accelerator module part; when the feedback information is read, the data analysis is fed back to the PS part through the port.
Reading and writing messages: the hardware accelerator module part is used as a Master, the adjustment data format is connected with the PS part through the AXI bus, the write data is directly connected to the PS part, and the data format is required to be adjusted to return the data to the hardware accelerator module part when the data is read. The message writing instruction may have a relatively long duration, and a cache is added to the message reading instruction to prevent the data loss of the message writing instruction, the message reading instruction does not carry data, and the message writing instruction has a short duration and is not cached.
The basic flow of the network hardware accelerator realized by the invention is as follows: the message is stored in the message cache in the chip through the input scheduling processing module, necessary message header information is sent to the analysis forwarding module for processing, the multi-level flow table is searched and processed, then the message is processed and enters the processing module, the message modification module performs necessary modification on the message according to the result of the previous processing, and then the message is sent to the cache, the queue and the scheduling module for processing and finally sent out from the interface. Wherein the content of the first and second substances,
and the scheduling management module inputs messages from the scheduling port, multiplexes the contents of the messages cached at the input port to the data bus when one message is cached, writes the contents into the global message cache, simultaneously generates the flow synchronization control of each forwarding engine, coordinates each forwarding engine to analyze the message and acquires the output interface of the message.
The message analyzing and forwarding module is used for analyzing and forwarding messages, forwarding various common services, supporting user-defined protocol message processing and completing multicast copying of the messages. Analyzing port input messages, acquiring each domain of the messages L2-L7, processing stacking forwarding information, and generating a message forwarding command; obtaining a forwarding domain of the message according to Hash calculation, realizing the search of a 4-level flow table, and carrying out corresponding processing according to a search result; the L2 processing part supports the forwarding processing based on MAC + VLAN of the universal switching chip; the route processing part is used for supporting the 3-layer forwarding processing of a general TCP/IP protocol and supporting IPv4/6 and multicast forwarding processing; and sending the specific message to the PS part for soft processing.
And the buffer management module discards the message according to the port, the queue buffer filling state and the discarding strategy configured by the user.
And the queue management module is used for managing a buffer pointer, distributing a buffer for the input message and recovering the buffer after the message is read from the buffer.
And the message modification module modifies the content of the message according to the descriptor of the message, and the processing of the content of the message is reflected to the output message.
In addition, an expansibility test can be provided for the design of a plurality of general processor hardcores, and a plurality of FPGAs are interconnected by using an expansion interface so as to generate a scheme of a plurality of working clusters.
The whole environment of the invention mainly comprises a Zynq series MPSoC development board, a cross compiling environment and a network test environment comprising a network tester, and the platform can rapidly complete function design, compiling verification and system test.
The Zynq series MPSoC development board mainly comprises a PS part and a PL part, wherein the PS part comprises a powerful heterogeneous multiprocessing infrastructure of four ARM Cortex-A53 kernels and two ARM Cortex-R5 kernels, and the PS part runs a Petalinux system support instruction to configure a network processor and process specific complex data packets; the PL part comprises programmable logic and a high-speed interface, and the PL part is designed to complete a hardware accelerator, an input/output interface and PS-PL connection.
When the network hardware accelerator module is used, instructions are received and sent through upper computer software, the instructions compile configuration information through software loaded on an operating system, the instructions configure the network hardware accelerator module through the PS-PL part, the network hardware accelerator module processes port data according to a configuration mode, the network module uploads and downloads data information through the PS-PL part, and the processed data and the information can be checked through the upper computer software.
The PL part generates a hardware accelerator forwarding module, the forwarding module adopts a scheduling structure with symmetrical input and output, has expandability and can realize parallel forwarding according to requirements. The forwarding module does not forward the message content, only transmits intermediate results of various forwarding processes, and adopts a message cache array with a distributed message cache array structure to schedule the message to be output to a port.
The multi-core processor is based on 4 general ARM Cortex-A53 kernels, various hardware acceleration engines are used as auxiliary aids, high-speed interconnection of a CPU core, the various hardware acceleration engines and a storage unit is realized by designing an internal resource interconnection network, and high-speed network processing capability and flexible capacity of adding various service services are improved. A general CPU is used as an inner core, a network processing hardware accelerator suitable for parallel is added, a Petaliinux operating system is mounted, and the whole design completion degree is high.
In a word, the Zynq UltraScale + MPSoC of the Sailing is selected to provide a powerful heterogeneous multiprocessing infrastructure comprising four ARM Cortex-A53 cores and two real-time processor cores based on functional design and performance requirements. Besides the core computing infrastructure, the system also comprises a series of rich hardened peripheral IP architectures, and the design mode can be flexibly realized. The multi-core network processor adopts a general CPU as an inner core, realizes the parallel processing of messages by the multi-inner core, designs a network hardware accelerator at a logic programming part and can support an operating system at the same time.
Claims (3)
1. A multi-core FPGA network processor comprises an MPSoC on-chip multi-core processor FPGA, wherein the FPGA comprises a PS processing system and a PL programmable logic part, the PS processing system and the PL programmable logic part are connected through a PS-PL connection interface part, the PL programmable logic part is also connected with an input/output interface, and the PS processing system runs with a Petaliinux system; the PL programmable logic part is used for realizing a network hardware accelerator and finishing data hardware processing, and specifically comprises the following modules:
the scheduling management module is used for multiplexing the content of the input port cache message into a data bus and then writing the content into a global message cache, realizing packet header separation and simultaneously generating the flow synchronization control of each forwarding engine, coordinating each forwarding engine to analyze the message and acquiring the output interface of the message;
the message analyzing and forwarding module is used for completing message analyzing and forwarding, forwarding service and user-defined protocol messages and simultaneously performing multicast copying on the messages;
the buffer management module is used for discarding the message according to the port, the queue buffer filling state and the discarding strategy configured by the user;
the queue management module is used for establishing a buffer pointer, distributing a buffer for an input message and recovering the buffer after the message is read from the buffer;
the message modification module is used for modifying the content of the message according to the descriptor of the message and reflecting the processing of the message content to the output message;
the input and output interface is used for receiving and transmitting network port data, the Petalinx system of the PS processing system receives an instruction of an upper computer, compiles instruction configuration information, configures the network hardware accelerator through the PS-PL connection interface part, processes the network port data according to a configuration mode by the network hardware accelerator, and interacts data information with the Petalinx system through the PS-PL connection interface part.
2. The multi-core FPGA network processor of claim 1, wherein the analysis forwarding message module adopts a scheduling structure with symmetrical input and output, and realizes parallel forwarding as required; when the analysis message forwarding module forwards the message, the message content is not forwarded, only intermediate results of various forwarding processes are transmitted, and the message is scheduled to be output to a port by adopting a distributed message cache array structure.
3. The multi-core FPGA network processor of claim 1, wherein the FPGA is a ZU19EG chip.
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Cited By (4)
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| CN111984492A (en) * | 2020-08-28 | 2020-11-24 | 思尔芯(上海)信息科技有限公司 | Prototype verification platform for concurrently controlling multiple FPGAs |
| WO2022235217A1 (en) * | 2021-05-07 | 2022-11-10 | 脸萌有限公司 | Integrated circuit, and data processing apparatus and method |
| CN115665051A (en) * | 2022-12-29 | 2023-01-31 | 北京浩瀚深度信息技术股份有限公司 | Method for realizing high-speed flow table based on FPGA + RLDRAM3 |
| CN117312202A (en) * | 2023-11-30 | 2023-12-29 | 浙江国利信安科技有限公司 | System on chip and data transmission method for system on chip |
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