CN111984492A - Prototype verification platform for concurrently controlling multiple FPGAs - Google Patents
Prototype verification platform for concurrently controlling multiple FPGAs Download PDFInfo
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- CN111984492A CN111984492A CN202010888839.9A CN202010888839A CN111984492A CN 111984492 A CN111984492 A CN 111984492A CN 202010888839 A CN202010888839 A CN 202010888839A CN 111984492 A CN111984492 A CN 111984492A
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Abstract
The embodiment of the invention provides a prototype verification platform for concurrently controlling a plurality of Field Programmable Gate Arrays (FPGAs), which belongs to the technical field of computer-aided equipment and specifically comprises a verification controller and an external port; the external port is used for transmitting a verification instruction to the verification controller; the verification controller is used for controlling the operation of at least one group of FPGA in each FPGA based on the verification instruction, reading the operation result information generated by the at least one group of FPGA based on the verification instruction, reading the storage information of each FPGA and transmitting the operation result information and the storage information between the at least two groups of FPGAs; the external port is also used for outputting the information received by the verification controller. Through the processing scheme of the invention, the common management and interaction of a plurality of FPGAs can be realized, and the speed of concurrent downloading is effectively improved.
Description
Technical Field
The invention relates to the technical field of computer-aided equipment, in particular to a prototype verification platform for concurrently controlling a plurality of FPGAs.
Background
With the development of the chip industry, the chip integration degree is higher and higher, the logic gate scale is larger and larger, the number of logic gates of a single FPGA prototype verification platform used for designing a chip is limited, and in order to meet the prototype verification of a larger-scale chip, a large-scale design needs to be distributed to a plurality of FPGAs for operation and can be controlled in real time in parallel. According to the existing scheme, the FPGA on the development board is interactively controlled one by one, the performance and the requirement that a plurality of FPGAs are controlled simultaneously cannot be met, and the high-performance concurrent control FPGA becomes a problem to be solved urgently by the design of the EDA with high integration level.
Disclosure of Invention
In view of this, the embodiment of the present invention provides a prototype verification platform for concurrently controlling multiple FPGAs, which can implement common management and interaction for multiple FPGAs, and effectively improve the speed of concurrent downloading.
In order to achieve the technical purpose, the invention adopts the following specific technical scheme:
a prototype verification platform for concurrently controlling a plurality of FPGAs comprises a verification controller and an external port;
the external port is used for transmitting a verification instruction to the verification controller;
the verification controller is used for controlling the operation of at least one group of FPGA in each FPGA based on the verification instruction, reading the operation result information generated by the at least one group of FPGA based on the verification instruction, reading the storage information of each FPGA and transmitting the operation result information and the storage information between the at least two groups of FPGAs;
the external port is also used for outputting the information received by the verification controller.
Further, a PS end logic program and a PL end logic program are arranged on the verification controller; the PS terminal logic program is used for converting the verification instruction into a control instruction and transmitting the operation result information and the storage information between at least two groups of FPGAs;
and the PL end logic program is used for controlling the operation of the FPGA according to the control instruction, sending the operation result to the PS end logic program after the FPGA generates operation result information, and reading the storage information of each FPGA and sending the storage information to the PS end logic program.
Further, the prototype verification platform for concurrently controlling the plurality of FPGAs further comprises peripheral hardware, and the peripheral hardware is in communication connection with the PL end logic program; the PL end logic program is also used for controlling the operation of the peripheral hardware according to the control instruction; the peripheral hardware is used for controlling and managing each FPGA, controlling and managing an external function daughter card of each FPGA and controlling and managing a communication interface of each FPGA.
Furthermore, the peripheral hardware comprises a voltage control device, a dial switch and a test daughter card;
the voltage control equipment is used for providing voltage control for the FPGA;
the dial switch is used for transmitting the operation result information and the storage information to the FPGA;
the test daughter card is used for supporting the functional module of the FPGA.
Further, the test daughter card includes a memory test daughter card, a network card test daughter card, a PCIE test daughter card, and a hard disk test daughter card.
Furthermore, the test daughter card further comprises a dial switch, and the dial switch is used for transmitting the operation result information and the storage information between at least two groups of the FPGAs.
Further, the PS end logic program is also used to set a test voltage for the test daughter card.
Further, the external port is also used for accessing the PS end logic program, setting network IP information for the FPGA, and reading, writing, and controlling the PS end logic program.
Further, the external port is an ethernet port.
By adopting the technical scheme, the invention can bring the following beneficial effects:
1. the invention can realize the common management and interaction of a plurality of FPGAs, and effectively improves the speed of concurrent downloading.
2. The invention can arrange a plurality of peripheral hardware in the system by a mode of common control of the PS logic and the PL logic so as to expand more functions.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of module cooperation of a prototype verification platform for concurrently controlling a plurality of FPGAs in an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than the number, shape and size of the components in practical implementation, and the type, quantity and proportion of the components in practical implementation can be changed freely, and the layout of the components can be more complicated.
In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
The embodiment of the invention provides a prototype verification platform for concurrently controlling a plurality of FPGAs, which comprises a verification controller and an external port, wherein the verification controller is connected with the external port;
the external port is used for transmitting a verification instruction to the verification controller;
the verification controller is used for controlling the operation of at least one group of FPGA in each FPGA based on the verification instruction, reading the operation result information generated by the at least one group of FPGA based on the verification instruction, reading the storage information of each FPGA and transmitting the operation result information and the storage information between the at least two groups of FPGAs;
the external port is also used for outputting the information received by the verification controller.
In one embodiment, the authentication controller is provided with a PS terminal logic program and a PL terminal logic program; the PS terminal logic program is used for converting the verification instruction into a control instruction and transmitting the operation result information and the storage information between at least two groups of FPGAs;
and the PL end logic program is used for controlling the operation of the FPGA according to the control instruction, sending the operation result to the PS end logic program after the FPGA generates operation result information, and reading the storage information of each FPGA and sending the storage information to the PS end logic program.
In this embodiment, the PL side logic program opens a channel corresponding to the PS side logic program for each concurrent function module, and the PS side logic program corresponds to the channel of the PL side logic program one by one in a network port manner, so that the function that the PS side logic program can control the logic of the PL side logic program in parallel is realized. The FPGA is hung on an I2C bus, and devices on the I2C bus are managed and controlled in a unified mode by a logic program at the PL end.
In this embodiment, when the user initiates the parallel download command, the user PC starts the server of the PS side logic program connected to the port corresponding to the FPGA number, and any subsequent data related to the FPGA control is issued to the server of the PS side logic program through this port, and the PS side logic program server then forwards the data to the bus address corresponding to the FPGA number. When reading FPGA data, after a user is connected with a PS terminal logic program service port corresponding to the FPGA number, sending a reading command to a bus address corresponding to the FPGA number, forwarding a PL terminal logic program to the FPGA, responding to data access by the FPGA, transmitting response data back to the PL terminal logic program, transmitting the response data back to the PS terminal logic program by the PL terminal logic program through the bus address corresponding to the FPGA number, and transmitting the data back to the user by the PS terminal.
In one embodiment, the prototype verification platform for concurrently controlling multiple FPGAs further includes peripheral hardware, the peripheral hardware is in communication connection with the PL-side logic program, and both are hung on the I2C bus, and the PL-side logic program manages and controls devices on the I2C bus in a unified manner; the PL end logic program is also used for controlling the operation of the peripheral hardware according to the control instruction; the peripheral hardware is used for controlling and managing each FPGA, controlling and managing an external function daughter card of each FPGA and controlling and managing a communication interface of each FPGA.
The peripheral hardware comprises voltage control equipment, a dial switch and a test daughter card;
the voltage control equipment is used for providing voltage control for the FPGA;
the dial switch is used for transmitting the operation result information and the storage information to the FPGA;
the test daughter card is used for supporting the functional module of the FPGA.
In one embodiment, the test daughter card includes a memory test daughter card, a network card test daughter card, a PCIE test daughter card, and a hard disk test daughter card.
In one embodiment, the test daughter card further comprises a dial switch, and the dial switch is used for transmitting the operation result information and the storage information between at least two groups of the FPGAs.
In one embodiment, the PS side logic program is also used to set a test voltage for the test daughter card.
In one embodiment, the external port is further configured to access the PS side logic program, set network IP information for the FPGA, and read, write, and control the PS side logic program.
In one embodiment, the external port is an ethernet port.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A prototype verification platform for controlling a plurality of FPGAs concurrently is characterized in that: the system comprises a verification controller and an external port;
the external port is used for transmitting a verification instruction to the verification controller;
the verification controller is used for controlling the operation of at least one group of FPGA in each FPGA based on the verification instruction, reading the operation result information generated by the at least one group of FPGA based on the verification instruction, reading the storage information of each FPGA and transmitting the operation result information and the storage information between the at least two groups of FPGAs;
the external port is also used for outputting the information received by the verification controller.
2. A prototype verification platform for concurrent control of multiple FPGAs according to claim 1, wherein: the verification controller is provided with a PS end logic program and a PL end logic program; the PS terminal logic program is used for converting the verification instruction into a control instruction and transmitting the operation result information and the storage information between at least two groups of FPGAs;
and the PL end logic program is used for controlling the operation of the FPGA according to the control instruction, sending the operation result to the PS end logic program after the FPGA generates operation result information, and reading the storage information of each FPGA and sending the storage information to the PS end logic program.
3. A prototype verification platform for concurrent control of multiple FPGAs according to claim 2, wherein: the prototype verification platform for concurrently controlling the plurality of FPGAs further comprises peripheral hardware, and the peripheral hardware is in communication connection with the PL terminal logic program; the PL end logic program is also used for controlling the operation of the peripheral hardware according to the control instruction; the peripheral hardware is used for controlling and managing each FPGA, controlling and managing an external function daughter card of each FPGA and controlling and managing a communication interface of each FPGA.
4. A prototype verification platform for concurrent control of multiple FPGAs according to claim 3, wherein: the peripheral hardware comprises voltage control equipment, a dial switch and a test daughter card;
the voltage control equipment is used for providing voltage control for the FPGA;
the dial switch is used for transmitting the operation result information and the storage information to the FPGA;
the test daughter card is used for supporting the functional module of the FPGA.
5. A prototype validation platform for concurrent control of multiple FPGAs according to claim 4, wherein: the test daughter card comprises a memory test daughter card, a network card test daughter card, a PCIE test daughter card and a hard disk test daughter card.
6. A prototype validation platform for concurrent control of multiple FPGAs according to claim 5, wherein: the test daughter card further comprises a dial switch, and the dial switch is used for transmitting the operation result information and the storage information between at least two groups of the FPGAs.
7. A prototype validation platform for concurrent control of multiple FPGAs according to claim 5, wherein: the PS terminal logic program is also used for setting a test voltage for the test daughter card.
8. A prototype verification platform for concurrent control of multiple FPGAs according to claim 2, wherein: the external port is also used for accessing the PS end logic program, setting network IP information for the FPGA and reading, writing and controlling the PS end logic program.
9. A prototype verification platform for concurrent control of multiple FPGAs according to claim 1, wherein: the external port is an Ethernet port.
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| CN115221001A (en) * | 2022-06-29 | 2022-10-21 | 芯启源(上海)半导体科技有限公司 | Data verification platform, data verification method, and computer-readable storage medium |
| CN115343605A (en) * | 2022-06-29 | 2022-11-15 | 芯启源(上海)半导体科技有限公司 | Chip design testing method, system, medium, equipment and FPGA prototype verification platform |
| CN116185935A (en) * | 2023-02-23 | 2023-05-30 | 上海思尔芯技术股份有限公司 | FPGA prototype verification method, system, medium and computing device of controller |
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