CN115343605A - Chip design testing method, system, medium, equipment and FPGA prototype verification platform - Google Patents

Abstract

The invention provides a chip design test method, a system, a medium, a device and an FPGA prototype verification platform; the FPGA prototype verification platform comprises at least two verification blocks; each verification block comprises a control FPGA and a test FPGA; the control FPGA is connected with the test FPGA and is used for controlling the test FPGA to test the design of the chip; according to the invention, through dividing the resources of the FPGA prototype verification platform, a design verification environment can be provided for a plurality of users at the same time, so that the resource waste of the FPGA prototype verification platform is effectively avoided, the verification efficiency of the client is improved, and the cost is reduced.

Description

Chip design testing method, system, medium, equipment and FPGA prototype verification platform

Technical Field

The invention belongs to the technical field of chip design test, and particularly relates to a chip design test method, a chip design test system, a chip design test medium, a chip design test device and an FPGA prototype verification platform.

Background

With the development of integrated circuits, the scale of the integrated circuits is increasing, the functional modules of the system are more and more complex, the design must be more rigorous and normative due to the huge design scale and the complex functions, the tape-out failure may be caused by tiny errors, and the release cycle is lengthened, so the test verification of the integrated circuits becomes very important.

The method is based on pure software, dynamic simulation technology and formal verification technology, and has inherent limitations, so that some chip design errors cannot be discovered by dynamic function simulation, because the simulation speed cannot be compared with the actual chip working speed, and an FPGA system can meet the requirement.

Therefore, compared with software simulation, the prototype verification system based on the FPGA can not only accelerate the development of ASIC and other designs, shorten the research and development period and reduce the development cost of ASIC application systems, but also has the advantages of high simulation speed, allowing designers to perform real operation on a platform and the like, and improves the chip flow success rate.

However, due to the uniqueness of the prototype verification platform, many times we do not need all FPGA resources to verify our design, which causes waste of resources.

Disclosure of Invention

In view of the above disadvantages of the prior art, an object of the present invention is to provide a chip design testing method, system, medium, device and FPGA prototype verification platform, which are used to solve the problem of resource waste of the existing FPGA prototype verification platform.

To achieve the above and other related objects, the present invention provides an FPGA prototype verification platform, comprising: at least two proof blocks; each verification block comprises a control FPGA and a test FPGA; the control FPGA is connected with the test FPGA and used for controlling the test FPGA to test the design of the chip.

In an embodiment of the present invention, the FPGA prototype verification platform further includes: at least one sub-control FPGA; at least two verification blocks are connected to form a multi-board FPGA; one multi-board FPGA corresponds to one sub-control FPGA; the branch control FPGA is connected with the multi-board FPGA to form a verification unit; the number of the verification units is at least two.

In an embodiment of the invention, at least one of the verification units forms a first verification unit group; forming at least one second verification unit group except the verification units in the first verification unit group in the verification units; the number of verification units in the second verification unit group and the connection relationship between the verification units are the same as those in the first verification unit group, or when the number of the verification units is at least three, any two verification units form a third verification unit group.

In an embodiment of the invention, the FPGA prototype verification platform further includes: a general control FPGA; and the master control FPGA is connected with the verification unit.

A chip design test method is applied to electronic equipment and comprises the following steps: acquiring data to be tested based on a chip; based on the environment configuration file in the data to be tested, sending the data to be tested to a target position on the FPGA prototype verification platform so that the FPGA prototype verification platform realizes the test of the design of the chip based on the data to be tested; the environment profile is used to configure the target location.

In an embodiment of the present invention, the method further includes the following steps: after the step of sending the data to be tested to the target position, responding to the received feedback information sent by the FPGA prototype verification platform, and judging that the target position is occupied; in response to the target location being occupied, modifying the environmental profile to alter the target location; sending the data to be tested to the changed target position so that the FPGA prototype verification platform realizes the test of the design of the chip based on the data to be tested; the modified target location is located on the FPGA prototype verification platform.

In an embodiment of the present invention, the chip-based obtaining of the data to be tested includes the following steps: acquiring the data to be tested based on the current resource use conditions of the chip and the FPGA prototype verification platform; the current resource usage includes at least: an occupied position on the FPGA prototype verification platform and/or an idle position on the FPGA prototype verification platform; the target location belongs to the free location.

The present invention provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the chip design testing method described above.

The present invention provides an electronic device including: a processor and a memory; the memory is used for storing a computer program; the processor is used for executing the computer program stored in the memory so as to enable the electronic equipment to execute the chip design testing method.

The invention provides a chip design test system, comprising: the electronic equipment and the FPGA prototype verification platform are provided; the electronic equipment is connected with the FPGA prototype verification platform.

As described above, the chip design test method, system, medium, device and FPGA prototype verification platform according to the present invention have the following advantages:

(1) Compared with the prior art, the invention provides the FPGA prototype verification platform suitable for multiple users, and the resources of the FPGA prototype verification platform are divided, so that a design verification environment can be provided for multiple users at the same time, the resource waste of the FPGA prototype verification platform is effectively avoided, the verification efficiency of the users is improved, and the cost is reduced.

(2) The verification unit is formed by connecting a plurality of verification blocks, so that the verification unit can realize the verification test of the complicated SOC/ASIC design, and can also allow a plurality of users to access and operate the FPGA prototype verification platform by planning reasonable FPGA resources for each design according to different requirements of different design gate-level scales, thereby realizing the simultaneous verification of a plurality of designs.

(3) The invention designs the connection relation between the verification units, can verify the design of the chip by modifying the environment configuration file and using other idle positions on the FPGA prototype verification platform when the configured target position is occupied, and ensures that the verification result is not influenced.

Drawings

Fig. 1 is a schematic structural diagram of a terminal according to an embodiment of the invention.

Fig. 2 is a schematic structural diagram of an FPGA prototype verification platform according to an embodiment of the present invention.

Fig. 3 is a schematic structural diagram of an FPGA prototype verification platform according to another embodiment of the present invention.

Fig. 4 is a schematic structural diagram of an FPGA prototype verification platform according to another embodiment of the present invention.

Fig. 5 is a schematic structural diagram of an FPGA prototype verification platform according to still another embodiment of the present invention.

Fig. 6 is a schematic structural diagram of an FPGA prototype verification platform according to still another embodiment of the present invention.

FIG. 7 is a flowchart illustrating a chip design test method according to an embodiment of the invention.

FIG. 8 is a flowchart illustrating a chip design test method according to an embodiment of the present invention when the target location is occupied.

FIG. 9 is a schematic structural diagram of a chip design test system according to an embodiment of the invention.

Description of the reference symbols

1. Terminal device

11. Processing unit

12. Memory device

121. Random access memory

122. Cache memory

123. Storage system

124. Program/utility tool

1241. Program module

13. Bus line

14. Input/output interface

15. Network adapter

2. External device

3. Display device

21. Verification block

211. Controlling an FPGA

212. Testing FPGA

22. Separately controlled FPGA

23. Multi-board FPGA

24. Verification unit

25. First verification unit group

26. Second verification unit group

27. General control FPGA

91. Electronic device

92 FPGA prototype verification platform

S71 to S72

S81 to S83 steps

Detailed Description

The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

Compared with the prior art, the chip design test method, the system, the medium, the equipment and the FPGA prototype verification platform provided by the invention have the advantages that the FPGA prototype verification platform suitable for multiple users is provided, and the resources of the FPGA prototype verification platform are divided, so that a design verification environment can be simultaneously provided for the multiple users, the resource waste of the FPGA prototype verification platform is effectively avoided, the verification efficiency of the clients is improved, and the cost is reduced; the verification unit is formed by connecting a plurality of verification blocks, so that the verification unit can realize the verification test of a complex SOC/ASIC design, and reasonable FPGA resources are planned for each design according to different requirements of different design gate-level scales, a plurality of users can be allowed to access and operate the FPGA prototype verification platform, and a plurality of designs can be verified simultaneously; the invention designs the connection relation between the verification units, can verify the design of the chip by modifying the environment configuration file and using other idle positions on the FPGA prototype verification platform when the configured target position is occupied, and ensures that the verification result is not influenced.

The storage medium of the present invention stores thereon a computer program that realizes the chip design test method described below when executed by a processor. The storage medium includes: a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, a usb disk, a Memory card, or an optical disk, which can store program codes.

Any combination of one or more storage media may be employed. The storage medium may be a computer-readable signal medium or a computer-readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a RAM, a ROM, an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).

The present invention is described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the computer program instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

The electronic device of the invention comprises a processor and a memory.

The memory is used for storing a computer program; preferably, the memory comprises: various media that can store program codes, such as ROM, RAM, magnetic disk, U-disk, memory card, or optical disk.

The processor is connected with the memory and is used for executing the computer program stored in the memory so as to enable the electronic equipment to execute the chip design testing method.

Preferably, the Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components.

In an embodiment, the electronic device includes a terminal and/or a server.

Fig. 1 shows a block diagram of an exemplary terminal 1 suitable for implementing an embodiment of the invention.

The terminal 1 shown in fig. 1 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiment of the present invention.

As shown in fig. 1, the terminal 1 is in the form of a general purpose computing device. The components of the terminal 1 may include, but are not limited to: one or more processors or processing units 11, a memory 12, and a bus 13 that couples various system components including the memory 12 and the processing unit 11.

Bus 13 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, such architectures include, but are not limited to, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an enhanced ISA (enhanced ISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

The terminal 1 typically includes a variety of computer system readable media. These media may be any available media that can be accessed by terminal 1 and includes both volatile and nonvolatile media, removable and non-removable media.

Memory 12 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 121 and/or cache memory 122. The terminal 1 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 123 may be used to read from and write to non-removable, nonvolatile magnetic media (not shown in FIG. 1 and commonly referred to as a "hard drive"). Although not shown in FIG. 1, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 13 by one or more data media interfaces. Memory 12 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.

Program/utility 124 having a set (at least one) of program modules 1241 may be stored in, for example, memory 12, such program modules 1241 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which examples or some combination thereof may comprise an implementation of a network environment. Program modules 1241 generally perform the functions and/or methodologies of embodiments of the invention as described herein.

The terminal 1 may also communicate with one or more external devices 2 (e.g., keyboard, pointing device, display 3, etc.), one or more devices that enable a user to interact with the terminal 1, and/or any device (e.g., network card, modem, etc.) that enables the terminal 1 to communicate with one or more other computing devices. Such communication may be through an input/output (I/O) interface 14. Also, the terminal 1 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the internet) through the network adapter 15. As shown in fig. 1, the network adapter 15 communicates with the other modules of the terminal 1 via the bus 13. It should be understood that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the terminal 1, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, to name a few.

As shown in fig. 2, in an embodiment, the FPGA prototype verification platform of the present invention includes at least two verification blocks 21 (the example of fig. 2 including two verification blocks 21 is used for illustration).

Specifically, each of the verification blocks 21 includes a control FPGA211 and a test FPGA212; the control FPGA211 is connected to the test FPGA212, and is configured to control the test FPGA212 to test a design of a chip.

It should be noted that, sometimes, the capacity of the logic gate of the FPGA of the single board can meet the logic requirement of the user (for some simple SOC/ASIC designs), that is, the test of the design of one chip can be implemented by one verification block 21; in the invention, by arranging at least two verification blocks 21, the design test of at least two chips can be realized simultaneously, thereby realizing multi-user access and operation of the FPGA prototype verification platform.

Further, in the field of FPGA prototype verification, when the capacity of the logic gate of the FPGA of a single board does not meet the logic requirement of a user (for some complicated SOC/ASIC designs), multiple FPGA boards need to be connected, that is, the FPGA of a multilayer board needs to be completed cooperatively; specifically, FPGAs can implement mutual transmission of signals through mutual pin connection, but considering the uniqueness of the FPGA prototype verification platform, it is often not necessary to verify the design by all FPGA resources on the FPGA prototype verification platform, which may cause waste of resources.

As shown in fig. 3, in one embodiment, the FPGA prototype verification platform further includes at least one control FPGA22.

Specifically, at least two verification blocks 21 are connected to form a multi-board FPGA23 (for example, fig. 3 includes four verification blocks 21); one multi-board FPGA23 corresponds to one sub-control FPGA22; the sub-control FPGA22 is connected with the multi-board FPGA23 to form a verification unit 24.

It should be noted that the number of the verification units 24 is at least two (taking two verification units 24 included in fig. 3 as an example for explanation); specifically, each verification unit 24 is used for performing verification testing on a design, and two verification units 24 can implement testing on designs of two chips.

Further, when one verification unit 24 needs to be occupied for one design verification, each verification unit 24 on the FPGA prototype verification platform can be used; of course, there may be designs whose verification requires the use of more than one verification unit 24.

As shown in fig. 4, in an embodiment, when the number of the verification units 24 is at least three (taking the example that fig. 4 includes four verification units 24, which correspond to the verification units a, B, C, and D in fig. 4, respectively), any two verification units 24 form a third verification unit group, that is, a third verification unit group formed by any two verification units 24 has the same function as another third verification unit group formed by any two other verification units 24, and verification tests can be performed on the same design.

Specifically, if a design is verified using verification unit a and verification unit B in fig. 4, but verification unit a is occupied by other designs, then verification unit B and verification unit C, or verification unit B and verification unit D, or verification unit C and verification unit D may be selected to verify the design.

It should be noted that, in consideration of layout wiring and actual production, the layout in fig. 4 is complicated.

As shown in fig. 5, in one embodiment, at least one of the verification units 24 forms a first verification unit group 25; at least one second verification cell group 26 is formed among the plurality of verification cells 24 except the verification cells 24 of the first verification cell group 25; the number of verification cells 24 in the second verification cell group 26 and the connection relationship between verification cells 24 are the same as those of the first verification cell group 25.

Specifically, the explanation is given taking as an example that the first verification cell group 25 and the second verification cell group 26 each include two verification cells 24 in fig. 5; the verification units E, F, G, H, I, J in fig. 5 are the verification units 24, wherein the verification units E and F are connected by FMC connectors to form a first verification unit group 25; the verification unit G and the verification unit H are connected through an FMC connector to form a second verification unit group 26; the verification unit I and the verification unit J are connected by an FMC connector to form another second verification unit group 26.

It should be noted that both the first verification cell group 25 and the second verification cell group 26 can be used to verify a certain design; when verifying the design using the first verifying unit group 25, if the first verifying unit group 25 is occupied by other designs, the design may be verified using any one second verifying unit group 26; specifically, by designing the verification cells 24 in the first verification cell group 25 and the second verification cell group 26, the verification result is not affected when the first verification cell group 25 is replaced with the second verification cell group 26.

In the present invention, it is ensured that the second and first verifying unit groups 26 and 25 can be arbitrarily replaced by designing the number and wiring manner of the verifying units 24 in the first and second verifying unit groups 25 and 26.

In the design of fig. 5, the wiring is simpler in actual production than in fig. 4.

As shown in fig. 5, in an embodiment, on the FPGA prototype verification platform, each minimum unit formed by cascading a plurality of FPGAs is referred to as a verification unit, it is assumed that a user king uses a verification unit E & verification unit F when performing design verification for the first time, and when performing design verification for the next time, the user king finds that the verification unit E & verification unit F has been reduced by the user Liu Zhanyong, and at this time, the user king can use a verification unit G & verification unit H for verification instead, and each verification of design may not occupy all FPGA resources in the verification unit, in order to ensure that the verification unit is replaced to perform testing without affecting the test result, in hardware design, it should be ensured that pin connections between FPGAs in each verification unit are completely the same, and when using a plurality of verification units, it is also ensured that when the verification unit is replaced to perform testing, pin connections between every two verification units may be the same, so that only when the verification unit is replaced to perform design verification, the environment of the FPGA prototype verification platform may not affect the verification result.

Further, in actual production, the FPGA prototype verification platform is designed by considering the effect that the finally formed FPGA prototype verification platform is prepared to make interchange between which verification units 24 (corresponding to the first verification unit group 25) can be made.

As shown in fig. 5, in an embodiment, the FPGA prototype verification platform further includes a general control FPGA27.

Specifically, the general control FPGA27 is connected to the verification unit 24.

The working principle of the FPGA prototype verification platform of the present invention is further explained by the following specific embodiments.

As shown in fig. 6, taking a product MIMIC-32 as an example, the product manages 8 verification units 24 in the device by using a main controller C32 (corresponding to the above-mentioned general control FPGA 27), which respectively corresponds to the verification unit K, the verification unit L, the verification unit M, the verification unit N, the verification unit O, the verification unit P, the verification unit Q, and the verification unit R in fig. 6, and each verification unit 24 has multiple FPGAs in cascade connection, and pin connections between FPGAs in each verification unit 24 are completely the same, and the 8 verification units 24 are connected by using a backplane at the same time, pin connections between the verification units K-N and O-R are completely the same, and pin connections between the verification units K-L/verification units M-N/verification units O-P/verification units Q-R are also completely the same; therefore, when the design only occupies one verification unit, any verification unit can be replaced for design verification during the second design verification, when the design occupies 2 verification units, the verification unit K & verification unit L can be replaced with the verification unit M & verification unit N, the verification unit O & verification unit P and the verification unit Q & verification unit R for design verification, and when the design occupies 3-4 verification units, the verification unit K & verification unit L & verification unit M (& verification unit N) can be replaced with the verification unit O & verification unit P & verification unit Q (& verification unit R) for design verification.

It should be noted that, after the FPGA prototype verification platform verifies a design (the design may occupy a verification block, a verification unit, or a verification unit group), the space occupied by the design during verification is released, so that the available space during next design verification includes the space occupied by the design during verification.

As shown in fig. 7, in an embodiment, the chip design testing method of the present invention is applied to an electronic device, and includes the following steps:

and S71, acquiring data to be tested based on the chip.

Specifically, a database file, that is, the data to be tested, is generated by performing operations such as code compiling, constraint condition setting, RTL code synthesis, netlist file generation, layout and routing on the design of the chip.

It should be noted that the database file includes an environment configuration file, where the environment configuration file is used to locate how much and a specific location of the FPGA resource amount required by the design, that is, to configure a target location for verifying the design; for example, the target position is the verification unit K & verification unit L described above.

And S72, sending the data to be tested to a target position on the FPGA prototype verification platform based on the environment configuration file in the data to be tested so that the FPGA prototype verification platform realizes the test of the design of the chip based on the data to be tested.

Specifically, the electronic device is connected to the FPGA prototype verification platform and configured to send the data to be tested to a target location on the FPGA prototype verification platform.

In one embodiment, the chip-based acquisition of the data to be tested includes the following steps: and acquiring the data to be tested based on the current resource use conditions of the chip and the FPGA prototype verification platform.

It should be noted that the current resource usage at least includes, but is not limited to, occupied locations on the FPGA prototype verification platform and/or idle locations on the FPGA prototype verification platform; the target location belongs to the free location.

Specifically, before the database file is generated, the electronic device already knows which positions on the FPGA prototype verification platform are occupied and/or which positions are idle, so that when the database file is generated, a target position can be selected from the idle positions, thereby ensuring that the target position is always the idle position on the FPGA prototype verification platform, avoiding the trouble that the target position needs to be changed because the target position is occupied due to other designs being tested, and improving the verification efficiency.

It should be noted that how the electronic device knows which locations on the FPGA prototype verification platform are occupied and/or which locations are free is not a condition for limiting the present invention; for example, when a certain design occupies a certain position on the FPGA prototype verification platform for verification, the FPGA prototype verification platform generates usage information accordingly, and feeds the usage information back to the electronic device, where the usage information at least includes the position information on the FPGA prototype verification platform occupied by the design.

Further, it is also possible that when the electronic device sends the data to be tested to a target location on the FPGA prototype verification platform, the electronic device does not know whether the target location is occupied because other designs are being tested.

As shown in fig. 8, in an embodiment, after the step of sending the data to be tested to the target location, the method further includes the following steps:

and S81, judging that the target position is occupied in response to receiving the feedback information sent by the FPGA prototype verification platform.

Specifically, when the electronic device sends the data to be tested according to the target position in the environment configuration file, if the target position is occupied (at this time, the target position does not receive the data to be tested), the FPGA prototype verification platform generates a feedback message and sends the feedback message to the electronic device, so that the electronic device knows that the target position is occupied after receiving the feedback message.

And S82, responding to the target position being occupied, modifying the environment configuration file to change the target position.

It should be noted that the modified target location is located on the FPGA prototype verification platform.

Specifically, the environment configuration file in the database file is modified to place the data to be tested in which verification units to test, and other users can verify their own design in other idle verification units.

And S83, sending the data to be tested to the changed target position so that the FPGA prototype verification platform realizes the test of the design of the chip based on the data to be tested.

It should be noted that, when the target position is switched to perform design verification, the environment configuration file in the database file compiled by the design only needs to be relocated, and the environment configuration file can be downloaded to any needed and available FPGA for design verification.

It should be noted that the protection scope of the chip design testing method of the present invention is not limited to the execution sequence of the steps listed in this embodiment, and all the schemes of adding, subtracting, and replacing steps in the prior art according to the principle of the present invention are included in the protection scope of the present invention.

As shown in fig. 9, in an embodiment, the chip design testing system of the invention includes the electronic device 91 and the FPGA prototype verification platform 92.

Specifically, the electronic device 91 is connected to the FPGA prototype verification platform 92.

It should be noted that the working principle of the chip design test system is as follows:

by operating software on the electronic device 91, the design of the chip is packaged, and adding an environment configuration file to generate a database file, and then the database file can be downloaded to a corresponding FPGA through command operation, and if the FPGA resource is occupied, the database file can be replaced to other idle FPGA resources by changing the environment configuration file.

The electronic device 91 includes a server as an example:

specifically, the server may open multiple windows for different users to use; in the invention, by dividing the resources of the FPGA prototype verification platform 92, when a customer tests the design of the customer later, the server firstly utilizes the software of the customer to package the design of the customer, and then adds an environment configuration file to control which FPGA the design is downloaded to, so that other idle FPGA resources can be used by other users.

By the design of the pin connection of the verification unit on the FPGA prototype verification platform 92, when a user uses multiple FPGAs for design test, for example, the multiple FPGAs are occupied by another user next time, the user can change to other multiple FPGAs for test, and the logic between the FPGAs does not change.

It should be noted that the chip design testing system of the present invention can implement the chip design testing method of the present invention, but the implementation apparatus of the chip design testing method of the present invention includes, but is not limited to, the structure of the chip design testing system as illustrated in this embodiment, and all the structural modifications and substitutions of the prior art made according to the principles of the present invention are included in the scope of the present invention.

In summary, compared with the prior art, the chip design test method, the system, the medium, the device and the FPGA prototype verification platform provided by the invention provide the FPGA prototype verification platform suitable for multiple users, and by dividing the resources of the FPGA prototype verification platform, a design verification environment can be provided for multiple users at the same time, so that the resource waste of the FPGA prototype verification platform is effectively avoided, the verification efficiency of the users is improved, and the cost is reduced; the verification unit is formed by connecting a plurality of verification blocks, so that the verification unit can realize the verification test of a complex SOC/ASIC design, and reasonable FPGA resources are planned for each design according to different requirements of different design gate-level scales, a plurality of users can be allowed to access and operate the FPGA prototype verification platform, and a plurality of designs can be verified simultaneously; the invention designs the connection relation between the verification units, can verify the design of the chip by modifying the environment configuration file and using other idle positions on the FPGA prototype verification platform when the configured target position is occupied, and ensures that the verification result is not influenced; therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. An FPGA prototype validation platform, comprising: at least two proof blocks; each verification block comprises a control FPGA and a test FPGA;

the control FPGA is connected with the test FPGA and used for controlling the test FPGA to test the design of the chip.

2. The FPGA proto-verification platform of claim 1, further comprising: at least one sub-control FPGA; at least two verification blocks are connected to form a multi-board FPGA; one multi-board FPGA corresponds to one sub-control FPGA; the branch control FPGA is connected with the multi-board FPGA to form a verification unit; the number of the verification units is at least two.

3. The FPGA prototype verification platform of claim 2, wherein at least one of said verification units forms a first set of verification units; forming at least one second verification unit group except the verification units in the first verification unit group in the verification units; the number of verification units in the second verification unit group and the connection relationship between the verification units are the same as those in the first verification unit group, or

When the number of the verification units is at least three, any two of the verification units form a third verification unit group.

4. The FPGA prototype verification platform according to claim 2, further comprising: a general control FPGA; and the master control FPGA is connected with the verification unit.

5. A chip design test method is applied to electronic equipment and is characterized by comprising the following steps:

acquiring data to be tested based on a chip;

sending the data to be tested to a target position on the FPGA prototype verification platform according to any one of claims 1 to 4 based on an environment configuration file in the data to be tested, so that the FPGA prototype verification platform realizes the test of the design of the chip based on the data to be tested; the environment profile is used to configure the target location.

6. The chip design testing method of claim 5, further comprising the steps of:

after the step of sending the data to be tested to the target position, responding to the received feedback information sent by the FPGA prototype verification platform, and judging that the target position is occupied;

in response to the target location being occupied, modifying the environmental profile to alter the target location;

sending the data to be tested to the changed target position so that the FPGA prototype verification platform can test the design of the chip based on the data to be tested; the modified target location is located on the FPGA prototype verification platform.

7. The chip design testing method of claim 5, wherein the chip-based obtaining of data to be tested comprises the steps of: acquiring the data to be tested based on the current resource use conditions of the chip and the FPGA prototype verification platform; the current resource usage includes at least: an occupied position on the FPGA prototype verification platform and/or an idle position on the FPGA prototype verification platform; the target location belongs to the free location.

8. A storage medium on which a computer program is stored, characterized in that the computer program, when executed by a processor, implements the chip design testing method of any one of claims 5 to 7.

9. An electronic device, comprising: a processor and a memory;

the memory is used for storing a computer program;

the processor is configured to execute the computer program stored in the memory to cause the electronic device to perform the chip design testing method of any one of claims 5 to 7.

10. A chip design test system, comprising: the electronic device of claim 9 and the FPGA prototype verification platform of any one of claims 1-4;

the electronic equipment is connected with the FPGA prototype verification platform.

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