CN110941934A - FPGA prototype verification development board segmentation simulation system, method, medium and terminal - Google Patents
FPGA prototype verification development board segmentation simulation system, method, medium and terminal Download PDFInfo
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Abstract
The invention discloses a FPGA prototype verification development board segmentation simulation system, a method, a medium and a terminal, wherein the system comprises: the segmentation selection module is used for selecting an engineering design needing segmentation according to the user requirement; a design partitioning module for partitioning the engineering design selected for partitioning into a plurality of smaller designs by using a partitioning tool according to a result selected by the partitioning selection module, and deploying the partitioned design into a plurality of FPGAs of one or more development boards; the top layer module is used for calling the netlist file of each smaller designed FPGA after being divided; and the segmentation simulation and judgment module is used for generating the top layer module, directly simulating the segmented smaller design according to the netlist file called by the top layer module, verifying the accuracy of a simulation result, and confirming the running state of the design by a segmentation design and simulation mode aiming at the larger engineering design, so that a user can conveniently carry out the engineering design with high capacity and high complexity.
Description
Technical Field
The invention relates to the technical field of development board simulation, in particular to a segmentation simulation system, a segmentation simulation method, a segmentation simulation medium and a segmentation simulation terminal for an FPGA prototype verification development board.
Background
The development board is a circuit board for developing an embedded system, and comprises a series of hardware components such as a central processing unit, a memory, an input device, an output device, a data path/bus, an external resource interface and the like. The development board is generally customized by an embedded system developer according to development requirements, and can also be researched and designed by a user. The development board is used for a beginner to know and learn hardware and software of the system, and meanwhile, a part of the development board also provides a basic integrated development environment, software source codes, a hardware schematic diagram and the like. Common development boards include 51, ARM, FPGA and DSP development boards.
The development board is a circuit board for developing an embedded system, and comprises a series of hardware components such as a central processing unit, a memory, an input device, an output device, a data path/bus, an external resource interface and the like. In a general embedded system development process, hardware is generally divided into two platforms, one is a development platform (host), and the other is a target platform (target), i.e. a development board. The development platform described herein refers to a computer connected to a target platform through a transmission interface, such as a serial port (RS-232), USB, parallel port, or network (Ethernet).
In the process of designing the development board, a certain large design often exists and cannot be independently accommodated in one FPGA, so that the design of the development board is affected, and the result after division cannot be known by adopting a direct division mode, which easily causes problems.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a partitioning simulation system, a partitioning simulation method, a partitioning simulation medium and a terminal for an FPGA prototype verification development board, which can confirm the running state of a design by a partitioning design and simulation mode aiming at a larger engineering design, thereby facilitating a user to carry out engineering design with large capacity and high complexity and effectively solving the problems provided by the background technology.
The technical scheme adopted by the invention for solving the technical problems is as follows:
an FPGA prototype verification development board segmentation simulation system comprises:
the segmentation selection module is used for selecting an engineering design needing segmentation according to the user requirement;
a design partitioning module for partitioning the engineering design selected for partitioning into a plurality of smaller designs by using a partitioning tool according to a result selected by the partitioning selection module, and deploying the partitioned design into a plurality of FPGAs of one or more development boards;
the top layer module is used for calling the netlist file of each smaller designed FPGA after being divided;
and the segmentation simulation and judgment module is used for generating the top layer module, directly simulating the segmented smaller design according to the netlist file called by the top layer module, and verifying the accuracy of the simulation result.
Further, the capacity of the engineering design selected by the segmentation selection module is greater than the capacity of the standard engineering design.
Furthermore, the netlist file called by the top module mainly comprises a top-layer simulated Verilog file and netlist files corresponding to each FPGA.
Further, the Verilog file contains the input and output of the whole selected engineering design and the call incidence relation between each FPGA.
Further, the segmentation simulation and judgment module judges the simulation result after the simulation, if the simulation result is correct, the correct simulation result is output, the operation is continued, and if not, the simulation is stopped.
Further, when the segmentation tool of the design segmentation module segments the selected engineering design, the user may remotely input the segmentation requirements to the segmentation tool through the ethernet.
An FPGA prototype verification development board segmentation simulation method comprises the following steps:
selecting an engineering design to be segmented through a segmentation selection module according to user requirements;
according to the result selected by the segmentation selection module, the design segmentation module utilizes a segmentation tool to segment the engineering design selected for segmentation into a plurality of smaller designs, and the designs obtained by segmentation are deployed into a plurality of FPGAs of one or a plurality of development boards;
and the top module calls the netlist file of each small-design FPGA after being divided, adopts the division simulation and judgment module according to the called netlist file of each small-design FPGA after being divided, directly simulates the small-design FPGA after being divided, and verifies the accuracy of a simulation result.
The invention provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the method described above.
The present invention provides a terminal, including: a processor and a memory; the memory is used for storing a computer program; the processor is configured to execute the computer program stored in the memory to cause the terminal to perform the above-mentioned method.
Compared with the prior art, the invention has the beneficial effects that:
the invention can divide and deploy a certain larger engineering design or a certain larger module in the engineering design to a plurality of FPGAs, can select to generate a simulation top module, and uses the generated simulation top module to carry out simulation so as to confirm the correct running state of the divided design, thereby ensuring that a user can confirm the correctness of the running state of the design and the division result of the design when designing a chip design with high capacity and high complexity based on a plurality of FPGAs, and accelerating the development flow of SOC products.
Drawings
FIG. 1 is a schematic view of the overall working flow of the segmentation simulation method of the present invention;
FIG. 2 is a schematic view of the overall working process of the segmentation simulation system of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 2, the present invention provides an FPGA prototype verification development board segmentation simulation system, which includes:
the segmentation selection module is used for selecting an engineering design needing segmentation according to the user requirement;
a design partitioning module for partitioning the engineering design selected for partitioning into a plurality of smaller designs by using a partitioning tool according to a result selected by the partitioning selection module, and deploying the partitioned design into a plurality of FPGAs of one or more development boards;
the top layer module is used for calling the netlist file of each smaller designed FPGA after being divided;
and the segmentation simulation and judgment module is used for generating the top layer module, directly simulating the segmented smaller design according to the netlist file called by the top layer module, and verifying the accuracy of the simulation result.
Specifically, a partition selection module is used for selecting an engineering design to be partitioned, and the capacity of the engineering design selected by the partition selection module is larger than that of a standard engineering design, so that the problem that some large engineering designs are difficult to simulate is solved.
And then simulating the selected engineering design through a design division module, dividing the selected and divided engineering design into a plurality of smaller designs, and deploying the divided designs into a plurality of FPGAs of one or a plurality of development boards.
In the process, when the segmentation tool of the design segmentation module segments the selected engineering design, a user can remotely input the segmentation requirement to the segmentation tool through the Ethernet, so that the user can remotely select the segmentation requirement through the segmentation tool, the operation is more convenient, and remote control can be performed.
The netlist file called by the top module mainly comprises a top simulation Verilog file and netlist files corresponding to each FPGA.
The Verilog file comprises the input and output of the whole selected engineering design and the calling incidence relation between each FPGA, and the netlist file corresponding to each FPGA is the result of the whole engineering design after being divided and deployed to each FPGA.
It is further explained that the segmentation simulation and judgment module judges the simulation result after the simulation, if the simulation result is correct, the correct simulation result is output, the operation is continued, otherwise, the simulation is stopped.
The invention can divide and deploy a certain larger engineering design or a certain larger module in the engineering design to a plurality of FPGAs, can select to generate a simulation top module, and uses the generated simulation top module to carry out simulation so as to confirm the correct running state of the divided design, thereby ensuring that a user can confirm the correctness of the running state of the design and the division result of the design when designing a chip design with high capacity and high complexity based on a plurality of FPGAs, and accelerating the development flow of SOC products.
As shown in fig. 1, the present invention also discloses a FPGA prototype verification development board segmentation simulation method, which comprises:
selecting an engineering design to be segmented through a segmentation selection module according to user requirements;
according to the result selected by the segmentation selection module, the design segmentation module utilizes a segmentation tool to segment the engineering design selected for segmentation into a plurality of smaller designs, and the designs obtained by segmentation are deployed into a plurality of FPGAs of one or a plurality of development boards;
and the top module calls the netlist file of each small-design FPGA after being divided, adopts the division simulation and judgment module according to the called netlist file of each small-design FPGA after being divided, directly simulates the small-design FPGA after being divided, and verifies the accuracy of a simulation result.
The specific working process is the same as that of the segmentation simulation system, and is not described herein again.
By adopting the segmentation simulation method in the technical scheme, after a certain large engineering design or a certain large module in the engineering design can be segmented and deployed to a plurality of FPGAs, a simulation top module can be selected to be generated, and the generated simulation top module is used for simulation so as to confirm the correct running state of the segmented design, so that a user can confirm the correctness of the running state of the design and the segmentation result of the design when designing a chip design with high capacity and high complexity based on a plurality of FPGAs, and the development flow of SOC products is accelerated.
The storage medium of the invention has stored thereon a computer program which, when executed by a processor, implements the method described above. The storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic disk, U-disk, memory card, or optical disk.
The terminal comprises a processor and a memory.
The memory is for storing a computer program. Preferably, the memory comprises: various media that can store program codes, such as ROM, RAM, magnetic disk, U-disk, memory card, or optical disk.
The processor is connected with the memory and is used for executing the computer program stored in the memory so as to enable the terminal to execute the method.
Preferably, the Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; the integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (9)
1. An FPGA prototype verification development board segmentation simulation system is characterized by comprising:
the segmentation selection module is used for selecting an engineering design needing segmentation according to the user requirement;
a design partitioning module for partitioning the engineering design selected for partitioning into a plurality of smaller designs by using a partitioning tool according to a result selected by the partitioning selection module, and deploying the partitioned design into a plurality of FPGAs of one or more development boards;
the top layer module is used for calling the netlist file of each smaller designed FPGA after being divided;
and the segmentation simulation and judgment module is used for generating the top layer module, directly simulating the segmented smaller design according to the netlist file called by the top layer module, and verifying the accuracy of the simulation result.
2. The FPGA prototyping development board segmentation simulation system of claim 1 wherein the volume of the engineering design selected by the segmentation selection module is greater than the volume of the standard engineering design.
3. The FPGA prototype verification development board segmentation simulation system according to claim 1, wherein the netlist file called by the top module mainly comprises a Verilog file of the top simulation and netlist files corresponding to each FPGA.
4. The FPGA prototyping development board segmentation simulation system of claim 3 wherein the Verilog file contains the input and output of the entire selected engineering design and the call associations between each FPGA.
5. The FPGA prototype verification development board segmentation simulation system according to claim 1, wherein the segmentation simulation and judgment module judges the simulation result after the simulation, and if the simulation result is correct, outputs the correct simulation result, continues to run, otherwise stops the simulation.
6. The FPGA prototyping development board segmentation simulation system of claim 1 wherein the segmentation tool of the design segmentation module is configured to remotely input the segmentation requirements to the segmentation tool via Ethernet when segmenting the selected engineering design.
7. A FPGA prototype verification development board segmentation simulation method is characterized by comprising the following steps:
selecting an engineering design to be segmented through a segmentation selection module according to user requirements;
according to the result selected by the segmentation selection module, the design segmentation module utilizes a segmentation tool to segment the engineering design selected for segmentation into a plurality of smaller designs, and the designs obtained by segmentation are deployed into a plurality of FPGAs of one or a plurality of development boards;
and generating a top layer module by the segmentation simulation and judgment module, calling the netlist file of each small-design FPGA after segmentation by the top layer module, directly simulating the small-design FPGA after segmentation by adopting the segmentation simulation and judgment module according to the called netlist file of each small-design FPGA after segmentation, and verifying the accuracy of a simulation result.
8. A storage medium on which a computer program is stored which, when being executed by a processor, carries out the method as claimed in claim 7.
9. A terminal, comprising: a processor and a memory;
the memory is used for storing a computer program;
the processor is configured to execute the computer program stored by the memory to cause the terminal to perform the method of claim 7.
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Cited By (4)
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| CN112329368A (en) * | 2020-10-30 | 2021-02-05 | 盛科网络（苏州）有限公司 | Method, apparatus and storage medium for automatically adjusting a segmentation scheme |
| CN113255263A (en) * | 2021-06-07 | 2021-08-13 | 上海国微思尔芯技术股份有限公司 | Particle band dividing method, device, computer equipment and storage medium |
| CN113255265A (en) * | 2021-06-07 | 2021-08-13 | 上海国微思尔芯技术股份有限公司 | Segmentation and verification method, device, electronic equipment and storage medium |
| CN113504463A (en) * | 2021-07-02 | 2021-10-15 | 芯启源(上海)半导体科技有限公司 | Probe signal multiplexing method in FPGA prototype verification |
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Cited By (6)
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| CN113504463A (en) * | 2021-07-02 | 2021-10-15 | 芯启源(上海)半导体科技有限公司 | Probe signal multiplexing method in FPGA prototype verification |
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