CN110988661B - FPGA prototype verification development board time division analysis system, method, medium and terminal - Google Patents
FPGA prototype verification development board time division analysis system, method, medium and terminal Download PDFInfo
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- CN110988661B CN110988661B CN201911247014.2A CN201911247014A CN110988661B CN 110988661 B CN110988661 B CN 110988661B CN 201911247014 A CN201911247014 A CN 201911247014A CN 110988661 B CN110988661 B CN 110988661B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31702—Testing digital circuits including elements other than semiconductor transistors, e.g. biochips, nanofabrics, mems, chips with magnetic elements
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
Abstract
The invention discloses a time division analysis system, a time division analysis method, a time division analysis medium and a time division analysis terminal of an FPGA prototype verification development board, wherein the system comprises: the clock constraint module is used for detecting whether a constraint file exists in the current development board engineering design or not so as to constrain a clock; the board-level design time division analysis module is used for providing a bidirectional dialog box for a user, determining whether the time division characteristics of a design object meet requirements, generating an analysis report, and performing different display processing for displaying and distinguishing whether the current project uses Time Division Multiplexing (TDM); the analysis report module is used for judging whether the board-level design time division analysis module generates an analysis report or not and generating a corresponding analysis report according to the generated analysis report, so that a user can conveniently analyze various time division characteristics, performance parameters and evaluation results in the design for the user to refer, judge whether the time division characteristics, performance parameters and evaluation results meet the requirements or not and effectively solve the problems provided by the background technology.
Description
Technical Field
The invention relates to the technical field of development boards, in particular to a time division analysis system, a time division analysis method, a time division analysis medium and a time division analysis terminal for verifying the board level design of a development board by an FPGA prototype.
Background
The development board is a circuit board used for developing an embedded system, and comprises a series of hardware components such as a central processing unit, a memory, an input device, an output device, a data path/bus, an external resource interface and the like. The development board is generally customized by an embedded system developer according to development requirements, and can also be researched and designed by a user. The development board is used for a beginner to know and learn hardware and software of the system, and meanwhile, a part of the development board also provides a basic integrated development environment, software source codes, a hardware schematic diagram and the like. Common development boards include 51, ARM, FPGA and DSP development boards.
In the development and design process of the development board, the time division characteristics and various performances of the current development board need to be evaluated to determine the subsequent processing operation.
Disclosure of Invention
In order to overcome the defects of the prior art scheme, the invention provides a time division analysis system, a time division analysis method, a time division analysis medium and a time division analysis terminal of an FPGA prototype verification development board, so that a user can conveniently analyze various time division characteristics, performance parameters and evaluation results in design, the performance parameters and the evaluation results are provided for the user to refer, whether the time division characteristics meet the requirements or not is judged, and the problems provided by the background art can be effectively solved.
The technical scheme adopted by the invention for solving the technical problem is as follows:
a time division analysis system of an FPGA prototype verification development board comprises:
the clock constraint module is used for detecting whether a constraint file exists in the current development board engineering design or not so as to constrain the clock;
the board-level design time division analysis module is used for providing a bidirectional dialog box for a user, determining whether the time division characteristics of a design object meet requirements, generating an analysis report, and performing different display processing for displaying and distinguishing whether the current project uses Time Division Multiplexing (TDM);
and the analysis report module is used for judging whether the board-level design time division analysis module generates an analysis report or not and generating a corresponding analysis report according to the generated analysis report.
Further, the analysis report module judges whether the current development board project uses TDM time division multiplexing, when TDM is used, an analysis result is output according to the analysis report, and when TDM is not used, the TDM time division ratio is output.
Further, the board-level design time division analysis module acquires time division information of each design object in the development board engineering design, compares the time division information with a set standard library, judges whether the time division information meets the requirement or not, and outputs an analysis result.
Further, the standard library adopts a universal standard of time division information in development board engineering design, and can also be manually set by a user.
Further, if the clock constraint module detects that the constraint clock does not exist, the clock constraint module reports an error and prompts a user to set clock constraint, otherwise, the function cannot run normally, and when the constraint clock exists, the subsequent processing process is performed normally.
A time division analysis method for an FPGA prototype verification development board comprises the following steps:
detecting whether a constraint file exists in the current development board engineering design through a clock constraint module to constrain a clock, if so, normally performing subsequent processing, otherwise, stopping operation;
a board-level design time division analysis module is utilized to provide a bidirectional dialog box for a user, so as to determine whether the time division characteristics of a design object meet requirements, generate an analysis report, and make different display treatments for displaying and distinguishing according to whether the current project uses time division multiplexing TDM;
and the analysis report module is used for judging whether the board-level design time division analysis module generates an analysis report or not, generating a corresponding analysis report according to the generated analysis report and finally obtaining a time division analysis result.
Further, when the analysis report module uses the TDM aiming at the user development board engineering design, the time division analysis result is directly output according to the analysis report, otherwise, the time division ratio of the TDM is output.
The invention provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the method described above.
The present invention provides a terminal, including: a processor and a memory; the memory is used for storing a computer program; the processor is configured to execute the computer program stored in the memory to cause the terminal to perform the above-mentioned method.
Compared with the prior art, the invention has the beneficial effects that:
the time division analysis system of the invention determines whether the time division characteristics of the development board engineering design of the user meet the requirements through the board-level design time division analysis module, judges and sets the clock constraint by using the clock constraint module, and finally completes the time division analysis according to the corresponding analysis report produced by using the analysis report module, so that the user can conveniently analyze various time division characteristics in the design and judge whether the time division characteristics meet the requirements, thereby accelerating the chip design development process.
Drawings
FIG. 1 is a schematic view of the overall working process of the time-division analysis system of the present invention;
fig. 2 is a schematic diagram of the overall work flow of the time division analysis method of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the present invention provides a time division analysis system for an FPGA prototype verification development board, comprising:
the clock constraint module is used for detecting whether a constraint file exists in the current development board engineering design or not so as to constrain the clock;
the board-level design time division analysis module is used for providing a bidirectional dialog box for a user, determining whether the time division characteristics of a design object meet requirements, generating an analysis report, and performing different display processing for displaying and distinguishing whether the current project uses Time Division Multiplexing (TDM);
after the board-level design time division analysis module outputs an analysis report, a user can judge whether each engineering design object meets the time division requirement of chip design only according to the output information.
And the analysis report module is used for judging whether the board-level design time division analysis module generates an analysis report or not and generating a corresponding analysis report according to the generated analysis report.
In the whole scheme, whether the time division characteristics of a user development board engineering design object meet requirements or not is determined through the board-level design time division analysis module, the clock constraint module is used for judging and setting clock constraints, and finally time division analysis is completed according to the analysis report produced by the analysis report decomposition module, so that the user can conveniently judge whether the time division characteristics meet the requirements or not, and the chip design development process is accelerated.
The analysis report module judges whether the current development board project uses TDM time division multiplexing, when using TDM, the analysis result is output according to the analysis report, when not using TDM, the TDM time division ratio is output.
The board-level design time division analysis module acquires time division information of each design object in the development board engineering design, compares the time division information with a set standard library to judge whether the time division information meets the requirement or not, and outputs an analysis result.
The standard library adopts a universal standard of time division information in development board engineering design, and can also be manually set by a user.
If the clock constraint module detects that the constraint clock does not exist, the clock constraint module reports an error and prompts a user to set clock constraint, otherwise, the function cannot run normally, when the constraint clock exists, the subsequent processing process is carried out normally, the clock constraint module detects the constraint clock, and the clock book in the analyzed engineering design object is ensured to exist, so that the analysis process is more accurate and reliable.
As shown in fig. 2, the present invention further provides a time division analysis method for an FPGA prototype verification development board, including:
detecting whether a constraint file exists in the current development board engineering design through a clock constraint module to constrain a clock, if so, performing normal subsequent processing, otherwise, stopping running;
a board-level design time division analysis module is used for providing a bidirectional dialog box for a user, determining whether the time division characteristics of a design object meet requirements or not, generating an analysis report, and performing different display processing for displaying and distinguishing whether the current project uses Time Division Multiplexing (TDM) or not;
and the analysis report module is used for judging whether the board-level design time division analysis module generates an analysis report or not, generating a corresponding analysis report according to the generated analysis report and finally obtaining a time division analysis result.
And when the analysis report module uses the TDM aiming at the user development board engineering design, directly outputting a time division analysis result according to the analysis report, otherwise, outputting the time division ratio of the TDM.
The invention determines whether the time division characteristics of the development board engineering design of the user meet the requirements or not through the board-level design time division analysis module, judges and sets the clock constraint by using the clock constraint module, and finally produces the corresponding analysis report according to the analysis report utilization module to complete time division analysis, so that the user can conveniently analyze various time division characteristics in the design and judge whether the time division characteristics meet the requirements or not, thereby accelerating the chip design development process.
The storage medium of the invention has stored thereon a computer program which, when executed by a processor, implements the method described above. The storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic disk, U-disk, memory card, or optical disk.
The terminal comprises a processor and a memory.
The memory is for storing a computer program. Preferably, the memory comprises: various media that can store program codes, such as ROM, RAM, magnetic disk, U-disk, memory card, or optical disk.
The processor is connected to the memory for executing the computer program stored in the memory 32 to make the terminal execute the above-mentioned method.
Preferably, the Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (7)
1. An FPGA prototype verification development board time division analysis system is characterized by comprising:
the clock constraint module is used for detecting whether a constraint file exists in the current development board engineering design or not so as to constrain the clock;
the board-level design time division analysis module is used for providing a bidirectional dialog box for a user, determining whether the time division characteristics of a design object meet requirements, generating an analysis report, and performing different display processing for displaying and distinguishing whether the current project uses Time Division Multiplexing (TDM);
the analysis report module is used for judging whether the board-level design time division analysis module generates an analysis report or not and generating a corresponding analysis report according to the generated analysis report;
the analysis report module judges whether the current development board project uses TDM time division multiplexing, when using TDM, the analysis result is output according to the analysis report, when not using TDM, the TDM time division ratio is output.
2. The FPGA prototype verification development board time division analysis system according to claim 1, wherein the board level design time division analysis module obtains time division information of each design object in the development board engineering design, compares the time division information with a set standard library to judge whether the time division information meets requirements, and outputs an analysis result.
3. The FPGA prototype verification development board time division analysis system according to claim 2, wherein the standard library adopts a universal standard of time division information in development board engineering design, and can be manually set by a user.
4. The FPGA prototype verification development board time-division analysis system according to claim 1, wherein the clock constraint module reports an error and prompts a user to set a clock constraint if it detects that the constraint clock does not exist, otherwise the function cannot normally run, and when the constraint clock exists, the subsequent processing is normally performed.
5. A time division analysis method for an FPGA prototype verification development board is characterized by comprising the following steps:
detecting whether a constraint file exists in the current development board engineering design through a clock constraint module to constrain a clock, if so, normally performing subsequent processing, otherwise, stopping operation;
a board-level design time division analysis module is used for providing a bidirectional dialog box for a user, determining whether the time division characteristics of a design object meet requirements or not, generating an analysis report, and performing different display processing for displaying and distinguishing whether the current project uses Time Division Multiplexing (TDM) or not;
the analysis report module is used for judging whether the board-level design time division analysis module generates an analysis report or not, generating a corresponding analysis report according to the generated analysis report and finally obtaining a time division analysis result;
and when the analysis report module uses the TDM aiming at the user development board engineering design, directly outputting a time division analysis result according to the analysis report, otherwise, outputting the time division ratio of the TDM.
6. A storage medium on which a computer program is stored which, when being executed by a processor, carries out the method as claimed in claim 5.
7. A terminal, comprising: a processor and a memory;
the memory is used for storing a computer program;
the processor is configured to execute the computer program stored by the memory to cause the terminal to perform the method recited in claim 5.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1818912A (en) * | 2005-02-11 | 2006-08-16 | 思尔芯(上海)信息科技有限公司 | Scalable reconfigurable prototyping system and method |
| CN101038578A (en) * | 2007-03-29 | 2007-09-19 | 上海大学 | Image digital information parameter controlling parts selection secondary development plate based on audio/video embedded development platform |
| US7454729B1 (en) * | 2005-11-16 | 2008-11-18 | Altera Corporation | Method and system for validating testbench |
| CN101975919A (en) * | 2010-09-19 | 2011-02-16 | 王振国 | Method and device for detecting circuit state |
| CN103729490A (en) * | 2012-10-15 | 2014-04-16 | 飞思卡尔半导体公司 | Mixed signal IP core prototype design system |
| CN104755896A (en) * | 2012-06-29 | 2015-07-01 | 英瑞杰汽车系统研究公司 | Device for measuring the pressure of gas in pollution control or energy storage system |
| CN104793699A (en) * | 2015-01-04 | 2015-07-22 | 北京君正集成电路股份有限公司 | Development board card |
| CN105915780A (en) * | 2015-02-23 | 2016-08-31 | 三星电子株式会社 | Image signal processor and devices including the same |
| CN108572312A (en) * | 2018-04-12 | 2018-09-25 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | SoC chip test method, device, system and SoC chip test witness plate |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8724665B2 (en) * | 2009-07-20 | 2014-05-13 | Synopsys, Inc. | Pseudo-synchronous time division multiplexing |
| CN108337582B (en) * | 2017-12-29 | 2021-01-29 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Time division multiplexing switching system based on field programmable gate array |
| CN108377172A (en) * | 2018-02-26 | 2018-08-07 | 广东小天才科技有限公司 | A kind of time-division and frequency division multiplexing circuit evolving method and device |
-
2019
- 2019-12-09 CN CN201911247014.2A patent/CN110988661B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1818912A (en) * | 2005-02-11 | 2006-08-16 | 思尔芯(上海)信息科技有限公司 | Scalable reconfigurable prototyping system and method |
| US7454729B1 (en) * | 2005-11-16 | 2008-11-18 | Altera Corporation | Method and system for validating testbench |
| CN101038578A (en) * | 2007-03-29 | 2007-09-19 | 上海大学 | Image digital information parameter controlling parts selection secondary development plate based on audio/video embedded development platform |
| CN101975919A (en) * | 2010-09-19 | 2011-02-16 | 王振国 | Method and device for detecting circuit state |
| CN104755896A (en) * | 2012-06-29 | 2015-07-01 | 英瑞杰汽车系统研究公司 | Device for measuring the pressure of gas in pollution control or energy storage system |
| CN103729490A (en) * | 2012-10-15 | 2014-04-16 | 飞思卡尔半导体公司 | Mixed signal IP core prototype design system |
| CN104793699A (en) * | 2015-01-04 | 2015-07-22 | 北京君正集成电路股份有限公司 | Development board card |
| CN105915780A (en) * | 2015-02-23 | 2016-08-31 | 三星电子株式会社 | Image signal processor and devices including the same |
| CN108572312A (en) * | 2018-04-12 | 2018-09-25 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | SoC chip test method, device, system and SoC chip test witness plate |
Non-Patent Citations (2)
| Title |
|---|
| 基于ARM SoC 的FPGA原型验证;杨安;《电子器件》;20110630;第34卷(第3期);第247-251页 * |
| 芯片测试平台中的FPGA时序分析及芯片接口测试方法研究;鲍瑞;《中国优秀硕士学位论文全文数据库 信息科技辑》;20140115;I135-292 * |
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