CN114328045A - I2C debugging method, system and device for BMC and computer readable storage medium - Google Patents
I2C debugging method, system and device for BMC and computer readable storage medium Download PDFInfo
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Abstract
The application discloses a method, a system and a device for I2C debugging of BMC and a computer readable storage medium, comprising: acquiring an I2C topology of BMC to be simulated; virtualizing a virtual I2C link corresponding to the I2C topology by utilizing a QEMU HW interface according to the I2C topology and pre-stored hardware characteristic information of an I2C device; and transmitting simulated hardware information to the BMC through the virtual I2C link, and monitoring and debugging the BMC. The I2C topology of the virtual BMC of QEMU is utilized to simulate the hardware information output of the mainboard, so that the I2C function of the BMC is tested in advance before the mainboard is manufactured, the BMC test and the mainboard research and development are carried out in parallel, and the research and development efficiency of the server is improved.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a method, a system and a device for I2C debugging of BMC (baseboard management controller) and a computer readable storage medium.
Background
With the rapid development of the internet industry, the demands of various industries on the server are higher and higher, and the updating and updating of the server are accelerated, so that the latest server can be provided more quickly, and the enterprise can be helped to seize the market first opportunity.
In the existing server, there is a small system, i.e., BMC (Baseboard Management Controller), independent of the CPU, and the BMC provides monitoring and Management for the server. In the research and development process of the server, the mainboard of the server needs to be used for 3 months to 1 year in different time through the processes of hardware design, board beating and verification, the BMC research and development process is relatively quick and is usually completed earlier than the mainboard research and development, the mainboard needs to be returned after the BMC is completed to start verification, the BMC cannot be tested before the mainboard is researched and developed, the BMC is a blocking point in the research and development process of the server, and the research and development efficiency of the server is influenced.
Therefore, an I2C (Inter-Integrated Circuit, I2C bus) debugging method of the BMC is required to improve the development efficiency of the server.
Disclosure of Invention
In view of the above, the present invention is directed to a method, a system, a device and a computer readable storage medium for I2C debugging of BMC, which can improve the efficiency of server development. The specific scheme is as follows:
an I2C debugging method for BMC comprises the following steps:
acquiring an I2C topology of BMC to be simulated;
virtualizing a virtual I2C link corresponding to the I2C topology by utilizing a QEMU HW interface according to the I2C topology and pre-stored hardware characteristic information of an I2C device;
and transmitting simulated hardware information to the BMC through the virtual I2C link, and monitoring and debugging the BMC.
Optionally, the process of transmitting the simulated hardware information to the BMC through the virtual I2C link includes:
through the virtual I2C link, a high-low signal during data transmission in the I2C link is simulated by using a software delay mode according to communication frequency, and simulated hardware information is transmitted to the BMC.
Optionally, the virtualizing a virtual I2C link corresponding to the I2C topology by using a HW interface of QEMU according to the I2C topology and pre-stored hardware characteristic information of the I2C device includes:
obtaining expansion chips used by each level in an I2C link according to the I2C topology;
acquiring channel information of each expansion chip by using the hardware characteristic information;
and virtualizing a virtual I2C link corresponding to the I2C topology by utilizing a HW interface of QEMU according to the channel information of the I2C topology, the expansion chip and the expansion chip.
Optionally, the virtualizing, according to the I2C topology, the channel information of the expansion chip, and the HW interface of the QEMU, the virtual I2C link corresponding to the I2C topology includes:
according to the I2C topology, confirming an I2C communication pin used for carrying out I2C communication in the BMC;
confirming the number of I2C channels of each expansion chip according to the expansion chips and the channel information of the expansion chips;
connecting an I2C communication pin of the BMC with the extension chips of all levels and channels of the extension chips according to the I2C topology to obtain an I2C circuit diagram;
and virtualizing the I2C circuit diagram by using a HW interface of QEMU, and virtualizing the virtual I2C link.
The invention also discloses an I2C debugging system of BMC, comprising:
the topology acquisition module is used for acquiring the I2C topology of the BMC to be simulated;
the link virtualization module is used for virtualizing a virtual I2C link corresponding to the I2C topology by utilizing a QEMU (hardware-assisted hardware) interface according to the I2C topology and pre-stored hardware characteristic information of the I2C device;
and the debugging module is used for transmitting simulated hardware information to the BMC through the virtual I2C link and monitoring and debugging the BMC.
Optionally, the debugging module is specifically configured to simulate, through the virtual I2C link, a high-low signal during data transmission in the I2C link in a software delay manner according to the communication frequency, and transmit simulated hardware information to the BMC.
Optionally, the link virtual module includes:
the chip confirmation submodule is used for acquiring the expansion chips used by each level in the I2C link according to the I2C topology;
the channel confirmation submodule is used for acquiring the channel information of each expansion chip by utilizing the hardware characteristic information;
and the link virtualization submodule is used for virtualizing a virtual I2C link corresponding to the I2C topology by utilizing a HW interface of the QEMU according to the channel information of the I2C topology, the expansion chip and the expansion chip.
Optionally, the link virtual sub-module includes:
a pin confirmation unit, configured to confirm an I2C communication pin for I2C communication in the BMC according to the I2C topology;
the channel confirming unit is used for confirming the number of the I2C channels of each expansion chip according to the expansion chips and the channel information of the expansion chips;
the circuit virtual unit is used for connecting the I2C communication pin of the BMC with the expansion chips of all levels and the channels of the expansion chips according to the I2C topology to obtain an I2C circuit diagram;
and the link virtualization unit is used for virtualizing the I2C circuit diagram by using a HW interface of the QEMU and virtualizing the virtual I2C link.
The invention also discloses an I2C debugging device for BMC, which comprises:
a memory for storing a computer program;
a processor for executing the computer program to implement the I2C debugging method of BMC as described above.
The invention also discloses a computer readable storage medium, which stores a computer program, and the computer program realizes the I2C debugging method of BMC when being executed by a processor.
In the invention, the I2C debugging method for BMC comprises the following steps: acquiring an I2C topology of BMC to be simulated; virtualizing a virtual I2C link corresponding to the I2C topology by utilizing a QEMU HW interface according to the I2C topology and pre-stored hardware characteristic information of an I2C device; and transmitting simulated hardware information to the BMC through the virtual I2C link, and monitoring and debugging the BMC.
According to the invention, the I2C topology of the QEMU virtual BMC is utilized to simulate the hardware information output of the mainboard, so that the I2C function of the BMC is tested in advance before the mainboard is manufactured, the concurrent execution of BMC test and mainboard research and development is realized, and the research and development efficiency of the server is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic flowchart of an I2C debugging method for BMC according to an embodiment of the present invention;
FIG. 2 is a schematic flowchart of another I2C debugging method for BMC according to the embodiment of the invention;
fig. 3 is a schematic structural diagram of an I2C debugging system of a BMC according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses an I2C debugging method for BMC, which comprises the following steps:
s11: the I2C topology of the BMC that needs to be simulated is obtained.
Specifically, before a server motherboard corresponding to the virtual-simulated BMC is manufactured, the design scheme of the server motherboard is known, and therefore, the I2C topology between the BMC and the server motherboard is known in the future, and therefore, if an I2C simulation test is performed on the BMC in advance, the I2C topology of the BMC needs to be acquired.
The I2C topology records how many pins and how many pins the BMC needs to use for I2C communication, also records the type of the expansion chip that needs to be used, how many I2C needs to be expanded, and the connection relationship between the I2C pins of the BMC and the expansion chip and the pins between the expansion chip, that is, the I2C circuit diagram of each level.
S12: and virtualizing a virtual I2C link corresponding to the I2C topology by utilizing the HW interface of QEMU according to the I2C topology and the pre-stored hardware characteristic information of the I2C device.
Specifically, although the model of the expansion chip is described in the I2C topology, the specific pin condition of the expansion chip is not described, and therefore, the pin condition of the expansion chip needs to be determined by using the pre-stored hardware characteristic information of the I2C device, and then the I2C topology is combined, so as to virtualize the link of the I2C, a virtual I2C link corresponding to the I2C topology can be virtualized by using a HW interface of QEMU (virtual operating system simulator), and the virtual I2C link can accurately simulate the transmission condition of signals between each level, thereby giving a possibility of virtual testing.
S13: and transmitting the simulated hardware information to the BMC through the virtual I2C link, and monitoring and debugging the BMC.
Specifically, the design of the server motherboard is known, so that the BMC monitors the hardware devices by using the I2C link, and therefore, the QEMU virtualizes the hardware information of each hardware on the server, transmits simulated hardware information to the BMC by using the virtual I2C link with the virtual number, and debugs the BMC by judging whether the BMC can accurately monitor, record and display the input hardware information, so as to finally ensure that the BMC can effectively monitor and complete the debugging.
Therefore, the embodiment of the invention simulates the hardware information output of the mainboard by using the I2C topology of the QEMU virtual BMC, so that the I2C function of the BMC is tested in advance before the mainboard is manufactured, the parallel execution of the BMC test and the mainboard research and development is realized, and the research and development efficiency of the server is improved.
The embodiment of the invention discloses a specific I2C debugging method for BMC, and compared with the previous embodiment, the embodiment further explains and optimizes the technical scheme. Referring to fig. 2, specifically:
s21: acquiring an I2C topology of BMC to be simulated;
s22: and acquiring the expansion chips used by each level in the I2C link according to the I2C topology.
Specifically, according to the flag in the I2C topology, determining the expansion chip used by each level in the I2C link, it can be understood that, in order to expand the I2C link of the BMC, a multi-level expansion chip is used for expansion, for example, as shown in table 1, where the first level is an I2C0 pin of the BMC, the second level is an expansion through a 9548 chip, the third level is an expansion through a 9555 expansion chip, and the fourth level is directly connected to a hardware device, so that the third level expansion chip obtains hardware information stored in the fourth level and feeds the hardware information back to the BMC step by step. Of course, the BMC may use more than one I2C pin to construct the I2C communication link, each pin may be similarly configured as a multi-level extension as shown in Table 1.
TABLE 1
S23: and acquiring channel information of each expansion chip by using the hardware characteristic information.
Specifically, information such as specific pin data of each expansion chip is described in the hardware characteristic information, for example, based on table 1, a 9548 expansion chip may expand 8 channels, each channel may be connected to a 9555 expansion chip, and the 9555 expansion chip may be connected to a hardware device through external 6 IO channels, for example, a memory, as shown in table 1, one BMC pin may be connected to one 9548 expansion chip, one 9548 expansion chip may be connected to 8 9555 expansion chips, and in total, 48 channels may be expanded to be connected to the hardware device, and of course, specific expansion conditions may be set according to actual application needs, which is not limited herein.
S24: and virtualizing a virtual I2C link corresponding to the I2C topology by utilizing the HW interface of the QEMU according to the channel information of the I2C topology, the expansion chip and the expansion chip.
Specifically, after channel information of the I2C topology, the expansion chip, and the expansion chip is confirmed, the information may be integrated, and a virtual I2C link corresponding to the I2C topology is virtualized by using the HW interface of the QEMU.
Further specific virtual processes may further include S241 to S244; wherein,
s241: according to the I2C topology, the I2C communication pin in the BMC for I2C communication is validated.
Specifically, since the BMC includes a plurality of pins, it is first confirmed what the number of pins is for I2C communication, so as to draw a circuit diagram later.
S242: confirming the number of I2C channels of each expansion chip according to the expansion chips and the channel information of the expansion chips;
s243: and connecting the I2C communication pin of the BMC with the extension chip of each hierarchy and the channel of the extension chip according to the I2C topology to obtain an I2C circuit diagram.
Specifically, after channels of an I2C communication pin of the BMC, an expansion chip of each hierarchy and an expansion chip are obtained, a simple I2C circuit diagram can be drawn according to an I2C topology, and the circuit diagram is only a connection relationship between each chip and the pin and does not have an analog data transmission function.
S244: virtual I2C links are virtualized using QEMU's HW interface virtual I2C wiring diagram.
Specifically, after the I2C circuit diagram is obtained, the actual operating data loaded by the content drawn in the I2C circuit diagram can be virtualized by using the QEMU HW interface, so as to obtain a virtual I2C link capable of simulating signal transmission.
Specifically, the hardware characteristic information may also be fused into the I2C topology, so that the I2C topology includes complete I2C link information, and at that time, virtualization can be performed only according to the I2C topology. In addition, the hardware characteristic information can be updated, and all devices required by simulation can be covered. It can be understood that the hardware on the simulation motherboard to which the I2C link is finally connected may also be stored in a separate file, may be input by a user, and may know the information of the hardware to be simulated by the simulation by reading, or may be integrated into the I2C topology, and may know the hardware to be simulated and the connection relationship with the I2C link by reading the I2C topology.
S25: and simulating a high-low signal during data transmission in the I2C link through the virtual I2C link in a software delay mode according to the communication frequency, and transmitting simulated hardware information to the BMC.
Specifically, the pulling up and down of I2C can be simulated by software delay according to the communication frequency, for example, by using a frequency of 100MHz, when a virtual I2C setting is called, 1 or 0 is returned at a speed of 1/100MHz, so as to simulate pulling up and pulling down.
Correspondingly, the embodiment of the present invention further discloses an I2C debugging system for BMC, as shown in fig. 3, the system includes:
the topology acquisition module 11 is configured to acquire an I2C topology of the BMC to be simulated;
the link virtualization module 12 is configured to virtualize a virtual I2C link corresponding to the I2C topology by using a HW interface of QEMU according to the I2C topology and pre-stored hardware characteristic information of the I2C device;
and the debugging module 13 is configured to transmit the simulated hardware information to the BMC through the virtual I2C link, and monitor and debug the BMC.
Therefore, the embodiment of the invention simulates the hardware information output of the mainboard by using the I2C topology of the QEMU virtual BMC, so that the I2C function of the BMC is tested in advance before the mainboard is manufactured, the parallel execution of the BMC test and the mainboard research and development is realized, and the research and development efficiency of the server is improved.
Specifically, the debugging module 13 is specifically configured to simulate, through the virtual I2C link, a high-low signal during data transmission in the I2C link in a software delay manner according to the communication frequency, and transmit simulated hardware information to the BMC.
Specifically, the link virtual module 12 may include: the chip confirming submodule, the channel confirming submodule and the link virtual submodule are arranged in the chip; wherein,
the chip confirmation submodule is used for acquiring the expansion chips used by each level in the I2C link according to the I2C topology;
the channel confirmation submodule is used for acquiring the channel information of each expansion chip by utilizing the hardware characteristic information;
and the link virtualization submodule is used for virtualizing a virtual I2C link corresponding to the I2C topology by utilizing the HW interface of the QEMU according to the channel information of the I2C topology, the expansion chip and the expansion chip.
Specifically, the link virtual sub-module may include: the device comprises a pin confirmation unit, a channel confirmation unit, a line virtual unit and a link virtual unit; wherein,
the pin confirmation unit is used for confirming an I2C communication pin used for carrying out I2C communication in the BMC according to the I2C topology;
the channel confirming unit is used for confirming the number of the I2C channels of each expansion chip according to the expansion chips and the channel information of the expansion chips;
the circuit virtual unit is used for connecting an I2C communication pin of the BMC with the expansion chips of all levels and channels of the expansion chips according to the I2C topology to obtain an I2C circuit diagram;
and the link virtual unit is used for virtualizing a virtual I2C link by utilizing a HW interface virtual I2C circuit diagram of QEMU.
In addition, the embodiment of the invention also discloses an I2C debugging device for BMC, which comprises:
a memory for storing a computer program;
a processor for executing a computer program to implement the I2C debugging method of BMC as described above.
In addition, the embodiment of the invention also discloses a computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and when being executed by a processor, the computer program realizes the I2C debugging method of the BMC.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The technical content provided by the present invention is described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the above description of the examples is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A I2C debugging method of BMC is characterized by comprising the following steps:
acquiring an I2C topology of BMC to be simulated;
virtualizing a virtual I2C link corresponding to the I2C topology by utilizing a QEMU HW interface according to the I2C topology and pre-stored hardware characteristic information of an I2C device;
and transmitting simulated hardware information to the BMC through the virtual I2C link, and monitoring and debugging the BMC.
2. The I2C debugging method of the BMC of claim 1, wherein the process of transmitting emulated hardware information to the BMC over the virtual I2C link comprises:
through the virtual I2C link, a high-low signal during data transmission in the I2C link is simulated by using a software delay mode according to communication frequency, and simulated hardware information is transmitted to the BMC.
3. The I2C debugging method for BMC of claim 1 or 2, wherein the virtualizing a virtual I2C link corresponding to the I2C topology by using QEMU HW interface according to the I2C topology and pre-stored hardware characteristic information of I2C device comprises:
obtaining expansion chips used by each level in an I2C link according to the I2C topology;
acquiring channel information of each expansion chip by using the hardware characteristic information;
and virtualizing the virtual I2C link corresponding to the I2C topology by utilizing a HW interface of QEMU according to the channel information of the I2C topology, the expansion chip and the expansion chip.
4. The I2C debugging method for BMC according to claim 3, wherein the virtualizing the virtual I2C link corresponding to the I2C topology by QEMU HW interface according to the channel information of the I2C topology, the extended chip and the extended chip comprises:
according to the I2C topology, confirming an I2C communication pin used for carrying out I2C communication in the BMC;
confirming the number of I2C channels of each expansion chip according to the expansion chips and the channel information of the expansion chips;
connecting an I2C communication pin of the BMC with the extension chips of all levels and channels of the extension chips according to the I2C topology to obtain an I2C circuit diagram;
and virtualizing the I2C circuit diagram by using a HW interface of QEMU, and virtualizing the virtual I2C link.
5. An I2C debugging system for BMC, comprising:
the topology acquisition module is used for acquiring the I2C topology of the BMC to be simulated;
the link virtualization module is used for virtualizing a virtual I2C link corresponding to the I2C topology by utilizing a QEMU (hardware-assisted hardware) interface according to the I2C topology and pre-stored hardware characteristic information of the I2C device;
and the debugging module is used for transmitting simulated hardware information to the BMC through the virtual I2C link and monitoring and debugging the BMC.
6. The I2C debugging system of BMC of claim 5, wherein the debugging module is specifically configured to simulate, via the virtual I2C link, a pull-up/pull-down signal during data transmission in an I2C link according to a communication frequency by using software latency, and transmit simulated hardware information to the BMC.
7. The I2C debugging system of BMC according to claim 5 or 6, wherein the link virtualization module comprises:
the chip confirmation submodule is used for acquiring the expansion chips used by each level in the I2C link according to the I2C topology;
the channel confirmation submodule is used for acquiring the channel information of each expansion chip by utilizing the hardware characteristic information;
and the link virtualization submodule is used for virtualizing a virtual I2C link corresponding to the I2C topology by utilizing a HW interface of the QEMU according to the channel information of the I2C topology, the expansion chip and the expansion chip.
8. The I2C debugging method for BMC of claim 7, wherein the link virtualization submodule comprises:
a pin confirmation unit, configured to confirm an I2C communication pin for I2C communication in the BMC according to the I2C topology;
the channel confirming unit is used for confirming the number of the I2C channels of each expansion chip according to the expansion chips and the channel information of the expansion chips;
the circuit virtual unit is used for connecting the I2C communication pin of the BMC with the expansion chips of all levels and the channels of the expansion chips according to the I2C topology to obtain an I2C circuit diagram;
and the link virtualization unit is used for virtualizing the I2C circuit diagram by using a HW interface of the QEMU and virtualizing the virtual I2C link.
9. An I2C debugging device for BMC, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the I2C debugging method of BMC of any of claims 1 to 4.
10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, implements the I2C debugging method of BMC according to any of claims 1 to 4.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115080191A (en) * | 2022-08-18 | 2022-09-20 | 苏州浪潮智能科技有限公司 | Method, device and equipment for managing I2C link and readable medium |
| CN115617616A (en) * | 2022-11-03 | 2023-01-17 | 宁畅信息产业(北京)有限公司 | Operation monitoring method, device and equipment of server FRU and storage medium |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115080191A (en) * | 2022-08-18 | 2022-09-20 | 苏州浪潮智能科技有限公司 | Method, device and equipment for managing I2C link and readable medium |
| CN115080191B (en) * | 2022-08-18 | 2023-01-06 | 苏州浪潮智能科技有限公司 | Method, device, equipment and readable medium for managing I2C link |
| WO2024036857A1 (en) * | 2022-08-18 | 2024-02-22 | 苏州元脑智能科技有限公司 | I2c link management method and apparatus, device, and nonvolatile readable medium |
| CN115617616A (en) * | 2022-11-03 | 2023-01-17 | 宁畅信息产业(北京)有限公司 | Operation monitoring method, device and equipment of server FRU and storage medium |
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