CN112118166B - Multi-chip networking system, method and application - Google Patents
Multi-chip networking system, method and application Download PDFInfo
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- CN112118166B CN112118166B CN202010983482.2A CN202010983482A CN112118166B CN 112118166 B CN112118166 B CN 112118166B CN 202010983482 A CN202010983482 A CN 202010983482A CN 112118166 B CN112118166 B CN 112118166B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40032—Details regarding a bus interface enhancer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40169—Flexible bus arrangements
- H04L12/40176—Flexible bus arrangements involving redundancy
- H04L12/40182—Flexible bus arrangements involving redundancy by using a plurality of communication lines
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
Abstract
The invention provides a multi-chip networking system which comprises n chips, wherein n is an integer larger than 2. The networking system comprises interconnection interfaces positioned on each chip, and the interconnection interfaces between adjacent chips are connected through cables to form interconnection nodes. The networking system further comprises a software platform, the software platform is connected with the interconnection nodes, and the software platform is used for identifying the position information of the interconnection nodes in real time and identifying interconnection information of interconnection communication success or failure between chips at two ends of the interconnection nodes in real time. The software platform is also in communication connection with the control terminal, and the control terminal is used for reading and displaying the position information and the interconnection information sent by the software platform in real time. The interconnection interfaces are arranged on the chips and connected through cables, the connection has unified specifications, the production and purchase period is shortened, the project process is accelerated, the software control terminal has a convenient positioning and debugging means, the operation is simple and convenient, the maintenance is easy, and the project is easy to adjust, copy and migrate integrally.
Description
Technical Field
The invention belongs to the field of electronic communication, relates to a network technology, and particularly relates to a multi-chip networking system, a method and application.
Background
In the integrated circuit design process, a verification stage is required to verify the design with more complex functions. Generally, the verification of the user in the integrated circuit design process is performed by cutting the designed integrated circuit into a plurality of parts and then placing the parts in each chip of the multichip system for verification. When a multi-chip system runs, one networking among a plurality of chips is needed to complete the construction of the system of the whole design.
At present, a multichip system usually selects XCVR (transceiver device), LVDS (RS-644 bus interface) networking for communication, or uses some general-purpose bus for communication, and if the communication is low speed, several chips can be connected by flying wires for communication. The interconnection communication is not convenient for networking of a super large number, and can not collect the state information of mutually interconnected chips in real time.
Therefore, it is necessary to design a networking method that can be applied to a multichip system.
Disclosure of Invention
The invention aims to provide a multi-chip networking system, a multi-chip networking method and application.
The technical scheme for realizing the purpose of the invention is as follows:
the invention provides a multi-chip networking system which comprises n chips, wherein n is an integer larger than 2. The networking system comprises interconnection interfaces positioned on each chip, and the interconnection interfaces between adjacent chips are connected through cables to form interconnection nodes.
The networking system further comprises a software platform, the software platform is connected with the interconnection nodes, and the software platform is used for identifying the position information of the interconnection nodes in real time and identifying interconnection information of interconnection communication success or failure between chips at two ends of the interconnection nodes in real time.
The software platform is also in communication connection with the control terminal, and the control terminal is used for reading and displaying the position information and the interconnection information sent by the software platform in real time.
According to the invention, the interconnection interfaces are arranged on the chips and connected through cables, so that the connection has a uniform specification, the production and purchase period is reduced, the project process is accelerated, the software control terminal has a convenient positioning and debugging means, the operation is simple and convenient, the maintenance is easy, and the project is easy to adjust, copy and migrate integrally.
Furthermore, a high-speed signal bus and a low-speed signal bus are packaged in the interconnection interface. The high-speed and low-speed signal buses are packaged together to realize single specification interconnection, and convenience can be provided for production, manufacturing and raw material purchasing. The high-speed signal bus is used for transmitting clocks and effective communication data in an interconnection system, and the low-speed signal bus is mainly used for transmitting low-speed control signals and data required by some low-speed interfaces.
Furthermore, the software platform comprises a power supply control module, a clock reading and writing module, a chip configuration module, a system identification module and a positioning module. The power supply control module is used for controlling the networking system to be powered on and powered off and controlling the networking system to be in a working state. The clock reading and writing module is used for adjusting the clock frequency of the networking system and reading back the clock frequency in real time. The chip configuration module is used for configuring the associated logic of the networking system, so that the networking system can complete specific functions. The identification module is used for identifying success or failure of communication connection of the interconnection nodes, and the positioning module is used for positioning the interconnection nodes.
Further, the communication connection between the software platform and the control terminal comprises a wired connection or a wireless connection. For example, the wired connection is interconnected with the control terminal through the USB port to complete communication; the wireless connection realizes the interconnection between the software platform and the control terminal by connecting the network port of the networking system to the exchange equipment through the wireless communication interface; it should be noted that, in addition to the two manners of the USB port and the wireless communication interface, other manners of wired connection or wireless connection may be selected for communication according to actual situations.
Furthermore, an analysis module is arranged in the control terminal and used for analyzing the reason of interconnection failure of the interconnection nodes.
The invention also provides a multi-chip networking method, which adopts the multi-chip networking system to carry out networking on a plurality of chips and comprises the following steps:
s101, respectively connecting interconnection interfaces of adjacent chips of n chips by cables to form a plurality of interconnection nodes, wherein the interconnection nodes are numbered as 1, 2, 3, … … and n-1 in sequence;
s102, starting a software platform and a control terminal, establishing communication connection between the software platform and each interconnection node in the step S101, and establishing communication connection between the software platform and the control terminal;
s103, identifying interconnection information and position information of communication connection of each interconnection node in real time by the software platform, and sending the interconnection information and the position information to the control terminal;
and S104, the control terminal reads and displays the interconnection information and the position information in real time.
Further, the method further includes step S105, when the control terminal receives the interconnection information of the interconnection communication failure, the control terminal locates the interconnection node according to the position information, and analyzes the reason of the interconnection communication failure. The interconnection system has a certain space to store interconnection handshake information of interconnection nodes, the positioning module is mainly used for reading the space and then returning, for the cable problem, the clock problem and the like all correspond to an error code, and corresponding solutions can be found according to the corresponding error code, such as cable replacement and clock adjustment.
The multi-chip networking system and method can be applied in the verification stage of integrated circuit design.
Compared with the prior art, the invention has the beneficial effects that: according to the invention, the interconnection interfaces are arranged on the chips and connected through cables, so that the connection has a uniform specification, the production and purchase period is reduced, the project process is accelerated, the software control terminal has a convenient positioning and debugging means, the operation is simple and convenient, the maintenance is easy, and the project is easy to adjust, copy and migrate integrally.
Drawings
In order to more clearly illustrate the technical solution of the embodiment of the present invention, the drawings used in the description of the embodiment will be briefly introduced below. It should be apparent that the drawings in the following description are only for illustrating the embodiments of the present invention or technical solutions in the prior art more clearly, and that other drawings can be obtained by those skilled in the art without any inventive work.
FIG. 1 is a diagram of a multi-chip networking system according to the present invention.
Detailed Description
The invention is further described below in conjunction with specific embodiments, and the advantages and features of the invention will become more apparent as the description proceeds. These examples are illustrative only and do not limit the scope of the present invention in any way. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention, and that such changes and modifications may be made without departing from the spirit and scope of the invention.
In the description of the present embodiments, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to a number of indicated technical features. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the invention, the meaning of "a plurality" is two or more unless otherwise specified.
Example 1:
the present embodiment provides a multi-chip networking system, which is described by taking an application in a verification stage of an integrated circuit design as an example. In this embodiment, the multi-chip networking system includes n chips, where n is an integer greater than 2, and as shown in fig. 1, the chips are numbered as chip 1, chip 2, chip 3, … …, and chip n in this order.
As shown in fig. 1, the networking system includes interconnection interfaces on each chip, and the interconnection interfaces between adjacent chips are linked by cables to form interconnection nodes. Specifically, the chip 1 and the chip 2 are linked through a cable to form an interconnection node 1; the chip 2 and the chip 3 are connected through a cable to form an interconnection node 2; and by analogy, the chip n-1 is connected with the chip n through a cable to form an interconnection node n-1.
Furthermore, a high-speed signal bus and a low-speed signal bus are packaged in the interconnection ports on each chip. In this embodiment, can realize single specification interconnection with two kinds of signal bus encapsulation of high speed and low speed together, can both provide convenient to manufacturing and raw materials purchase. The high-speed signal bus is used for transmitting clocks and effective communication data in an interconnection system, and the low-speed signal bus is mainly used for transmitting low-speed control signals and data required by some low-speed interfaces.
As shown in fig. 1, the networking system further includes a software platform, where the software platform is linked with the interconnection node, and the software platform is configured to identify, in real time, location information of the interconnection node and identify, in real time, interconnection information of success or failure of interconnection communication between chips at two ends of the interconnection node.
Furthermore, the software platform comprises a power supply control module, a clock reading and writing module, a chip configuration module, a system identification module and a positioning module. The power supply control module is used for controlling the networking system to be powered on and powered off and controlling the networking system to be in a working state. The clock reading and writing module is used for adjusting the clock frequency of the networking system and reading back the clock frequency in real time. The chip configuration module is used for configuring the associated logic of the networking system, so that the networking system can complete specific functions. The identification module is used for identifying success or failure of communication connection of the interconnection nodes, and the positioning module is used for positioning the interconnection nodes.
As shown in fig. 1, the software platform is further in communication connection with a control terminal, and the control terminal is used for reading and displaying the position information and the interconnection information sent by the software platform in real time.
Further, the communication connection between the software platform and the control terminal comprises a wired connection or a wireless connection. For example, the wired connection is interconnected with the control terminal through the USB port to complete communication; the wireless connection realizes the interconnection between the software platform and the control terminal by connecting the network port of the networking system to the exchange equipment through the wireless communication interface; it should be noted that, besides the two manners of USB port and wireless communication interface, other manners of wired connection or wireless connection may be selected for communication according to actual situations.
Furthermore, an analysis module is arranged in the control terminal and used for analyzing the reason of interconnection failure of the interconnection nodes.
Example 2:
the embodiment provides a multi-chip networking method, which is to adopt the multi-chip networking system of the embodiment 1 to perform networking on a plurality of chips, and comprises the following steps:
s101, respectively connecting interconnection interfaces of adjacent chips of n chips by cables to form a plurality of interconnection nodes, wherein the interconnection nodes are numbered as 1, 2, 3, … … and n-1 in sequence;
s102, starting a software platform and a control terminal, establishing communication connection between the software platform and each interconnection node in the step S101, and establishing communication connection between the software platform and the control terminal;
s103, identifying interconnection information and position information of communication connection of each interconnection node in real time by the software platform, and sending the interconnection information and the position information to the control terminal;
and S104, the control terminal reads and displays the interconnection information and the position information in real time.
Further, in the networking process of the n chips, there may be a problem of networking failure due to various factors, and in order to timely find and locate the position of the interconnection node where networking fails, the multi-chip networking method further includes S105, that is, S105, when the control terminal receives interconnection information of interconnection communication failure, the control terminal locates the interconnection node according to the position information, and analyzes the reason of interconnection communication failure. Because the interconnection system has a certain space for storing interconnection handshake information of interconnection nodes, the positioning module is mainly used for reading the space and then returning, so that corresponding solutions are adopted, such as: when networking failure is caused by a cable problem, a clock problem and the like correspond to one error code, and corresponding solutions such as cable replacement and clock adjustment can be found according to the corresponding error code.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (7)
1. A multi-chip networking system comprises n chips, wherein n is an integer greater than 2, and is characterized in that: the networking system comprises interconnection interfaces positioned on each chip, and the interconnection interfaces between adjacent chips are linked through cables to form interconnection nodes;
the networking system further comprises a software platform, wherein the software platform is linked with the interconnection nodes and is used for identifying the position information of the interconnection nodes in real time and identifying interconnection information of success or failure of interconnection communication between the chips at two ends of the interconnection nodes in real time;
the software platform is also in communication connection with a control terminal, and the control terminal is used for reading and displaying the position information and the interconnection information sent by the software platform in real time.
2. The multi-chip networking system of claim 1, wherein: and a high-speed signal bus and a low-speed signal bus are packaged in the interconnection interface.
3. The multi-chip networking system of claim 1, wherein: the software platform comprises a power supply control module, a clock reading and writing module, a chip configuration module, a system identification module and a positioning module;
the power supply control module is used for controlling the networking system to be powered on and powered off and monitoring the working state of the networking system;
the clock read-write module is used for adjusting the clock frequency of the networking system and reading back the clock frequency in real time;
the chip configuration module is used for configuring the associated logic of the networking system;
the identification module is used for identifying success or failure of communication connection of the interconnection node, and the positioning module is used for positioning the interconnection node.
4. The multi-chip networking system of claim 1, wherein: the communication connection between the software platform and the control terminal comprises wired connection or wireless connection.
5. The multi-chip networking system of claim 1, wherein: and an analysis module is arranged in the control terminal and used for analyzing the reason of interconnection failure of the interconnection nodes.
6. A multi-chip networking method, which adopts the multi-chip networking system of any one of claims 1 to 5 to perform networking on a plurality of chips, and is characterized in that: the method comprises the following steps:
s101, respectively connecting interconnection interfaces of adjacent chips of n chips by cables to form a plurality of interconnection nodes, wherein the interconnection nodes are numbered as 1, 2, 3, … … and n-1 in sequence;
s102, starting a software platform and a control terminal, establishing communication connection between the software platform and each interconnection node in the step S101, and establishing communication connection between the software platform and the control terminal;
s103, identifying interconnection information and position information of communication connection of each interconnection node in real time by the software platform, and sending the interconnection information and the position information to the control terminal;
and S104, the control terminal reads and displays the interconnection information and the position information in real time.
7. The method of claim 6, wherein: and S105, when the control terminal receives the interconnection information of interconnection communication failure, the control terminal positions the interconnection node according to the position information and analyzes the reason of the interconnection communication failure.
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| CN112394300B (en) * | 2021-01-20 | 2021-04-09 | 上海国微思尔芯技术股份有限公司 | Networking detection method and system |
| CN113157630B (en) * | 2021-04-26 | 2023-11-21 | 上海思尔芯技术股份有限公司 | Networking detection method and networking detection system of programmable logic array system |
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