CN113157630B - Networking detection method and networking detection system of programmable logic array system - Google Patents
Networking detection method and networking detection system of programmable logic array system Download PDFInfo
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Abstract
The application provides a networking detection method and a networking detection system of a programmable logic array system, which belong to the field of integrated circuits and specifically comprise the steps of obtaining a universal test file distributed to a programmable logic device; numbering the programmable logic device based on preset interconnection information; resetting a configurable transceiver of the programmable logic device according to the numbering information and the data verification; controlling the configurable transceiver to generate a position sequence code and controlling the configurable transceiver to store the position sequence code; controlling the configurable transceiver to send random data to the upper computer and sending the random data to the configurable transceiver of another programmable logic device for verification; and when the data information verification is judged to be correct, the upper computer is controlled to acquire the interconnection state information of all the programmable logic devices according to the position sequence code, and a hardware description file is generated according to the interconnection state information. By the processing scheme of the application, the failed cable or port can be accurately positioned.
Description
Technical Field
The application relates to the field of integrated circuits, in particular to a networking detection method and a networking detection system of a programmable logic array system.
Background
In programmable logic array (FPGA) -based SOC ASIC chip verification applications, it is often necessary to interconnect multiple FPGAs to meet high resource occupation requirements, typically by networking through high-speed transceivers or common IO services. In the actual operation flow of the connection cables, the relation and the number of the connection cables among different FPGAs are given according to the design topology requirement, specific sockets are allocated, the PIN positions (PIN positions) of the FPGA corresponding to the IO ports contained in the sockets are inquired, the PIN positions are allocated to FPGA PIN constraint files (design constraint and XDC), corresponding bit streams are generated according to the constraint file requirements to program and download the FPGA, and then the sockets are connected by cables to work.
However, when the system contains tens of FPGAs, and each FPGA contains tens of wires, if there is a quality or contact problem on tens of FPGAs, the system cannot normally operate, so that it is necessary to verify the interconnection performance of the interconnection system, and it is necessary to locate the cable or FPGA pins with problems.
For detecting the interconnection of cables, two methods, namely visual detection of appearance and measurement and detection of a universal meter are generally adopted. Visual inspection of the appearance is used for detecting whether cable interconnection, lead breakage and the like exist between connectors. The universal meter detection is to measure the two ends of the cable connection connector by using an ohmic gear of the universal meter, and the connection resistance value of the universal meter is smaller than 0.5 omega. The visual appearance detection operation is simple, but the accuracy cannot be ensured; the universal meter detects the accuracy height, but needs manual measurement, and to the high connector that adopts the bottom paster mode of integrated level moreover, the pin does not all expose in the outside, and the operation degree of difficulty that the signal was got to the gauge needle of universal meter is big. Moreover, after the detection is finished, for the networking condition of the whole system, a hardware description file (topview HDL file) of a top layer (topview) which can be automatically generated cannot be obtained immediately at present, and a user needs to manually write out the file according to a measurement result, which is time-consuming and labor-consuming.
Disclosure of Invention
Therefore, in order to overcome the defects of the prior art, the application provides a networking detection method and a networking detection system of a programmable logic array system, which can accurately position a cable or a port with faults and can automatically generate design constraint files (Design constraint SDC/XDC) and HDL top-level system board level description files of industry standards.
In order to achieve the above object, the present application provides a networking detection method of a programmable logic array system, including: acquiring a universal test file distributed to the programmable logic device through a controller of the programmable logic device, wherein the universal test file carries a receiving address and data verification of the programmable logic device, and the programmable logic array comprises a controller and a plurality of programmable logic devices, wherein the programmable logic device comprises a device body and a plurality of configurable transceivers, and each configurable transceiver carries out cross interconnection on the programmable logic device through a configuration circuit; numbering the programmable logic devices based on preset interconnection information, and issuing the numbering information of the programmable logic devices to the corresponding programmable logic devices through an upper computer control port; resetting a configurable transceiver of the programmable logic device according to the numbering information and the data verification; controlling the configurable transceiver to generate a position sequence code corresponding to the configurable transceiver, and controlling the configurable transceiver to store the position sequence code; controlling the configurable transceiver to transmit the random data to a configurable transceiver of another programmable logic device for verification; and when the data information verification is judged to be correct, controlling the upper computer to acquire interconnection state information of all the programmable logic devices according to the position sequence code, and generating hardware description files corresponding to all the programmable logic devices according to the interconnection state information.
In one embodiment, the resetting the configurable transceiver of the programmable logic device according to the number information and the data check includes: resetting a transmitting end of the configurable transceiver according to the number information and the data verification, and generating an idle identifier; transmitting the idle identifier to a receiving end of the configurable transceiver, wherein the receiving end resets according to the idle identifier; the transmitting end generates an alignment code and transmits the pair Ji Ma to the receiving end, and the receiving end corrects the data generated subsequently according to the alignment code.
In one embodiment, the controlling the configurable transceiver to send the random data to a configurable transceiver of another programmable logic device for verification includes: controlling a transmitting end of the configurable transceiver to generate a group of specific position sequence codes for a short time, and transmitting the position sequence codes to a receiving end of the configurable transceiver; and controlling the receiving end of the configurable transceiver to be in a state of waiting for a specific sequence, and once the position sequence code sent by the upper computer is received, storing the position sequence code into a register corresponding to the configurable transceiver for reading by the upper computer.
In one embodiment, the controlling the configurable transceiver to send random data to the host computer and send the random data to the configurable transceiver of another programmable logic device for verification includes: when the transmitting end transmits the position sequence code, the transmitting end is controlled to change the data transmitting state, and the transmitting end is controlled to transmit random data to the receiving end of the configurable transceiver of the other programmable logic device; the receiving end of the configurable transceiver of the other programmable logic device is controlled to receive and store data information so as to verify the data information and the random data, and each configurable transceiver is provided with a two-way handshake single-ended control signal which is used for verifying whether the random data of the sending end is sent by the random data or whether the data information is received by the receiving end.
In one embodiment, the controlling the configurable transceiver to send the random data to a configurable transceiver of another programmable logic device for verification includes: when the transmitting end transmits the position sequence code, the transmitting end is controlled to change the data transmitting state, and the transmitting end is controlled to transmit random data to a receiving end of a configurable transceiver of another programmable logic device in preset time; and controlling the receiving end of the configurable transceiver of the other programmable logic device to receive and store the transmitted data information at preset time so as to verify the data information and the random data.
The application provides a networking detection system based on a configurable transceiver, which comprises: the programmable logic arrays comprise a controller and a plurality of programmable logic devices, the programmable logic devices comprise a device body and a plurality of configurable transceivers, the programmable logic arrays are connected through the configurable transceivers, and the programmable logic devices are connected with the controller through a special connection port for downloading configuration and a bidirectional port for control; and the upper computer is used for controlling the programmable logic array through the controller, wherein each configurable transceiver is used for carrying out cross interconnection on the programmable logic devices through cross cables, and the networking detection system is used for implementing the networking detection method.
In one embodiment, the upstream ports of the controller and the upper computer are any one of an ethernet port, an RS-485 port and a USB port.
In one embodiment, the upper computer is a computer, a server, an industrial personal computer or an MCU.
Compared with the prior art, the application has the advantages that: the networking system of the programmable logic array system is detected by utilizing the characteristics of the configuration circuit, so that automation of cable interconnection detection of the development board is realized, manual measurement is not needed in the whole process, the limitation of the installation environment of the development board is avoided, the speed is high, the accuracy is high, meanwhile, all interconnection conditions can be adapted only by one test file, a cable or a port with faults can be accurately positioned, an industry standard design constraint file (Design constraint SDC/XDC) and an HDL top-layer system board level description file can be automatically generated, the communication rate is improved, less interconnection line requirements (which are beneficial to reducing the number of interconnection lines and the networking complexity) are needed for realizing the same bandwidth, and the networking mode does not have the risk of multiple driving.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a networking detection system in an embodiment of the present application;
FIG. 2 is a flow chart of a networking detection method according to an embodiment of the present application;
FIG. 3 is an interconnection matrix diagram of a networking detection method in an embodiment of the application;
FIG. 4 is a schematic diagram of a synchronization flow of a networking detection method according to an embodiment of the present application;
fig. 5 is a schematic diagram of a synchronization flow of a networking detection method according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, apparatus may be implemented and/or methods practiced using any number and aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that aspects may be practiced without these specific details.
As shown in fig. 1, an embodiment of the present application provides a networking detection system 100 of a programmable logic array system, which includes a host computer 10 and a plurality of programmable logic arrays 20.
The upper computer 10 may be a computer (PC), a server, an industrial personal computer, or an MCU.
The programmable logic array 20 includes a controller 21 and a plurality of programmable logic devices 22.
The controller 21 and the programmable logic device 22 are connected by a dedicated connection port for download configuration and a bidirectional port for control. The controller 21 is connected to the host computer through an upstream port. The upper computer 10 controls the programmable logic array 20 through the controller 21, and the controller 21 controls the programmable logic device 22. In one embodiment, the upstream ports of the controller and the upper computer are any one of an Ethernet port, an RS-485 port and a USB port.
The programmable logic device 22 includes a device body 221 and a plurality of configurable transceivers 222. The programmable logic devices 22 are connected by a configurable transceiver 222. Each of the configurable transceivers 222 interconnects the programmable logic devices 22 through cross-wires. The programmable logic device 22 may contain 12 or 24 configurable transceivers 222. Configurable transceiver 222 may be a GTX high speed transceiver for FPGA, a GTH high speed transceiver, or the like. The configurable transceiver 222 may be comprised of 4 transceiver channels that are connected together by providing cross-cable connections between dedicated sockets and the high-speed transceiver when interconnected.
As shown in fig. 2, an embodiment of the present application provides a networking detection method based on a configurable transceiver, which is applied to the networking detection system shown in fig. 1, and includes the following steps:
step 201, a universal test file allocated to the programmable logic device is obtained through a controller of the programmable logic device, the universal test file carries a receiving address and data verification of the programmable logic device, the programmable logic array comprises a controller and a plurality of programmable logic devices, the programmable logic device comprises a device body and a plurality of configurable transceivers, and each configurable transceiver carries out cross interconnection on the programmable logic device through a cross cable.
The generic test file is a generic test file generated for the programmable logic device in advance according to the configurable transceiver settings. The universal test file carries the received address and data verification of the programmable logic device. The programmable logic device may be a chip such as an FPGA, ASIC, or the like. When the programmable logic device is an FPGA, the universal test file may be an FPGA universal test bit. Each FPGA can carry out interconnection detection on each connection port of all high-speed transceivers only by downloading the same bit, and the step can be carried out by each FPGA automatically through a configuration circuit in a connected controller when the circuit is started. Different FPGAs realize cross connection of cables through cross cables.
Step 202, numbering the programmable logic devices based on preset interconnection information, and issuing the numbering information of the programmable logic devices to the corresponding programmable logic devices through an upper computer control port.
After the FPGA is powered on and downloaded, the FPGA does not know the position of the FPGA in the system, so that the upper computer can number the programmable logic device based on preset interconnection information and send the number information of the programmable logic device to the corresponding programmable logic device through an upper computer control port.
And 203, resetting the configurable transceiver of the programmable logic device according to the number information and the data verification.
The programmable logic device resets the configurable transceiver of the programmable logic device based on the numbering information and the data verification. The same global reset or the method of the side handshake synchronization can be used by the FPGA of the same networking system as the starting point of the system synchronization, and all the FPGA in the system are synchronously reset. When the method based on global reset synchronization is used, the transmitting ends of all high-speed transceivers of all FPGAs in the networking are reset in advance, idle codes are transmitted and used for resetting the receiving ends, and the receiving ends reset after a period of time after the transmitting ends of the high-speed transceivers GT are reset successfully, namely, the matching between the transmitting ends and the receiving ends is completed; when the method of the synchronous of the side handshake is used, the sending end resets in advance, and after the resetting is finished, the receiving end is controlled by the side signal to reset again so as to complete the matching between the sending end and the receiving end.
Step 204, controlling the configurable transceiver to generate a position sequence code corresponding to the configurable transceiver, and controlling the configurable transceiver to store the position sequence code.
The upper computer controls the configurable transceiver to generate a position sequence code corresponding to the configurable transceiver, and controls the configurable transceiver to store the position sequence code. After receiving the corresponding position sequence code, the receiving end of the configurable transceiver writes the position sequence code into a corresponding register for reading by a host computer.
Step 205, control the configurable transceiver to send random data to the configurable transceiver of another programmable logic device for verification.
The upper computer controls the configurable transceiver to transmit the random data and transmits the random data to the configurable transceiver of another programmable logic device for verification. All the receiving ends of the configurable transceiver will be in the data receiving and transmitting verification state, and error counting is carried out on the data which are not matched with the receiving ends. Based on the special requirement of the high-speed signal, the receiving and transmitting end can use 8/10b or other codes to transmit, thereby ensuring the reliability of the data. The entire test verification process may be hours or days. The upper computer can acquire random data received and stored by the receiving ends of the configurable transceivers, and receive the random data sent by the sending ends of the configurable transceivers, and the upper computer compares and verifies the random data from two different sources to obtain data with unmatched receiving ends and count errors. In another embodiment, the random data may carry verification information, and the upper computer may determine the transmitted configurable transceiver and the received configurable information according to the received verification information, and perform verification according to the determined information.
And 206, when the data information verification is judged to be correct, controlling the upper computer to acquire the interconnection state information of all the programmable logic devices according to the position sequence code, and generating hardware description files corresponding to all the programmable logic devices according to the interconnection state information.
When the data information verification is judged to be correct, the upper computer is controlled to acquire the interconnection state information of all the programmable logic devices according to the position sequence code, and the PC end upper computer scans all ports of the FPGA through the controller to acquire the interconnection state information. And the upper computer constructs an interconnection matrix according to all the collected information, and verifies the interconnection of the system so as to avoid the situation of misplacement. The upper computer can traverse the register modules of all the FPGA high-speed transceivers to check the current position information (the position information read by the port without interconnection is the initial value 0 xFFFF), generate a corresponding interconnection matrix and verify the interconnection of the system so as to avoid the condition of misplacement. As shown in fig. 3, the scanned interconnection matrix is a block symmetric matrix, and specific interconnection information only needs a lower triangle block or an upper triangle block. The marked positions indicate that cable interconnection exists among connectors, and finally, hardware description files corresponding to all the programmable logic devices are output according to an interconnection matrix, wherein the hardware description files can be interconnection tables, networking XDC files and HDL files.
According to the networking detection method, the networking system of the configurable transceiver is detected by utilizing the characteristics of the configuration circuit, so that automation of cable interconnection detection of the development board is realized, manual measurement is not needed in the whole process, the limitation of the installation environment of the development board is avoided, the speed is high, the accuracy is high, meanwhile, all interconnection conditions can be adapted only by one test file, a failed cable or port can be accurately positioned, an industry standard design constraint file (Design constraint SDC/XDC) and an HDL top-layer system board level description file can be automatically generated, the communication rate is improved, the same bandwidth is realized, fewer interconnection line requirements (which are beneficial to reducing the number of interconnection lines and the networking complexity) are not needed, and the networking mode has no risk of multiple driving.
In one embodiment, resetting a configurable transceiver of a programmable logic device based on numbering information and data verification includes: resetting a transmitting end of the configurable transceiver according to the number information and the data verification, and generating an idle identifier; transmitting the idle mark to a receiving end of the configurable transceiver, and resetting the receiving end according to the idle mark; the transmitting end generates an alignment code and transmits the alignment code to the receiving end, and the receiving end corrects the data generated subsequently according to the alignment code.
When the method based on global reset synchronization is used, the transmitting ends of all high-speed transceivers of all FPGAs in the networking are reset in advance, and idle codes (idle marks at the moment are idle codes) are transmitted for resetting the receiving end, and the receiving end resets after a period of time after the transmitting ends of the high-speed transceivers GT are reset successfully, namely, the matching between the transmitting end and the receiving end is completed. When the method of the side handshake synchronization is used, the transmitting end resets in advance, and after the resetting is finished, the receiving end is controlled to reset again through the side signal (the idle mark at the moment is the side signal), so that the matching between the transmitting end and the receiving end is finished.
After the receiving end is reset, the transmitting end transmits an alignment code for a long enough time for the receiving end to perform data alignment. If the global reset synchronization-based method is used, the transmitting end needs to wait for a period of time to transmit the alignment code, where the period of time needs to be long enough to compensate for the inconsistency that may exist in the global reset. The aligned transceiving channels already have the ability to correctly transceive data.
In one embodiment, controlling the configurable transceiver to generate a position sequence code corresponding to the configurable transceiver and controlling the configurable transceiver to store the position sequence code includes: controlling a transmitting end of the configurable transceiver to generate a group of specific position sequence codes for a short period of time, and transmitting the position sequence codes to a receiving end of the configurable transceiver; the receiving end of the configurable transceiver is controlled to be in a state of waiting for a specific sequence, and once the position sequence code sent by the upper computer is received, the position sequence code is stored in a register corresponding to the configurable transceiver for reading by the upper computer.
In one embodiment, controlling the configurable transceiver to transmit random data to a configurable transceiver of another programmable logic device for verification includes: when the transmitting end transmits the position sequence code, the transmitting end is controlled to change the data transmitting state, and the transmitting end is controlled to transmit random data to the receiving end of the configurable transceiver of the other programmable logic device; the receiving end of the configurable transceiver of the other programmable logic device is controlled to receive and store the data information so as to verify the data information and the random data, and each configurable transceiver is provided with a two-way handshake single-ended control signal which is used for verifying whether the random data of the sending end sends the random data or verifying whether the receiving end receives the data information.
As shown in fig. 4, when handshaking the transceiving ends with the side single-ended control signal to synchronize both ends and acquire the position signal, this requires an additional auxiliary signal, and requires that each high-speed transceiver unit (two side single-ended control signals are required for each high-speed transceiver unit) is used instead of a single lane, so that the signal of each lane needs to be anded. Due to the addition of the auxiliary signal, the system can work more stably, and the reset logic at the moment is irrelevant to global reset.
In fig. 4, d1 represents a delay time length 1, and a transmitting end reset operation of the configurable transceiver is performed; d2 represents the delay time length 2, and the execution is that the receiving end of the configurable transceiver receives the idle identifier and the receiving end performs reset operation; d3 represents a delay time length 3, and the transmitting end of the configurable transceiver transmits an alignment code; d4 represents a delay time length 4, and the sending end of the configurable transceiver sends a position sequence code; d5 represents a delay time length 5, and the receiving end of the configurable transceiver of another programmable logic device receives the alignment code and aligns the data; d6 represents the time delay duration 6, performed is that the receiving end of the configurable transceiver receives the position sequence code, which is stored in the register; d7 represents a time delay duration 7, and the sending end of the configurable transceiver sends random data; d8 represents a time delay duration 8, and waits for the completion of the process of transmitting the position sequence by the transmitting end; d9 represents a delay time length 9, and the sending end of the configurable transceiver receives the acknowledgement signal sent by the receiving end and sends random data; d10 represents the delay time 10, and is performed by the receiving end of the configurable transceiver receiving the random data and storing it in a register for subsequent data verification and counting.
In one embodiment, controlling the configurable transceiver to transmit random data to a configurable transceiver of another programmable logic device for verification includes: when the transmitting end transmits the position sequence code, the transmitting end is controlled to change the data transmitting state, and the transmitting end is controlled to transmit random data to the receiving end of the configurable transceiver of the other programmable logic device at preset time; and controlling a receiving end of the configurable transceiver of the other programmable logic device to receive and store the transmitted data information at a preset time so as to verify the data information and the random data.
As shown in FIG. 5, when the global reset timing synchronization is based, the method can work stably as long as the time of global reset reaching each FPGA is ensured to be consistent, meanwhile, auxiliary signals are not needed, each channel works independently, and signal coupling is avoided among the channels. The test result is independent of the auxiliary pins, and the phenomenon that interconnection detection fails when the auxiliary pins have problems does not exist.
In fig. 5, d1 represents a delay time length 1, and a transmitting end reset operation of the configurable transceiver is performed; d2 represents the delay time length 2, and the execution is that the receiving end of the configurable transceiver receives the idle identifier and the receiving end performs reset operation; d3 represents a delay time length 3, and the transmitting end of the configurable transceiver transmits an alignment code; d4 represents a delay time length 4, and the sending end of the configurable transceiver sends a position sequence code; d5 represents a delay time length 5, and the receiving end of the configurable transceiver receives the alignment code and aligns the data; d6 represents the time delay duration 6, performed is that the receiving end of the configurable transceiver receives the position sequence code and stores it in a register; d7 represents a time delay duration 7, and the sending end of the configurable transceiver sends random data; d8 represents a time delay duration 8, and waits for the completion of the process of transmitting the position sequence by the transmitting end; d9 represents the delay time 9, and is performed by the receiving end of the configurable transceiver receiving the random data and storing it in a register for subsequent data verification and counting.
The present application is not limited to the above embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present application are intended to be included in the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (8)
1. The networking detection method of the programmable logic array system is characterized by comprising the following steps of:
acquiring a universal test file distributed to the programmable logic device through a configuration circuit of the programmable logic device, wherein the universal test file carries a receiving address and data verification of the programmable logic device, a programmable logic array comprises a controller and a plurality of programmable logic devices, the programmable logic device comprises a device body and a plurality of configurable transceivers, and each configurable transceiver interconnects the programmable logic devices through a cross cable;
numbering the programmable logic devices based on preset interconnection information, and issuing the numbering information of the programmable logic devices to the corresponding programmable logic devices through an upper computer control port;
resetting a configurable transceiver of the programmable logic device according to the numbering information and the data verification;
controlling the configurable transceiver to generate a position sequence code corresponding to the configurable transceiver, and controlling the configurable transceiver to store the position sequence code;
the configurable transceiver is controlled to send random data to a configurable transceiver of another programmable logic device so that the upper computer can compare and verify the random data from two different sources, the random data carries verification information, and the upper computer determines the sent configurable transceiver and the received configurable information according to the received verification information and verifies according to the determined information;
and when the random data verification is judged to be correct, controlling the upper computer to acquire interconnection state information of all the programmable logic devices according to the position sequence codes, and generating hardware description files corresponding to all the programmable logic devices according to the interconnection state information.
2. The networking detection method of claim 1, wherein resetting the configurable transceiver of the programmable logic device based on the numbering information and the data verification comprises:
resetting a transmitting end of the configurable transceiver according to the number information and the data verification, and generating an idle identifier;
transmitting the idle identifier to a receiving end of the configurable transceiver, wherein the receiving end resets according to the idle identifier;
the transmitting end generates an alignment code and transmits the pair Ji Ma to the receiving end, and the receiving end corrects the data generated subsequently according to the alignment code.
3. The networking detection method of claim 1, wherein controlling the configurable transceiver to generate a location sequence code corresponding to the configurable transceiver and controlling the configurable transceiver to store the location sequence code comprises:
controlling a transmitting end of the configurable transceiver to generate a group of specific position sequence codes for a short time, and transmitting the position sequence codes to a receiving end of the configurable transceiver;
and controlling the receiving end of the configurable transceiver to be in a state of waiting for a specific sequence, and once the position sequence code sent by the upper computer is received, storing the position sequence code into a register corresponding to the configurable transceiver for reading by the upper computer.
4. A networking detection method according to claim 3, wherein the controlling the configurable transceiver to send the random data to a configurable transceiver of another programmable logic device for verification comprises:
when the transmitting end transmits the position sequence code, the transmitting end is controlled to change the data transmitting state, and the transmitting end is controlled to transmit random data to the receiving end of the configurable transceiver of the other programmable logic device;
the receiving end of the configurable transceiver of the other programmable logic device is controlled to receive and store data information so as to verify the data information and the random data, and each configurable transceiver is provided with a two-way handshake single-ended control signal which is used for verifying whether the random data of the sending end is sent by the random data or whether the data information is received by the receiving end.
5. A networking detection method according to claim 3, wherein the controlling the configurable transceiver to send the random data to a configurable transceiver of another programmable logic device for verification comprises:
when the transmitting end transmits the position sequence code, the transmitting end is controlled to change the data transmitting state, and the transmitting end is controlled to transmit random data to a receiving end of a configurable transceiver of another programmable logic device in preset time;
and controlling the receiving end of the configurable transceiver of the other programmable logic device to receive and store the transmitted data information at preset time so as to verify the data information and the random data.
6. A configurable transceiver-based networking detection system, comprising:
the programmable logic arrays comprise a controller and a plurality of programmable logic devices, the programmable logic devices comprise a device body and a plurality of configurable transceivers, the programmable logic arrays are connected through the configurable transceivers, and the programmable logic devices are connected with the controller through a special connection port for downloading configuration and a bidirectional port for control; and
the upper computer controls the programmable logic array through the controller,
each configurable transceiver is used for carrying out cross interconnection on the programmable logic device through a cross cable, and the networking detection system is used for implementing the networking detection method according to any one of claims 1-5.
7. The networking detection system of claim 6, wherein the upstream ports of the controller and the upper computer are any one of an ethernet port, an RS-485 port and a USB port.
8. The networking detection system of claim 6, wherein the host computer is a computer, a server, an industrial personal computer, or an MCU.
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