CN117376221A - Automatic verification method and system for communication protocol - Google Patents
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- 238000012795 verification Methods 0.000 title claims abstract description 80
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/18—Protocol analysers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
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Abstract
The invention belongs to the technical field of communication, and particularly relates to an automatic verification method and system of a communication protocol. The automatic verification method of the communication protocol comprises the following steps: according to the target communication protocol, acquiring a corresponding time sequence combination from a preset communication protocol module library; acquiring preset test data and preset return data, generating an input excitation file by combining the preset test data and time sequence, and generating an expected result file by combining the preset return data and time sequence; reading an input excitation file by using a test host, sending an excitation signal to a slave to be tested, receiving a response signal returned by the slave to be tested, and storing the response signal in an actual result file; and comparing the actual result file with the expected result file for verification, if the verification is passed, the slave to be tested passes the test and the verification, and if the verification fails, the error position is positioned and displayed. The invention greatly lightens the working intensity of the testing process and the verification process by an automatic testing and verification mode.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to an automatic verification method and system of a communication protocol.
Background
With the development of embedded technology, more and more devices need to perform interconnection communication, and common communication protocols include I2C, SPI, UART and the like. The traditional verification method mainly comprises the steps of preparing test excitation, manually building a test platform (testbench) to verify a Design Under Test (DUT), and finally checking whether waveforms accord with expectations. The verification of the communication protocol often occupies a great deal of manpower and time resources in actual engineering practice, so a simple, efficient and reliable testing method is urgently needed.
Disclosure of Invention
Aiming at the technical problems of time and labor waste when verifying a design to be tested in an embedded technology, the invention aims to provide an automatic verification method and system of a communication protocol.
To solve the foregoing technical problem, a first aspect of the present invention provides an automatic verification method of a communication protocol, including:
according to a target communication protocol, acquiring a corresponding time sequence combination from a preset communication protocol module library, wherein the communication protocol module library is provided with a plurality of modules and corresponding time sequences thereof;
acquiring preset test data and preset return data, generating an input excitation file according to the preset test data and the time sequence combination, and generating an expected result file according to the preset return data and the time sequence combination;
reading the input excitation file by using a test host, sending an excitation signal to a slave to be tested, receiving a response signal returned by the slave to be tested, and storing the response signal in an actual result file;
and comparing the actual result file with the expected result file for verification, if the verification is passed, the slave to be tested passes the test and the verification, and if the verification is failed, the error position is positioned and displayed.
Optionally, in the method for automatically verifying a communication protocol as described above, the communication protocol module library is generated in the following manner:
obtaining a plurality of communication protocols, carrying out module division on each communication protocol to obtain a plurality of module lists, and establishing an association mapping relation between the communication protocols and the corresponding module lists, wherein the module lists are provided with a plurality of modules;
adding one or more time sequences of the modules into one or more corresponding time sequence lists, and establishing an association mapping relation between the modules and the corresponding time sequences to obtain a communication protocol module library comprising a plurality of module lists and a plurality of time sequence lists.
Optionally, in an automatic verification method of a communication protocol as described previously, the modules include, but are not limited to, one or more of a start, a restart, a slave address, a read flag bit, a write flag bit, a reply bit, a non-reply bit, a data byte, and an end.
Optionally, in the method for automatically verifying a communication protocol as described above, the target communication protocol and the communication protocol each include a standard protocol or a user-defined protocol.
Optionally, in the method of automatic verification of a communication protocol as described above, the standard protocol preferably includes, but is not limited to, one or more of I2C, SPI and UART.
Optionally, in the automatic verification method of the communication protocol as described above, the input stimulus file and the expected result file are generated separately using the same file generation script.
Optionally, in the method for automatically verifying a communication protocol as described above, the file generation script is a preset Python script.
Optionally, in the method for automatic verification of a communication protocol as described above, the verifying by comparing the actual result file and the expected result file includes:
and comparing the actual result file with the expected result file through a bit matcher, if the bit matching of the data can be realized, considering that the verification is passed, and otherwise, considering that the verification is failed.
To solve the foregoing technical problem, a second aspect of the present invention provides an automatic verification system of a communication protocol, including:
a test host;
the slave machine to be tested is provided with the same communication protocol as the test host;
the time sequence combination module is used for acquiring a corresponding time sequence combination from a preset communication protocol module library according to a target communication protocol;
the file generation module is used for acquiring preset test data and preset return data, generating an input excitation file according to the preset test data and the time sequence combination, and generating an expected result file according to the preset return data and the time sequence combination;
the testing module is used for reading the input excitation file by using the testing host, sending an excitation signal to the slave machine to be tested, receiving a response signal returned by the slave machine to be tested and storing the response signal in an actual result file;
and the verification module is used for verifying the actual result file and the expected result file by comparing, if the verification is passed, the slave to be tested passes the test and the verification, and if the verification is failed, the error position is positioned and displayed.
Optionally, in the automated verification system of the communication protocol as described above, further comprising:
and the bit matcher is used for comparing the actual result file with the expected result file.
Optionally, in the automated verification system of the communication protocol as described above, further comprising:
the division module is used for carrying out module division on the communication protocol to obtain a module list, establishing an association mapping relation between the communication protocol and the module list, adding one or more time sequences of the modules into the corresponding one or more time sequence lists, and establishing the association mapping relation between the modules and the corresponding time sequences.
The invention has the positive progress effects that:
1. the invention can perform normal communication function only by reasonably combining the modules through modularized division of the communication protocol, and has good expandability.
2. The invention can realize the automatic verification function, realize the verification of the bit matching stage, greatly improve the accuracy and the efficiency of chip verification and conveniently position the error position.
3. According to the invention, through a time sequence combination mode of the modules, the script is utilized to automatically generate the excitation file required by the test, manual handwriting is not needed, and the script is utilized to automatically generate the expected result file for verification, so that the working intensity of the test process and the verification process is greatly reduced.
Drawings
The present disclosure will become more apparent with reference to the accompanying drawings. It is to be understood that these drawings are solely for purposes of illustration and are not intended as a definition of the limits of the invention. In the figure:
FIG. 1 is a schematic flow chart of a method of the present invention;
FIG. 2 is a protocol timing diagram of an embodiment of the present invention;
FIG. 3 is a block diagram of the division of FIG. 2;
FIG. 4 is a frame construction diagram of one embodiment of the present invention;
FIG. 5 is a flow chart of an embodiment of the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which is to be read in light of the specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
In the description of the present invention, it should be noted that, for the azimuth terms, such as terms "outside," "middle," "inside," "outside," and the like, the azimuth and positional relationships are indicated based on the azimuth or positional relationships shown in the drawings, only for convenience in describing the present invention and simplifying the description, but not to indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and should not be construed as limiting the specific protection scope of the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features. Thus, the definition of "a first", "a second" feature may explicitly or implicitly include one or more of such feature, and in the description of the present invention, the meaning of "a number", "a number" is two or more, unless otherwise specifically defined.
Referring to fig. 1, an embodiment of the present invention provides an automatic verification method of a communication protocol, including the steps of:
s1, acquiring a time sequence combination: and acquiring a corresponding time sequence combination from a preset communication protocol module library according to the target communication protocol.
The communication protocol module library in the step is preset, a plurality of modules are arranged in the communication protocol module library, the modules are combined to form a communication protocol, different communication protocols are provided with different combinations of the modules, and each module corresponds to different time sequences. Therefore, the communication protocol module library is provided with a plurality of modules corresponding to different communication protocols and corresponding time sequences.
For different communication protocols, there may be one or more time sequences required for communication, so that the modules constituting the communication protocol have one or more time sequences correspondingly, and the time sequence combination obtained in this step also has one or more groups.
According to different target communication protocols, a plurality of corresponding modules and corresponding time sequences can be obtained from a communication protocol module library, and the time sequences are combined to obtain corresponding time sequence combinations.
In some embodiments, the library of communication protocol modules in step S1 is generated as follows:
the method comprises the steps of obtaining a communication protocol, carrying out module division on the communication protocol to obtain a module list, and establishing an association mapping relation between the communication protocol and the module list, wherein the module list is provided with a plurality of modules. Adding one or more time sequences of the modules into one or more corresponding time sequence lists, and establishing an association mapping relation between the modules and the corresponding time sequences to obtain a module list and one or more time sequence lists corresponding to the communication protocol.
The communication protocols are divided in the mode, and a communication protocol module library comprising a plurality of module lists and a plurality of time sequence lists is finally obtained.
In actual operation, the above generation manner of the embodiment may be adopted for different communication protocols, so as to obtain a module list and one or more timing lists corresponding to the communication protocol.
The generation mode of the embodiment may also be adopted for a new communication protocol according to the update of the actual application scenario, so as to obtain a module list and one or more time sequence lists corresponding to the new communication protocol, and update the communication protocol module library.
The communication protocol module library can be generally used for testing and verifying different slaves to be tested, and has good expandability.
In some embodiments, the modules include, but are not limited to, one or more of a start, a restart, a slave address, a read flag bit, a write flag bit, a reply bit, a non-reply bit, a data byte, and an end.
In some embodiments, the target communication protocol, the communication protocol, each comprise a standard protocol or a user-defined protocol.
The standard protocols preferably include, but are not limited to, one or more of I2C, SPI and UART.
The user-defined protocol is a protocol which is user-defined according to actual requirements. The embodiment is not limited to the standard protocol, can realize the division, test and verification of the modules, is also suitable for the user-defined protocol, and further improves the expandability of the method.
S2, generating a file: and acquiring preset test data and preset return data, generating an input excitation file by combining the preset test data and time sequence, and generating an expected result file by combining the preset return data and time sequence.
In timing combinations, some basic blocks, such as a start block or an end block, are constant for the communication protocol. However, for example, the slave address module, the digital byte module, or the like, is variable according to the slave to be tested and the data to be tested for the communication protocol. Therefore, the step also obtains preset test data, such as the slave address or the data to be tested, and the preset test data needs to be assigned to the variables in the time sequence combination to generate the final input excitation file.
In order to realize the subsequent automatic verification function, the invention also generates an expected result file in the step. When the slave to be tested is tested through the input excitation file generated by the preset test data, the slave to be tested returns a response signal, and in the theoretical case, the response signal is a group of data corresponding to the preset test data. The invention takes the data as preset return data, and generates an expected result file in the same way for subsequent verification.
In some embodiments, in step S2, the input stimulus file and the expected result file are generated separately using the same file generation script.
When the input excitation file and the expected result file are generated, only the input original data are different, namely the original data corresponding to the input excitation file are to-be-tested data which are required to be sent by the test host to the to-be-tested slave, and the original data corresponding to the expected result file are theoretical data which are received by the test host from the to-be-tested slave. The generated files are also different, the input excitation file is used for testing the use of the excitation signal sent by the host computer to the slave computer to be tested, and the expected result file is used for verifying the use of the actual result file.
In some embodiments, the file generation script is a preset Python script.
Of course, other forms of script in the art may be used as long as the input stimulus file and the expected result file can be generated.
S3, testing: and reading the input excitation file by using the test host, sending an excitation signal to the slave to be tested, receiving a response signal returned by the slave to be tested, and storing the response signal in an actual result file.
In some embodiments, the test host may be a simulation model, and the slave to be tested is a design to be tested, which is an RTL design that has been completed.
S4, verification: and comparing the actual result file with the expected result file for verification, if the verification is passed, the slave to be tested passes the test and the verification, and if the verification fails, the error position is positioned and displayed.
In some embodiments, in step S4, the actual result file and the expected result file are compared by the bit matcher, if the bit matching of the data can be achieved, the verification is considered to pass, otherwise the verification is considered to fail.
The bit matcher of the embodiment is an existing tool, and can realize the function of matching bits one by one, so that the specific structure thereof is not repeated here.
By means of the method, the purpose that bits are matched one by one for verification can be achieved, for example, if any bit in an actual result file and any bit in an expected result file are different, verification is considered to be failed, at the moment, the bit position of a verification error can be easily found, and bug can be conveniently and quickly located.
The presentation form of the step can have one or more of a plurality of modes, such as a printing mode, a list mode, a chart mode and the like.
Example 1:
taking the write function verification method of the I2C bus as an example, it has the following characteristics:
the I2C interface is bi-directional and allows multiple devices to operate on the same bus. To configure the bus function, each device has a unique hardware address called a slave address, and to communicate with a particular device on the bus, the controller (master) sends the slave address and obtains a response from the slave, called a reply bit. If the slave on the bus is properly addressed, it acknowledges the master by pulling the SDA (data line) bus low. If the address does not match the slave address, pulling the SDA bus high (NACK) does not answer the master. There will also be an ACK (response) when data is transmitted, and the slave will ACK after receiving each data byte when the master is writing data. When the host reads data, the host replies after receiving each data byte, letting the slave know that it wants to receive another data byte. When the host stops reading, it will send a NACK after the last data byte is received and create a stop condition on the bus.
All communications on the bus begin with either a start-up condition or a repeat start-up condition. When SCL (clock line) is high, the host generates a start condition by driving SDA high to low. A repetition start is generated to address different devices or to switch in read-write mode.
All communications on the bus end with a stop condition, which is generated from low to high when SCL is high. After the stop condition is generated, the bus remains idle until the host generates a start condition.
Referring to fig. 2, which is a basic communication sequence of the I2C communication protocol, module division is performed based on the protocol rule, and referring to fig. 3, the sequence is divided into 9 different modules, and the module list includes a start module, a restart module, a slave address module, a read flag bit, a write flag bit, a response bit, a non-response bit, a data byte and an end module. Each module corresponds to different time sequences, and for the I2C communication protocol, the module is provided with two time sequences, so that the module is provided with two time sequence lists, namely an SDA time sequence list and an SCL time sequence list, the time sequences of the modules are added into the two time sequence lists in sequence, and finally an input excitation file and an expected result file can be generated according to the two time sequence lists. And pre-storing the module list, the SDA time sequence list and the SCL time sequence list into a communication protocol module library.
Since each module has its corresponding timing, normal communication can be performed as long as the modules are reasonably combined. Therefore, in the case where the target communication protocol is the I2C communication protocol shown in fig. 2, the timing sequence corresponding to each module may be obtained from the communication protocol module library to be combined, so as to obtain one SDA timing sequence combination and one SCL timing sequence combination. Referring to fig. 4 and 5, an input stimulus file and an expected result file are generated in combination with preset test data and return data.
Taking Python script generation of input stimulus file and expected result file as examples:
the timing of the start module is represented in the Python script as list sda_start= [ 10 0], scl_start= [ 10 ];
the timing of the restart module is represented in the Python script as the list sda_restart= [ 10 0], scl_restart= [1 10 ];
the timing of the slave address module is represented in the Python script as list sda_addr= [ X XXXX ], scl_addr= [0 10 0 10 0 10 0 10 0 10 0 10 0 10 ];
the timing of the read flag bit module is represented in the Python script as list sda_read= [1 1 1], scl_read= [0 10 ];
the timing of the write flag bit module is represented in the Python script as list sda_write= [0 0 0], scl_write= [0 10 ];
the timing of the reply bit module is represented in the Python script as list sdaack= [0 0 0] and scl_ack= [0 10 ];
the timing of the non-reply bit module is represented in the Python script as list sda_nack= [1 1 1], scl_nack= [0 10 ];
the timing of the data byte module is represented in the Python script as the list sda_data= [ X XXXXXX ], scl_data= [0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 ];
the timing of the end module is represented in the Python script as the list sda_stop= [ 0.1 ], scl_stop= [ 0.1 ].
Wherein "X XXXX" in sda_addr is the slave address in the preset test data. "X XXXXX" in sda_data is data to be tested in the preset test data.
Referring to fig. 4 and 5, the test host adopts a simulation model, and the slave to be tested is an RTL design which is already completed, and tests and verifies the slave to be tested.
Before testing and verification, the sequence is divided into modules in advance according to protocol rules, and input excitation files and expected result files are generated by using Python scripts according to test cases, namely preset test data and preset return data.
After the test host reads the input excitation file, sequentially transmitting an excitation signal corresponding to the SDA time sequence combination and an excitation signal corresponding to the SCL time sequence combination to the slave to be tested bit by bit through an SDA pin and an SCL pin under the synchronization of the high-speed clock PCLK. After the slave to be tested detects the excitation signal of the test host, the slave to be tested responds to the test host.
And storing the output of the slave to be tested into an actual result file.
Comparing the actual result file with the expected result file through bit matching, and if the bit matching of the data can be realized, verifying the test case; otherwise, the verification fails and the bit position causing the verification error is printed, so that the bug can be conveniently and quickly positioned.
After the verification failure is found, checking can be performed by checking whether the RTL code of the slave to be tested is correct or checking whether the Python script is correct.
Therefore, the method of the embodiments can automatically verify the slave to be tested by changing different test cases. For the slaves to be tested of different protocols, the time sequence combination corresponding to the different protocols can be selected, and the slaves to be tested of the different protocols can be tested and verified. The invention greatly reduces the manpower and time resources in the process of testing and verifying the communication protocol.
The embodiment of the invention also provides an automatic verification system of the communication protocol, which comprises the following steps:
a test host;
the slave machine to be tested has the same communication protocol as the test host;
the time sequence combination module is used for acquiring a corresponding time sequence combination from a preset communication protocol module library according to a target communication protocol;
the file generation module is used for acquiring preset test data and preset return data, generating an input excitation file according to the preset test data and time sequence combination, and generating an expected result file according to the preset return data and time sequence combination;
the testing module is used for reading the input excitation file by using the testing host, sending an excitation signal to the slave to be tested, receiving a response signal returned by the slave to be tested and storing the response signal in an actual result file;
and the verification module is used for verifying the actual result file and the expected result file by comparing, if the verification is passed, the slave to be tested passes the test and the verification, and if the verification fails, the error position is positioned and displayed.
In some embodiments, the automated verification system of the communication protocol further comprises a bit matcher for comparing the actual result file and the expected result file.
In some embodiments, the automated verification system of the communication protocol further comprises:
the division module is used for dividing the communication protocol into modules to obtain a module list, establishing an association mapping relation between the communication protocol and the module list, adding one or more time sequences of the modules into the corresponding one or more time sequence lists, and establishing the association mapping relation between the modules and the corresponding time sequences.
The present invention has been described in detail with reference to the embodiments of the drawings, and those skilled in the art can make various modifications to the invention based on the above description. Accordingly, certain details of the embodiments are not to be interpreted as limiting the invention, which is defined by the appended claims.
Claims (10)
1. An automatic verification method of a communication protocol, comprising:
according to the target communication protocol, acquiring a corresponding time sequence combination from a preset communication protocol module library;
acquiring preset test data and preset return data, generating an input excitation file according to the preset test data and the time sequence combination, and generating an expected result file according to the preset return data and the time sequence combination;
reading the input excitation file by using a test host, sending an excitation signal to a slave to be tested, receiving a response signal returned by the slave to be tested, and storing the response signal in an actual result file;
and comparing the actual result file with the expected result file for verification, if the verification is passed, the slave to be tested passes the test and the verification, and if the verification is failed, the error position is positioned and displayed.
2. The method for automatically verifying a communication protocol according to claim 1, wherein the library of communication protocol modules is generated by:
obtaining a plurality of communication protocols, carrying out module division on each communication protocol to obtain a plurality of module lists, and establishing an association mapping relation between the communication protocols and the corresponding module lists, wherein the module lists are provided with a plurality of modules;
adding one or more time sequences of the modules into one or more corresponding time sequence lists, and establishing an association mapping relation between the modules and the corresponding time sequences to obtain a communication protocol module library comprising a plurality of module lists and a plurality of time sequence lists.
3. The method of automatic verification of a communication protocol according to claim 2, wherein the modules include, but are not limited to, one or more of a start, a restart, a slave address, a read flag bit, a write flag bit, a reply bit, a non-reply bit, a data byte, and an end.
4. The method for automatic verification of a communication protocol according to claim 2, wherein the target communication protocol and the communication protocol each comprise a standard protocol or a user-defined protocol.
5. The method of automatic verification of a communication protocol of claim 4, wherein the standard protocol comprises one or more of I2C, SPI and UART.
6. The automated method of validating a communication protocol of claim 1, wherein said input stimulus file and said expected result file are generated separately using the same file generation script.
7. The method for automatically verifying a communication protocol as defined in claim 1, wherein the verifying by comparing the actual result file and the expected result file comprises:
and comparing the actual result file with the expected result file through a bit matcher, if the bit matching of the data can be realized, considering that the verification is passed, and otherwise, considering that the verification is failed.
8. An automated verification system for a communication protocol, comprising:
a test host;
the slave machine to be tested is provided with the same communication protocol as the test host;
the time sequence combination module is used for acquiring a corresponding time sequence combination from a preset communication protocol module library according to a target communication protocol;
the file generation module is used for acquiring preset test data and preset return data, generating an input excitation file according to the preset test data and the time sequence combination, and generating an expected result file according to the preset return data and the time sequence combination;
the testing module is used for reading the input excitation file by using the testing host, sending an excitation signal to the slave machine to be tested, receiving a response signal returned by the slave machine to be tested and storing the response signal in an actual result file;
and the verification module is used for verifying the actual result file and the expected result file by comparing, if the verification is passed, the slave to be tested passes the test and the verification, and if the verification is failed, the error position is positioned and displayed.
9. The automated verification system of a communication protocol of claim 8, further comprising:
and the bit matcher is used for comparing the actual result file with the expected result file.
10. The automated verification system of a communication protocol of claim 8, further comprising:
the division module is used for carrying out module division on the communication protocol to obtain a module list, establishing an association mapping relation between the communication protocol and the module list, adding one or more time sequences of the modules into the corresponding one or more time sequence lists, and establishing the association mapping relation between the modules and the corresponding time sequences.
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