CN116340150A - Reusable register performance interactive verification system based on UVM and application thereof - Google Patents
Reusable register performance interactive verification system based on UVM and application thereof Download PDFInfo
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Abstract
The invention relates to the field of integrated circuit design, in particular to a reusable register performance interactive verification system based on UVM and application thereof. The verification system is applied to a verification device comprising a master and a slave. The verification system is written in a system verilog language and is created based on a UVM library and runs in a host of the verification device. The slave computer is in communication connection with the host computer through an interface; the slaves are RTL designs written using verilog or system verilog language. The invention provides a register performance interactive verification system, which comprises: the system comprises a configuration module, a test case module, an excitation sequence library module, a verification layer and a transaction-level modeling communication unit. The verification system can be used for other project verification only by configuring the communication content between the master and the slave without changing the internal code. Therefore, the invention can solve the problems of high simulation and verification cost of the project caused by the fact that the verification system and tools cannot be reused among different projects in the existing chip design process.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a reusable register performance interactive verification system based on UVM and application thereof.
Background
The chip is used as an important support and core technology component for informatization and intellectualization of modern science and technology and scientific products, and plays a role in national science and technology strategy. Chip design and production are high-technology, high-investment and high-risk industries, and particularly under the new process, the investment of funds produced by a single chip is even up to tens of millions, and often, a small error in the whole process of integrated circuit development can possibly lead the performance of the produced chip to be substandard, and all work in the early stage is lost.
The design of the chip starts from the architecture design, then through algorithm simulation, after the simulation is correct, the design specification is formulated, and RTL (Register Transfer Level ) design is carried out according to the design specification. After the design scheme is formed, the RTL code is required to be simulated and verified, the correctness of the RTL design is checked, and whether the design scheme design accurately meets all requirements in the specification is verified by taking the design specification as a standard. Finally, the design scheme and simulation verification are iterated repeatedly until the verification result shows that the verification result completely accords with the specification standard, and then the work such as logic synthesis, static time sequence analysis, form verification, layout wiring, layout physical verification and the like is performed. After the tasks of the whole chip design stage are completed, the work of the chip manufacturing stage can be formally started.
In the whole chip design and manufacturing flow, simulation verification is an important link, and the accuracy and completeness of the verification are very high, so that the accuracy of the RTL design can be ensured. So the requirement on chip verification in the chip development link is higher and higher at present, and the construction of a verification platform is more complicated. The traditional directional test platform is based on verilog language, and can not cover all functional points to be tested and can not be reused among different projects. Therefore, the technician needs to configure the corresponding verification program specifically for the designed RTL design scheme, and the prior art does not have a solution specifically for the interaction of the verification master and the slave, which can be reused among multiple projects, and all greatly influences the verification efficiency; the research and development period of the chip is greatly prolonged, and the simulation and verification cost in the design stage is increased.
Disclosure of Invention
In order to solve the problem that in the existing chip design process, the simulation and verification cost of items is high due to the fact that a verification system and tools cannot be reused among different items, the invention provides a reusable register performance interactive verification system based on UVM and application thereof.
The invention is realized by adopting the following technical scheme:
a reusable register performance interactive verification system based on UVM is applied to a verification device comprising a master and a slave. The reusable register performance interactive verification system based on UVM is written in a system verilog language and is created based on a UVM library and runs in a host of verification equipment. The slave computer is in communication connection with the host computer through an interface; the slaves are RTL designs written using verilog or system verilog language.
The invention provides a reusable register performance interactive verification system based on UVM, comprising: the system comprises a configuration module, a test case module, an excitation sequence library module, a verification layer and a transaction-level modeling communication unit.
The configuration module is used for creating corresponding configuration files according to the current connected slave and the corresponding verification task, and further declaring the information base files and the definition base files in the configuration files. The configuration module is also used to instantiate a virtual interface between the master and the slave.
The test case module is used for establishing each test case required by the host and the slave in the verification stage, and the test case is used for instantiating each instruction required by the verification stage.
The excitation sequence library module comprises a large number of excitation sequences generated according to each test case, and each excitation sequence comprises all information to be transmitted by communication between the host and the slave. The stimulus sequence library module utilizes a series of stimulus sequences to construct a sequence library required to verify different register functions.
The verification layer contains all functional modules for performing verification tasks, including agents, register models, self-comparators, and first-in-first-out queues. The agent comprises a sequencer, a driver and a monitor. The sequence generator is responsible for data transmission, and then sequence information in the excitation sequence library module is sequentially sent to the driver according to the requirements of the slave machine. The driver defines functions under different commands, drives the sequence information to the interfaces of the host and the slave, and further realizes bidirectional transmission of signals between the agent and the slave through the virtual interface. The monitor is connected with the interface between the host and the slave, and collects information on signal lines between the interfaces, and verifies the function and time sequence of signals sent by the driver in the verification stage. The register model is used for simulating an actual register in the design to be tested; and then according to the signal fed back to the host computer by the slave computer in the verification stage, the virtual operation of the full-function verification process of the register to be tested is realized in the host computer. The driver is also connected with the automatic comparator through the first-in first-out queue so as to realize that the driver can sequentially send the information to be verified to the automatic comparator simultaneously while sending signals to the slave. The automatic comparator also receives feedback information from the register module, compares the received sending signal with the feedback information, and verifies correct if the sending signal and the feedback information are the same, otherwise verifies errors.
The transaction-level modeling communication unit is used for realizing communication connection between different function modules instantiated in the verification layer, and specifically comprises the inside of the agent and the driver, the between the agent and the first-in first-out queue, and the between the first-in first-out queue and the automatic comparator; and finally, a stable information communication connection can be established between the driver and the automatic comparator.
As a further development of the invention, the information base file is derived from the object class. Defining all fixed information needed by the whole register performance interactive verification system in an information base file; comprising the following steps: the length of the read-write data, the number of the read-write data, the format of commands and feedback when the master machine and the slave machine interact, and the like. The library file defines fixed information as local variables and uses an automated domain mechanism to register these variables into the overall register performance interactive verification system for use by all components.
As a further improvement of the present invention, the library file is defined so as to be able to observe the verification result more conveniently. The definition library file defines sampling rules of the feedback signals on the signal lines, and defines each state of the verification stage by adopting an enumeration type. The definition library file contains each command state sent by the host, each command state fed back by the slave, the address state sent by the host, and the like. Such that the signals of all interactions in the validation process debug waveform correspond to different schedules for each command.
In the scheme provided by the invention, the interface between the host and the slave comprises all the definition of the interface signals of the slave which are needed to be used, so that the data communication between the host and the slave is realized. The virtual interface is used for instantiating the communication link between the host computer and the slave computer in the verification process of each register chip, so that when the slave computer is changed, the virtual interface is only required to be changed, and the transmission of signals between each component in the test certificate layer of the host computer and the slave computer can be realized through a config_db mechanism of UVM.
As a further improvement of the invention, in the test case module, the test cases are divided into two types of basic test cases and extended test cases. The test cases of the basic test respectively need an instance verification environment, a default sequence is set, the overtime exit time of the whole system is set, and the values of partial parameters in the verification environment are set. The expanding test cases are combined on the basis of the basic test cases, so that a plurality of test cases for completing verification tasks, such as data reading, writing, erasing and the like, are expanded.
As a further improvement of the invention, in the excitation sequence library module, when the slave machine or the test case is adjusted, the sequence library needs to be changed; at this time, only a new excitation sequence needs to be generated, and the original excitation sequence needs to be added, deleted or modified.
As a further improvement of the invention, the authentication layer is re-created before the execution of the multiple authentication tasks for each IP. The agent is an execution module that validates the task and completes the task using the driver, monitor, and sequencer. For different verification tasks in the same IP, only partial adaptation is needed to be carried out on the agent; for part of the common IP, a dedicated agent is selected to be configured for direct replacement in the verification layer creation process.
As a further development of the invention, a verification component is also included in the verification layer, the verification component being in communication with the monitor. The verification component is used for counting all monitoring information acquired by the monitor, further judging whether the excitation signal sent by the driver already contains verification of all functions of the slave, and finally outputting a coverage rate index representing the completion degree of the verification function. In a UVM-based reusable register performance interactive verification system, the verification component chooses to employ an integrator or coverage collector.
As a further development of the invention, a top module is included in the topmost layer of the authentication device. The top-level module defines clock and reset variables that generate clock and reset signals. The top-level module instantiates an interface between the master and the slave; the top-level module also instantiates the slave and connects the signals on the slave with the interface signals.
The invention also comprises a reusable register performance interactive verification system application based on UVM, in the application, the reusable register performance interactive verification system based on UVM is used as a host, an RTL design scheme written by using verilog or system verilog language is used as a slave, and an interface between the host and the slave is instantiated through a top layer module; furthermore, a virtualization verification device for verifying the register performance of the RTL design scheme can be built. The virtualized verification device is used for completing verification tasks related to data reading, writing and erasing of registers in an RTL design scheme.
In the virtualized verification device constructed by the invention, the verification process of the data writing function comprises the following steps:
s1: in the register performance interactive verification system of the host, the information base file and the write information defining the base file are configured. The write information includes a write command of the host, write feedback of the slave, write address of the host, address feedback of the slave, write data of the host, write data feedback of the slave, and the like.
S2: and instantiating and starting a corresponding sequence in a sequence library in the virtual sequence according to scene requirements, wherein verification tasks started and executed by the sequence comprise multiple times of writing operation, and addresses and data of the multiple times of writing operation are distributed in a specified mode and a random mode.
S3: and writing a test case corresponding to the write operation verification scheme, inheriting the test case from a test layer, and finally mounting the virtual sequence to a sequence sender in a default_sequence mode to start a corresponding sequence.
S4: and transferring a character string to run_test () to create an instance of the class represented by the character string, then automatically starting the register performance interactive verification system, sequentially executing the phase mechanisms of all components, and ending simulation after all phases are executed.
S5: the automatic comparator generates verification data of each verification, and then the external script is operated to directly summarize and analyze the related data of multiple verifications, so as to give a final verification result.
The technical scheme provided by the invention has the following beneficial effects:
1. the verification system provided by the invention has high universality. The verification system adopts the most mainstream UVM verification methodology to build the verification environment, so that the verification environment can be reasonably reused. This ensures both the correctness of the verification system code and avoids repeated development of the verification components. Only a small amount of code modification is needed in different projects, and the code modification can be put into other verification processes; therefore, the research and development cost of the verification stage in the chip design process can be effectively reduced.
2. The present invention provides a powerful verification system. Not only is the system-level chip verification platform limited to the IP module level verification platform, but also the system-level chip verification platform can be multiplexed. For different development projects, the method can be applied to complex IP and system levels by only configuring a plurality of groups of corresponding signals.
3. The verification system provided by the invention has strong expansibility. Communication between the host and the slave computers with various configurations is supported, the interface supports bidirectional signals shared by the host and the slave computers, the register model supports front door access and back door access, supports different bus bit widths, and supports modification to other bus protocols.
4. The verification system provided by the invention is simple in application process operation. The convergence of verification completeness can be accelerated by flexibly constructing various required test cases and adding constrained random excitation. The verification efficiency of the written test case is high, a more comprehensive scene can be simulated, and the research and development period of the IC design is greatly shortened.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
fig. 1 is a functional schematic diagram of an authentication device including a master and a slave in embodiment 1 of the present invention.
Fig. 2 is a system topology structure diagram of a reusable register performance interactive verification system based on UVM according to embodiment 1 of the present invention.
Fig. 3 is a schematic diagram of a two-stage check scheme for back gate access employed in the register model.
Fig. 4 is a diagram of the architecture of the virtualized authentication device created in embodiment 2 of the invention.
FIG. 5 is a workflow diagram of the virtualization device verification phase shown in example 2 taking a data write operation of a register as an example.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1
In the actual development of chip design projects, the design among the projects, although not entirely identical, is always able to find key point similarities. No matter how complex the design is for different RTL designs, many common base designs are always involved and a single base functional test is required. For the verification link of a specific chip design project, the most important work is to establish communication between an external system and an RTL design, where the external system corresponds to a master, and the RTL design corresponds to a slave. The corresponding command is then sent by the host, and the slave receives and gives feedback. And finally judging the correctness of the RTL design according to the evaluation result of feedback received by the host.
Therefore, for the application scenario, the embodiment provides a reusable register performance interactive verification system based on UVM. The core advantage of this register performance interactive verification system is reusability, i.e. it can be applied to functional verification of different RTL designs. The application process does not need to change the internal code of the verification system, and only needs to reconfigure the communication content between the host and the slave, so the verification system belongs to a flexible, strong-adaptability and expandability verification system.
Specifically, the scheme of the embodiment is applied to an authentication device comprising a master and a slave. The reusable register performance interactive verification system based on the UVM is written in a system verilog language and is established based on a UVM library, and the verification system operates in a host of verification equipment and serves as an execution subject of verification tasks. The slave computer is in communication connection with the host computer through an interface; the slave is an RTL design scheme written in verilog or system verilog language, and the slave is an execution object of verification tasks, and the logical relationship between the two is shown in fig. 1.
As shown in fig. 2, the reusable register performance interactive verification system based on UVM designed in this embodiment includes: the system comprises a configuration module, a test case module, an excitation sequence library module, a verification layer and a transaction-level modeling communication unit.
The configuration module is used for creating corresponding configuration files according to the current connected slave and the corresponding verification task, and further declaring the information base files and the definition base files in the configuration files. The configuration module is also used to instantiate a virtual interface between the master and the slave.
The information base file is derived from the object class. Defining all fixed information needed by the whole register performance interactive verification system in an information base file; comprising the following steps: the length of the read-write data, the number of the read-write data, the format of commands and feedback when the master machine and the slave machine interact, and the like. The library file defines fixed information as local variables and uses an automated domain mechanism to register these variables into the overall register performance interactive verification system for use by all components.
The information base file stated in the configuration file can realize the change of the configuration of the verification system from the top layer, so that the problem of a great deal of information base file modification content in different projects can be avoided. There is no concern about the hidden trouble that the whole verification system is crashed due to careless modification of a place. This arrangement greatly reduces the error rate. Meanwhile, the proposal of the embodiment also defines set and get functions for changing or printing the editable information so as to ensure that the platform can not be changed as much as possible after transplanting. When the slave changes, many fixed information will also change, and only one change is needed in the file, and related information does not need to be modified at any other place.
The definition library file is written so that the verification result can be observed more conveniently. Because the hybrid embodiment is built in the verification equipment comprising the master and the slave, the interactive signal lines are fewer, and all 8-bit, 24-bit or 32-bit data are displayed in series. This results in a serial waveform that is very inconvenient to observe as the verification process proceeds to the waveform analysis stage. For better debugging, the embodiment uses the definition library file to define the sampling rule of the feedback signal on the signal line, and uses the enumeration type to define each state of the verification stage. The definition library file contains each command state sent by the host, each command state fed back by the slave, the address state sent by the host, and the like. Such that the signals of all interactions in the validation process debug waveform correspond to different schedules for each command.
In the scheme provided by the embodiment, the interface between the host and the slave comprises all the definition of the interface signals of the slave which are needed to be used, so that the data communication between the host and the slave is realized. The host computer can drive the generated excitation sequence to the slave computer, the slave computer can receive the excitation sequence and output a result to be fed back to the host computer, and the host computer further operates the slave computer according to the fed back result. To some extent, the interface simplifies the connections between modules, avoids hierarchical references, eliminates absolute paths, and avoids modifying all signals when a slave is changed.
Aiming at the defect that the traditional hardware interface cannot be well suitable for an object-oriented test platform and cannot be instantiated in programs and classes, the embodiment adopts a virtual interface between a host computer and a slave computer, and the virtual interface instantiates a communication link between the host computer and the slave computer in the verification process of each register chip so as to ensure that when the slave computer changes, only the virtual interface needs to be changed, and the transmission of signals between components in the test certificate layer of the host computer and the slave computer can be realized through a config_db mechanism of UVM.
The test case module is used for establishing each test case required by the host and the slave in the verification stage, and the test case is used for instantiating each instruction required by the verification stage. In the test case module, the test cases are divided into two types of basic test cases and extended test cases. The test cases of the basic test respectively need an instance verification environment, a default sequence is set, the overtime exit time of the whole system is set, and the values of partial parameters in the verification environment are set. The expanding test cases are combined on the basis of the basic test cases, so that a plurality of test cases for completing verification tasks, such as data reading, writing, erasing and the like, are expanded.
The excitation sequence library module comprises a large number of excitation sequences generated according to each test case, and each excitation sequence comprises all information to be transmitted by communication between the host and the slave. The stimulus sequence library module utilizes a series of stimulus sequences to construct a sequence library required to verify different register functions. In the excitation sequence library module, when the slave machine or the test case is adjusted, the sequence library needs to be changed; at this time, only a new excitation sequence needs to be generated, and the original excitation sequence needs to be added, deleted or modified.
The verification layer is an execution unit which is instantiated in the UVM-based reusable register performance interactive verification system and executes various verification instruction operations. It is composed of a series of functional modules that perform verification tasks, and the test layer china includes agents, register models, self-comparators, and first-in-first-out queues, etc.
The agent comprises a sequencer, a driver and a monitor. The sequence generator is responsible for data transmission, and then sequence information in the excitation sequence library module is sequentially sent to the driver according to the requirements of the slave machine. The driver defines functions under different commands, drives the sequence information to the interfaces of the host and the slave, and further realizes bidirectional transmission of signals between the agent and the slave through the virtual interface. The monitor is connected with the interface between the host and the slave, and collects information on signal lines between the interfaces, and verifies the function and time sequence of signals sent by the driver in the verification stage.
The register model is used to simulate the actual registers in the design under test. Specifically, the register model simulates the real register function characteristics in the RTL design scheme, reflects the current register state, and simultaneously realizes virtual operation of the full-function verification process of the register to be tested in the host through operations such as reading, writing, mirroring and the like. In this embodiment, the register model performs two-stage checking by adopting the back door access mode as described in fig. 3, so as to improve the efficiency of quick positioning problem in the verification process.
In the two-stage check scheme employed in fig. 3, a back gate access is taken as an example to explain the read/write operation procedure of the register model. For example, the master sends a write command to the slave, the slave gives feedback indicating that the command was received, then the master sends the address of the write, and the slave gives feedback indicating that the address was received. The host then sends the written data and the slave gives feedback indicating that this data was received and written into an internal register. The host sends a read command to the slave, the slave gives feedback indicating that the read address was received, then the host sends the read address, the slave gives feedback indicating that the read address was received, and then the slave sends the data of the corresponding register at the address to the host.
The driver is also connected with the automatic comparator through the first-in first-out queue so as to realize that the driver can sequentially send the information to be verified to the automatic comparator simultaneously while sending signals to the slave. The communication connection state between different functional modules instantiated in the verification layer by the transaction-level modeling communication unit specifically comprises the communication connection between the agent and the driver, between the agent and the first-in first-out queue, and between the first-in first-out queue and the automatic comparator; and finally, a stable information communication connection can be established between the driver and the automatic comparator.
The whole verification system of the automatic comparator compares the feedback content of the RTL design scheme, one end of the whole verification system receives information sent by a driver, the other end of the whole verification system receives data of a register model (in the embodiment, a back door access mode of the register model is taken as an example), the two groups of data are compared, if the two groups of data are equal, the verification is correct, and if the two groups of data are not equal, the verification is failed.
For example, when a host wants to write things to a slave, the sequence generated by the sequence generator will include written information such as a written address and written data thereon, which is then sent to the drive. The driver drives the sequence to the slave and sends the information to the automatic comparator, the automatic comparator receives a correct address and correct written data, and the register model fetches the real data in the slave corresponding to the address through a back gate access mode and transmits the real data to the automatic comparator, and the automatic comparator has two groups of data. One group is the correct data that should be written, the other group is the data that is actually written into the register, if equal, the correct is verified, and if unequal, the error is verified.
In the solution of the present embodiment, the verification layer needs to be recreated before the IP of each design performs various verification tasks. The agent is an execution module that validates the task and completes the task using the driver, monitor, and sequencer. For different verification tasks in the same IP, only partial adaptation is needed to be carried out on the agent; for part of the common IP, a dedicated agent is selected to be configured for direct replacement in the verification layer creation process.
In addition, in some verification tasks of RTL designs that include more complex functionality, it is also necessary to further add a verification component in the verification layer, the verification component being communicatively connected to the monitor. The verification component is used for counting all monitoring information acquired by the monitor, further judging whether the excitation signal sent by the driver already contains verification of all functions of the slave, and finally outputting a coverage rate index representing the completion degree of the verification function. In a UVM-based reusable register performance interactive verification system, the verification component chooses to employ an integrator or coverage collector.
Example 2
The embodiment provides a reusable register performance interactive verification system application based on UVM, in the application, the reusable register performance interactive verification system based on UVM provided in embodiment 1 is used as a host, an RTL design scheme written by using verilog or system verilog language is used as a slave, and an interface between the host and the slave is instantiated through a top-level module; furthermore, a virtualization verification device for verifying the register performance of the RTL design scheme can be built.
The virtualization verification device is mainly used for completing verification tasks related to data reading, writing and erasing of registers in an RTL design scheme. As shown in fig. 4, the top layer of the verification device of the present embodiment includes a top layer module. The top-level module defines clock and reset variables that generate clock and reset signals. The top-level module instantiates an interface between the master and the slave; the top-level module also instantiates the slave and connects the signals on the slave with the interface signals.
In the scheme of the embodiment, the verifier only needs to modify the interface between the slaves, then update the information in the information base file according to the communication requirement between the slaves, and finally verify the different slaves by performing some simple configuration on the proxy. Therefore, the scheme provided by the embodiment can greatly improve the verification efficiency of the complex RTL design scheme while ensuring the verification quality.
In the solution of this embodiment, any complex verification task may be decomposed into different test cases for implementation. Thus the verification process for all RTL designs can employ approximately the same processing logic; the method mainly comprises five stages of verification system configuration, sequence library instantiation, test case writing and excitation sequence generation, register simulation and verification data sampling analysis.
For example, in the virtualized authentication device constructed in the present embodiment, the authentication process of the data writing function is approximately as shown in fig. 5, and includes the steps of:
s1: in the register performance interactive verification system of the host, the information base file and the write information defining the base file are configured. The write information includes a write command of the host, write feedback of the slave, write address of the host, address feedback of the slave, write data of the host, write data feedback of the slave, and the like.
S2: and instantiating and starting a corresponding sequence in a sequence library in the virtual sequence according to scene requirements, wherein verification tasks started and executed by the sequence comprise multiple times of writing operation, and addresses and data of the multiple times of writing operation are distributed in a specified mode and a random mode.
S3: and writing a test case corresponding to the write operation verification scheme, inheriting the test case from a test layer, and finally mounting the virtual sequence to a sequence sender in a default_sequence mode to start a corresponding sequence.
S4: and transferring a character string to run_test () to create an instance of the class represented by the character string, then automatically starting the register performance interactive verification system, sequentially executing the phase mechanisms of all components, and ending simulation after all phases are executed.
S5: the automatic comparator generates verification data of each verification, and then the external script is operated to directly summarize and analyze the related data of multiple verifications, so as to give a final verification result.
In summary, the system provided in this embodiment uses the currently most mainstream UVM verification methodology to build the verification environment, so that the system has high universality and is suitable for reasonable multiplexing. Thus, the correctness of the code can be ensured, and repeated development of the verification component can be avoided. The technician can put the code into the verification process of other projects only by making a small amount of code modification for the specific project designed. In addition, the system is not only limited to the IP module level verification platform, but also can be multiplexed on the system level chip verification platform, and multiple groups of signals can be configured at will, so that the system is more convenient to apply in some complex IP and system levels.
The system has strong expansibility, supports communication between the host computers and the slave computers with various configurations, supports bidirectional signals shared by the host computers and the slave computers, supports front door access and back door access by a register model, supports different bus bit widths, and supports modification to other bus protocols. Meanwhile, by flexibly constructing various required test cases and adding constrained random excitation, convergence of verification completeness can be accelerated. Therefore, the verification system of the embodiment has high verification efficiency of the test cases, can simulate more comprehensive scenes, and greatly shortens the research and development period of the IC design.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. A UVM-based reusable register performance interactive verification system, characterized by: the method is applied to an authentication device comprising a master machine and a slave machine; the reusable register performance interactive verification system based on UVM is written by adopting a system verilog language, is created based on a UVM library and operates in a host of verification equipment; the slave computer is in interface communication connection with the host computer; the slave machine is an RTL design scheme written by using verilog or system verilog language; the UVM-based reusable register performance interactive verification system comprises:
the configuration module is used for creating a corresponding configuration file according to the current connected slave and the corresponding verification task, and further declaring the information base file and the definition base file in the configuration file; the configuration module is also used for instantiating a virtual interface between the host and the slave;
the test case module is used for establishing each test case required by the host and the slave in the verification stage, and the test case is used for instantiating each instruction required by the verification stage;
the excitation sequence library module comprises a large number of excitation sequences generated according to each test case, and each excitation sequence comprises all information to be transmitted by communication between the host and the slave; the excitation sequence library module utilizes a series of excitation sequences to form a sequence library required for verifying different register functions;
the verification layer comprises all functional modules for executing verification tasks, including an agent, a register model, a self-comparator and a first-in first-out queue; the agent comprises a sequencer, a driver and a monitor; the sequence generator is in charge of data transmission, and further sequentially sends sequence information in the excitation sequence library module to the driver according to the requirements of the slave machine; the driver defines functions under different commands, drives sequence information to interfaces of the host and the slave, and further realizes bidirectional transmission of signals between the agent and the slave through a virtual interface; the monitor is connected with an interface between the host and the slave, collects information on a signal line between the interfaces, and verifies the function and time sequence of signals sent by the driver in a verification stage; the register model is used for simulating an actual register in the design to be tested; further, according to signals fed back to the host computer by the slave computer in the verification stage, virtual operation of the full-function verification process of the register to be tested is realized in the host computer; the driver is also connected with the automatic comparator through the first-in first-out queue so as to realize that the driver can sequentially send the information to be verified to the automatic comparator at the same time when sending signals to the slave; the automatic comparator also receives feedback information from the register module, compares the received sending signal with the feedback information, and verifies correct if the sending signal and the feedback information are the same, otherwise verifies error; and
a transaction-level modeling communication unit for realizing communication connection between the agent and the driver, between the agent and the first-in first-out queue, and between the first-in first-out queue and the automatic comparator, which are instantiated in the verification layer; and information communication between the driver and the automatic comparator is ensured.
2. The UVM based reusable register performance interactive verification system of claim 1, wherein: the information base file is derived from the object class, and all fixed information required by the whole register performance interactive verification system is defined in the information base file; comprising the following steps: the length of the read-write data, the number of the read-write data, and the format of command and feedback during the interaction of the master and slave; the library file defines the fixed information as local variables and uses an automated domain mechanism to register these variables into the overall register performance interactive verification system for use by all components.
3. The UVM based reusable register performance interactive verification system of claim 1, wherein: the definition library file is written to enable more convenient observation of the verification result; the definition library file defines sampling rules of feedback signals on the signal line, and defines each state of the verification stage by adopting an enumeration type; defining all command states sent by a host in a library file, feeding back all command states by a slave, and sending address states of all commands by the host; such that the signals of all interactions in the validation process debug waveform correspond to different schedules for each command.
4. The UVM based reusable register performance interactive verification system of claim 1, wherein: the interface between the host and the slave comprises all the definition of the interface signals of the slave which are needed to be used, so as to realize the data communication between the host and the slave; the virtual interface is used for instantiating the communication link between the host computer and the slave computer in the verification process of each register chip, so that when the slave computer is changed, the virtual interface is only required to be changed, and the transmission of signals between each component in the test certificate layer of the host computer and the slave computer can be realized through a config_db mechanism of UVM.
5. The UVM based reusable register performance interactive verification system of claim 1, wherein: in the test case module, the test cases are divided into a basic test case and an extended test case; the test cases of the basic test respectively need an instance verification environment, default sequences are set, overtime exit time of the whole system is set, and values of partial parameters in the verification environment are set; the expanding test cases are combined on the basis of the basic test cases, so that a plurality of test cases for completing verification tasks, such as data reading, writing, erasing and the like, are expanded.
6. The UVM based reusable register performance interactive verification system of claim 1, wherein: in the excitation sequence library module, when the slave machine or the test case is adjusted, the sequence library needs to be changed; at this time, only a new excitation sequence needs to be generated, and the original excitation sequence needs to be added, deleted or modified.
7. The UVM based reusable register performance interactive verification system of claim 1, wherein: the verification layer is re-created before the execution of a plurality of verification tasks of each IP; the agent is an execution module for verifying the task and completes the task by using the driver, the monitor and the sequencer; for different verification tasks in the same IP, only partial adaptation is needed to be carried out on the agent; for part of the common IP, a dedicated agent is selected to be configured for direct replacement in the verification layer creation process.
8. The UVM based reusable register performance interactive verification system of claim 1, wherein: the verification layer also comprises a verification component which is in communication connection with the monitor; the verification component is used for counting all monitoring information acquired by the monitor, judging whether an excitation signal sent by the driver already contains verification of all functions of the slave, and finally outputting a coverage rate index representing the completion degree of the verification function; in the UVM-based reusable register performance interactive verification system, a verification component selects to employ an integrator or coverage collector.
9. The UVM based reusable register performance interactive verification system of claim 1, wherein: a top layer module is contained in the top layer of the verification device; the top module defines clock and reset variables and generates clock and reset signals; the top-level module instantiates an interface between the master and the slave; the top-level module also instantiates the slave and connects the signals on the slave with the interface signals.
10. A reusable register performance interactive verification system application based on UVM, wherein the reusable register performance interactive verification system based on UVM as claimed in any one of claims 1-9 is used as a master, and an RTL design scheme written in verilog or system verilog language is used as a slave, and an interface between the master and the slave is instantiated through a top-level module; furthermore, a virtual verification device for verifying the register performance of the RTL design scheme can be built; the virtualization verification equipment is used for completing verification tasks related to data reading, writing and erasing of registers in the RTL design scheme;
the verification process of the data writing function in the virtualized verification device comprises the following steps:
s1: in a register performance interactive verification system of a host, configuring write information of an information base file and a definition base file; the writing information comprises a writing command of the host, writing feedback of the slave, writing address of the host, address feedback of the slave, writing data of the host and writing data feedback of the slave;
s2: instantiating and starting a corresponding sequence in a sequence library in a virtual sequence according to scene requirements, wherein verification tasks started and executed by the sequence comprise multiple times of writing operation, and addresses and data of the multiple times of writing operation are distributed in a specified mode and a random mode;
s3: writing a test case corresponding to the write operation verification scheme, inheriting the test case in a test layer, and finally mounting the virtual sequence to a sequence sender in a default_sequence mode to start a corresponding sequence;
s4: transmitting a character string to run_test () to create an instance of the class represented by the character string, then automatically starting a register performance interactive verification system, sequentially executing phase mechanisms of all components, and ending simulation after all phases are executed;
s5: the automatic comparator generates verification data of each verification, and then the external script is operated to directly summarize and analyze the related data of multiple verifications, so as to give a final verification result.
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