CN114266210A

CN114266210A - WGL file processing method and application in chip ATE test

Info

Publication number: CN114266210A
Application number: CN202111564962.6A
Authority: CN
Inventors: 高胜; 赵毅辰; 胡扬央
Original assignee: Mouxin Technology Shanghai Co ltd
Current assignee: Mouxin Technology Shanghai Co ltd
Priority date: 2021-12-20
Filing date: 2021-12-20
Publication date: 2022-04-01

Abstract

The invention discloses a WGL file processing method and application in a chip ATE test, and relates to the technical field of chip development. The method comprises the following steps: acquiring a waveform generation language WGL file to be verified, and converting the waveform generation language WGL file into a simulation testbench file and a comprehensive testbench file through a script; sending a starting command to the comprehensive testbench file through the simulation testbench file, starting the comprehensive testbench file after receiving the starting command, sending IO excitation to the chip to be tested, and acquiring response output information of the chip to be tested; and comparing the response output information with preset standard output data to verify the correctness of the WGL file. The invention can ensure the correctness of the WGL file provided for the ATE test end, reduces the misjudgment rate of the ATE test, and further can shorten the whole development period of the chip.

Description

WGL file processing method and application in chip ATE test

Technical Field

The invention relates to the technical field of chip development, in particular to a WGL file processing method and application in a chip ATE test.

Background

ATE (Automatic Test Equipment) includes devices operable to perform high-speed testing on Integrated Circuit (IC) chips to verify that memory, logic, and other IC devices are functioning properly during and after their development, fabrication, manufacturing, and generation. Specifically, the ATE uses a chip design simulation file as a chip input stimulus, provides a chip test environment through an ATE test platform, and compares the output of the chip with a test result to determine the quality of the chip.

In the chip field, before the production of chips, the automatic chip testing and screening must be performed by ATE test vectors (ATE patterns). In the chip Design process, the simulation file is generally generated by an Electronic Design Automation (EDA) simulation tool, and the simulation file generated by the EDA simulation tool cannot be directly used by the ATE, and needs to be converted into a test file that can be recognized by the ATE. At present, usually, a chip EDA verifier provides a VCD (value Change dump) Waveform file for ATE testing, and after acquiring the VCD Waveform file, an ATE tester converts the VCD Waveform file into a WGL (Waveform Generation Language) file, and then converts the WGL file into an ATE pattern. The VCD waveform file is a file format based on ASCII codes and used for recording signal information generated by an EDA simulation tool, and the VCD waveform file is a simulation file which is most widely used in the development process of a test program at the present stage, takes zero moment as a starting point and time as a horizontal axis and mainly comprises an event set of level signals of 0, 1, x, z and the like. Each signal keeps the previous state before the next state jump, and the internal part of each signal contains rich time sequence information. The WGL file mainly describes the signal names of input/output (IO) pins to be used for the test and information of the test process. The WGL is a data descriptive language describing scan structures and states, and timing and values of test pattern parts, and WGL syntax can support the generation of hardware scan structures and test programs in devices, allows variable definition and inline equation expressions, and can replace graphic data representation of ASCII code with binary format. The main syntax structure of the WGL includes a waveform block, a timing block, a signal block, a subroutine block, a scan chain block, and the like.

For the conversion of VCD waveform files to WGL files, and WGL files to ATE patterns, conversion is currently usually performed by a conversion script or conversion software purchased. However, since the VCD file is difficult to compare after conversion, the VCD file includes all information of each pin, and the VCD file must be cycled using a fixed cycle, and when a timing format is determined for each cycle, some timing information may be omitted, and thus the converted signal will be different from the original signal, so that an error occurs in the converted WGL file. Due to the fact that the WGL file after conversion is wrong, the ATE pattern obtained by conversion of the WGL file also contains errors, the ATE test result is regarded that chip logic functions are in a problem, and misjudgment of chip failure is generated. The above situations belong to the actual qualification of chips, but the WGL file conversion causes wrong screening of an ATE machine, the chips are considered unqualified, the reject ratio of the chips is increased (the yield is reduced), and the mass production of the chips is delayed.

For the above situation, at present, EDA verification information and ATE test information often need to be checked to determine whether a chip is truly unqualified or an ATE machine is mistakenly screened due to a problem occurring when an EDA file is converted into an ATE pattern. However, at present, the above-mentioned work is often carried out manually by a tester for debugging and troubleshooting, and for a chip with high integration level and complex function, the test data is huge, and a lot of time is spent by the tester. Meanwhile, the manual investigation is relied on, so that the investigation speed and efficiency are low, and the whole chip development period is influenced.

Disclosure of Invention

The invention aims to: the defects of the prior art are overcome, and a WGL file processing method and application in the ATE test of a chip are provided. The WGL file is a simulation testbench file and a synthesizable testbench file, and a chip to be tested (DUT) is simulated based on the generated simulation testbench and synthesizable testbench to verify the correctness of the WGL file, so that the incorrect WGL file can be screened, the correctness of the WGL file provided for an ATE test end is ensured, the condition that a chip ATE test result is not in accordance with reality due to the misconversion of the WGL file can be eliminated in advance, the misjudgment rate of ATE test is reduced, and the whole development period of the chip can be shortened.

In order to achieve the above object, the present invention provides the following technical solutions:

a WGL file processing method in an ATE (automatic test Equipment) test of a chip comprises the following steps:

acquiring a waveform generation language WGL file to be verified;

converting the WGL file into a simulation testbench file based on verilog language and a synthesizable testbench file based on synthesizable verilog language through scripts, wherein the synthesizable testbench file can be synthesized into a netlist;

sending a starting command to the comprehensive testbench file through the simulation testbench file, starting the comprehensive testbench file after receiving the starting command, sending IO excitation to the chip to be tested, and acquiring response output information of the chip to be tested;

and comparing the response output information with preset standard output data to verify the correctness of the WGL file.

Further, when the response output information is consistent with preset standard output data in comparison, the WGL file is judged to pass verification, and the WGL file is triggered to be converted into an ATE machine file, wherein the ATE machine file comprises test vector ATE pattern information and time sequence information.

Further, when the response output information is inconsistent with the preset standard output data, the WGL file is judged to be failed to be verified, and warning information of WGL file errors is output through a GUI (graphical user interface).

Further, the script is a python script.

Further, the function verification of the synthesized netlist of the synthesizable testbench file comprises the following steps,

performing insertion logic test and layout wiring processing on the comprehensive netlist to obtain a PR netlist, converting the PR netlist into a bitfile, and programming the bitfile file on the FPGA daughter board;

after power-on reset is started, IO excitation information is sent to a chip on a socket bottom plate through an FPGA daughter board through a slot, and an actual return value output by the chip is obtained through the FPGA daughter board;

and the FPGA daughter board compares the obtained actual return value with a preset ideal return value to verify the correctness of the testbench file which can be synthesized.

Further, when the actual return value is consistent with the ideal return value, the testbench file verification test can be comprehensively passed, the indicator lamp on the FPGA daughter board is triggered to light, and otherwise, the verification test result is judged to be failed.

Further, after the testbench file is started, each period value of IO excitation is sent to the chip to be tested through the counter.

The invention also provides a WGL file processing device in the ATE test of a chip, which comprises the following structure:

the receiving unit is used for acquiring a waveform generation language WGL file to be verified;

the file conversion unit is used for converting the WGL file into a simulation testbench file based on verilog language and a synthesizable testbench file based on synthesizable verilog language through the conversion script, and the synthesizable testbench file can be synthesized into a netlist;

and the file verification unit is used for sending a starting command to the comprehensive testbench file through the simulation testbench file, starting the comprehensive testbench file after receiving the starting command, sending IO excitation to the chip to be tested, acquiring response output information of the chip to be tested, and comparing the response output information with preset standard output data to verify the correctness of the WGL file.

Further, the system also comprises a netlist verification unit which is used for performing functional verification on the comprehensive netlist of the comprehensive testbench file; the netlist verification unit is configured to: performing insertion logic test and layout wiring processing on the comprehensive netlist to obtain a PR netlist, converting the PR netlist into a bitfile, and programming the bitfile file on the FPGA daughter board;

the FPGA daughter board is configured to send IO excitation information to a chip on a socket bottom board through a slot after power-on reset starting, and acquire an actual return value output by the chip; and comparing the obtained actual return value with a preset ideal return value to verify the correctness of the comprehensive testbench file.

The invention also provides a chip ATE test method, which comprises the following steps:

acquiring a VCD waveform file for ATE test provided by an EDA verification terminal;

after the VCD waveform file is converted to generate a WGL file, converting the WGL file into a simulation testbench file based on verilog language and a synthesizable testbench file based on synthesizable verilog language through a script, wherein the synthesizable testbench file can be synthesized into a netlist; sending a starting command to the comprehensive testbench file through the simulation testbench file, starting the comprehensive testbench file after receiving the starting command, sending IO excitation to the chip to be tested, and acquiring response output information of the chip to be tested; comparing the response output information with preset standard output data;

and when the comparison is consistent, converting the WGL file into an ATE machine file, and inputting the ATE machine file to an ATE test end for function test.

Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects as examples: the WGL files are the simulation testbench file and the synthesizable testbench file, and a chip to be tested (DUT) is simulated based on the generated simulation testbench and synthesizable testbench to verify the correctness of the WGL files, so that incorrect WGL files can be screened, the correctness of the WGL files provided for an ATE test end is ensured, the condition that a chip ATE test result is not practical due to the fact that the WGL files are wrongly converted can be eliminated in advance, the misjudgment rate of ATE test is reduced, and the whole development period of the chip can be shortened. Meanwhile, the process is simplified, the simulation result of the WGL file is guaranteed, and a chip design company can directly provide the WGL file for a client according to the requirement.

Drawings

Fig. 1 is a flowchart of a WGL file processing method in an ATE test of a chip according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of information processing for simulating a chip DUT based on a simulated testbench and a synthesizable testbench according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of information processing of testbench that can be comprehensively verified by FPGA according to the embodiment of the present invention.

Detailed Description

The WGL file processing method in the test of the ATE on a chip disclosed in the present invention is described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that technical features or combinations of technical features described in the following embodiments should not be considered as being isolated, and they may be combined with each other to achieve better technical effects. In the drawings of the embodiments described below, the same reference numerals appearing in the respective drawings denote the same features or components, and may be applied to different embodiments. Thus, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

It should be noted that the structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are only for the purpose of understanding and reading the present disclosure, and are not intended to limit the scope of the invention, which is defined by the claims, and any modifications of the structures, changes in the proportions and adjustments of the sizes and other dimensions, should be construed as falling within the scope of the invention unless the function and objectives of the invention are affected. The scope of the preferred embodiments of the present invention includes additional implementations in which functions may be executed out of order from that described or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present invention.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

Examples

Referring to fig. 1, a WGL file processing method in an ATE test of a chip according to the present invention includes the following steps.

S100, acquiring a Waveform Generation Language (WGL) file to be verified.

The WGL file mainly describes the input/output (IO) pin signal names used for the test and information of the test process. The main syntax structure of the WGL includes a waveform block, a timing block, a signal block, a subroutine block, a scan chain block, and the like.

The WGL file to be validated may be converted from an (E) VCD file provided by EDA validation personnel. The VCD file and the EVCD file are both in a file format based on ASCII code for recording signal information generated by EDA simulation tools, and the formats are basically consistent, and the main difference between them is that the EVCD file has information of pin type, i.e. it is marked that the pin is an input pin or an output pin, and the VCD file does not have the pin type information. In specific implementation, the conversion from the VCD file to the WGL file may be performed through dedicated conversion software or conversion scripts, which belongs to the prior art and is not described herein again.

And S200, converting the WGL file into a verilog language-based simulation testbench file (namely, a simulation excitation file) and a synthesizable testbench file (namely, a synthesizable true excitation file) through a script, wherein the synthesizable testbench file can be synthesized into a netlist.

The Testbench file is used to simulate whether the function or timing of the model meets the design requirement, and the content of the Testbench file may generally include: defining an interface type according to a model to be tested, initializing an input interface signal, instantiating the model, storing a waveform, importing and storing data and the like.

In this embodiment, the simulation testbench file is written based on verilog language, and the simulation testbench is not comprehensive and is used as an excitation file for EDA simulation and is executed in a simulator on a computer host.

The synthesizable testbench file is compiled based on synthesizable verilog language and is characterized in that a netlist can be synthesized, bitfile (bit stream file) can be generated after layout and wiring of the synthesized netlist on an FPGA verification platform, and the generated bitfile is downloaded to an FPGA to run.

S300, sending a starting command to the comprehensive testbench file through the simulation testbench file, starting and operating the comprehensive testbench file after receiving the starting command, sending IO (Input/Output) excitation to the chip to be tested, and obtaining response Output information of the chip to be tested.

As described with reference to fig. 2, after the simulated testbench file and the synthesizable testbench file are generated, the simulated testbench sends a start command to the synthesizable testbench. The comprehensive testbench can start Running (RUN) after receiving the starting command; the Testbench can be synthesized to continuously send IO excitation to a chip DUT (namely, a chip to be tested, the DUT is short for Design Under Testbench), and response output information of the chip DUT is obtained.

S400, comparing the response output information with preset standard output data to verify the correctness of the WGL file.

When the response output information is compared with preset standard output data to be consistent, the WGL file is judged to pass verification, and the WGL file is triggered to be converted into an ATE machine file, wherein the ATE machine file comprises test vector ATE pattern information and timing information (timing).

When the response output information is inconsistent with the preset standard output data, the WGL file is judged to fail to be verified, and warning information of WGL file errors can be output through a GUI (graphical user interface).

In this embodiment, the script is preferably a python script.

By way of example and not limitation, portions of the WGL file to be validated, for example, are as follows:

wherein, in the [1X-X-X0X10X0X0X1-X11-X0X0X0X0X0X0X0X1X-X-XX ] array, "X" represents NO concern (cat), "-" represents NO.

After the conversion by the python script, the content of the generated synthesizable verilog file is as follows:

after the testbench file capable of being synthesized is started, a counter (counter) sends out a cycle value of the IO port.

In another embodiment of this embodiment, the automatically generated synthesizable testbench file further supports FPGA (Field-Programmable Gate Array) verification, and may perform functional verification on the synthesized netlist of the synthesizable testbench file: because the simulation of the netlist more closely approximates the behavior of a real chip than the simulation of the RTL.

Specifically, as shown in fig. 3, the method includes the following steps: performing insertion logic test (DFT) and layout Routing processing on the comprehensive netlist to obtain a PR netlist, wherein the PR netlist is a netlist obtained after layout Routing (layout Routing) is completed on the basis of the DFT netlist, and the function and the time sequence of the PR netlist are closest to those of a physical chip; after the PR netlist is converted into a bitfile, the bitfile is burnt on the FPGA daughter board; after power-on reset is started, IO excitation information is sent to a chip on a socket bottom plate through an FPGA daughter board through a slot, and an actual return value output by the chip is obtained through the FPGA daughter board; and the FPGA daughter board compares the obtained actual return value with a preset ideal return value to verify the correctness of the testbench file which can be synthesized. At the moment, when the actual return value is consistent with the ideal return value, the testbench file verification test can be comprehensively passed, at the moment, the indicator lamp on the FPGA daughter board can be triggered to light, and otherwise, the verification test result is judged to be failed.

As an example of a typical manner, the comprehensive netlist of the synthesizable testbench file may be processed by an FPGA synthesis tool and a PR tool vivado to generate a binary bitfile, and then the bitfile may be burned into an FPGA daughter board (FPGA chip board). After the power-on reset is started, the FPGA daughter board starts to send the IO excitation information to a chip to be tested (chip DUT) on the socket bottom board through the slot, and the chip finally outputs a return value, which is called as an actual return value. And the FPGA daughter board receives the return value and starts to carry out data comparison, when the actual return value is consistent with the ideal return value, the PASS of the test result (PASS) is judged, the LED prompt lamp on the FPGA board is lightened, and otherwise, the test result FAILs (FAIL).

The socket board has the advantages that chips can be taken and placed at any time, and the purpose of constructing a small automatic test platform is achieved. When a large number of chips are screened as unqualified in the ATE test, automatically generated comprehensive verilog can be processed to generate a bitfile file, and the bitfile file is burnt and written on an FPGA board to test the chips.

Optionally, two prompting lamps, namely a green lamp and a red lamp, are arranged on the FPGA board, and when the test result passes, the green lamp is triggered to be turned on; and when the test result is failure, triggering a red light to light. Of course, the above prompting manner is preferred but not limited, for example, a person skilled in the art may select other prompting structures based on sound and/or light as required to represent the test result, such as a buzzer, and if the test result is successful, the buzzer does not sound, and if the test result is failed, the buzzer sounds. Therefore, the test result of the tester can be tested simultaneously in time.

The invention further provides a WGL file processing device in the ATE test.

The device comprises a receiving unit, a file conversion unit and a file verification unit.

The receiving unit is used for acquiring a waveform generation language WGL file to be verified.

The file conversion unit is used for converting the WGL file into a simulation testbench file based on verilog language and a synthesizable testbench file based on synthesizable verilog language through the conversion script, and the synthesizable testbench file can be synthesized into a netlist.

The file verification unit is used for sending a starting command to the comprehensive testbench file through the simulation testbench file, starting and operating the comprehensive testbench file after receiving the starting command, sending IO excitation to the chip to be tested, acquiring response output information of the chip to be tested, and comparing the response output information with preset standard output data to verify the correctness of the WGL file.

On the other hand, the device can also comprise a netlist verification unit which is used for performing functional verification on the synthesized netlist of the synthesizable testbench file; the netlist verification unit is configured to: and performing insertion logic test and layout wiring processing on the comprehensive netlist to obtain a PR netlist, converting the PR netlist into a bitfile, and programming the bitfile to the FPGA daughter board.

Other technical features are referred to in the previous embodiments and are not described herein.

The invention further provides a method for testing the ATE. The method comprises the following steps:

and S10, acquiring the VCD waveform file for the ATE test provided by the EDA verification terminal.

S20, converting the VCD waveform file to generate a WGL file, and converting the WGL file into a simulation testbench file based on verilog language and a synthesizable testbench file based on synthesizable verilog language through scripts, wherein the synthesizable testbench file can be synthesized into a netlist; sending a starting command to the comprehensive testbench file through the simulation testbench file, starting the comprehensive testbench file after receiving the starting command, sending IO excitation to the chip to be tested, and acquiring response output information of the chip to be tested; and comparing the response output information with preset standard output data.

And S30, converting the WGL file into an ATE machine file when the WGL file is consistent with the ATE machine file, and inputting the ATE machine file to an ATE test end for function test.

Further, the method can further include the step of performing functional verification on the synthesized netlist of the synthesizable testbench file, which is specifically as follows: performing insertion logic test and layout wiring processing on the comprehensive netlist to obtain a PR netlist, converting the PR netlist into a bitfile, and programming the bitfile file on the FPGA daughter board; after power-on reset is started, IO excitation information is sent to a chip on a socket bottom plate through an FPGA daughter board through a slot, and an actual return value output by the chip is obtained through the FPGA daughter board; and the FPGA daughter board compares the obtained actual return value with a preset ideal return value to verify the correctness of the testbench file which can be synthesized.

In the foregoing description, the disclosure of the present invention is not intended to limit itself to these aspects. Rather, the various components may be selectively and operatively combined in any number within the intended scope of the present disclosure. In addition, terms like "comprising," "including," and "having" should be interpreted as inclusive or open-ended, rather than exclusive or closed-ended, by default, unless explicitly defined to the contrary. All technical, scientific, or other terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs unless defined otherwise. Common terms found in dictionaries should not be interpreted too ideally or too realistically in the context of related art documents unless the present disclosure expressly limits them to that. Any changes and modifications of the present invention based on the above disclosure will be within the scope of the appended claims.

Claims

1. A WGL file processing method in an ATE (automatic test Equipment) test of a chip is characterized by comprising the following steps of: acquiring a waveform generation language WGL file to be verified;

2. The method of claim 1, wherein: when the response output information is compared with preset standard output data to be consistent, judging that the WGL file passes verification, and triggering to convert the WGL file into an ATE machine file, wherein the ATE machine file comprises test vector ATE pattern information and time sequence information.

3. The method of claim 1, wherein: when the response output information is inconsistent with the preset standard output data, judging that the WGL file fails to be verified, and outputting warning information of the WGL file error through a Graphical User Interface (GUI).

4. The method of claim 1, wherein: the script is a python script.

5. The method of claim 1, wherein: the function verification of the synthesized netlist of the synthesizable testbench file comprises the following steps,

6. The method of claim 5, wherein: and when the actual return value is consistent with the ideal return value, the testbench file verification test can be comprehensively passed, the indicator lamp on the FPGA daughter board is triggered to light, and otherwise, the verification test result is judged to be failed.

7. The method of claim 1, wherein: after the testbench file capable of being synthesized is started, sending out each period value of the IO port through the counter.

8. A WGL file processing device in an ATE test of a chip is characterized by comprising:

9. The apparatus of claim 8, wherein: the comprehensive testbench file system also comprises a netlist verification unit which is used for performing functional verification on the comprehensive netlist of the comprehensive testbench file; the netlist verification unit is configured to: performing insertion logic test and layout wiring processing on the comprehensive netlist to obtain a PR netlist, converting the PR netlist into a bitfile, and programming the bitfile file on the FPGA daughter board;

10. A method for testing an ATE (automatic test equipment) chip is characterized by comprising the following steps: