CN203434992U - Networking protocol serial port test device - Google Patents
Networking protocol serial port test device Download PDFInfo
- Publication number
- CN203434992U CN203434992U CN201320530093.XU CN201320530093U CN203434992U CN 203434992 U CN203434992 U CN 203434992U CN 201320530093 U CN201320530093 U CN 201320530093U CN 203434992 U CN203434992 U CN 203434992U
- Authority
- CN
- China
- Prior art keywords
- fpga
- configuration module
- testing apparatus
- interface unit
- serial ports
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The embodiment of the utility model provides a networking protocol serial port test device. The networking protocol serial port test device comprises two interface units used for receiving a to-be-tested protocol signal, two level switching circuits having the same number with the interface units and connected with the interface units, and also comprises a high-speed clock, a power supply module, a field programmable gate array (FPGA) and a configuration module for storing the work code of the FPGA. The level switching circuits, the configuration module, the high-speed clock and the power supply module are all connected with the FPGA, and the power supply module is also connected with the level switching circuits, the configuration module and the high-speed clock, and is used to supply power to the level switching circuits, the FPGA, the configuration module and the high-speed clock. The test device provided by the embodiment of the utility model can satisfy the requirement that the protocol signal interaction of a plurality of to-be-tested boards is tested simultaneously, and is lower in cost and simple in structure.
Description
Technical field
The utility model relates to serial ports technical field of measurement and test, relates in particular a kind of networking agreement serial ports testing apparatus.
Background technology
Object test is the important step in procotol exploitation, i.e. the agreement of actual motion exploitation in board in kind or real equipment is used for verifying the correctness of Network Protocol Design, to guarantee the normal operation of designed network.At present, the base band object test of wireless networking agreement mainly adopts wireless mode and wired mode.
Wireless mode is for each board under test configuration radio frequency unit, realizes totally interconnected by wireless channel.But which need to arrange corresponding radio-frequency apparatus, if there is no applicable radio-frequency apparatus, or radio-frequency apparatus itself is also in the development phase, when its performance is also unstable, is difficult to carry out base band object test.
Wired mode can adopt the mode of the direct-connected or switch of cable.
Adopt the direct-connected mode of cable can only realize point-to-point communication, and can not carry out a plurality of tests, adopt in addition the mode of wireless mode or switch, not only cost rises, and also makes test structure become complicated.
Utility model content
In view of this, the utility model proposes a kind of networking agreement serial ports testing apparatus, in order to solve testing apparatus in existing object test, can not carry out multinode test, cost is higher and baroque defect.
Technical scheme is as follows:
An agreement serial ports testing apparatus, at least two for receiving the interface unit of protocol signal to be measured, level shifting circuit identical with described interface unit number and that be connected with described interface unit;
Also comprise high-frequency clock, power module, FPGA, deposit the configuration module of described FPGA operation code;
Described level shifting circuit, configuration module, high-frequency clock, power module are all connected with described FPGA;
Described power module is also connected with described level shifting circuit, configuration module, high-frequency clock, and described power module is for providing required power supply to described level shifting circuit, FPGA, configuration module, high-frequency clock.
Preferably, in above-mentioned networking agreement serial ports testing apparatus, described configuration module also comprises jtag interface, and described jtag interface is connected with the JTAG pin of described FPGA, and PC carries out on-line debugging working procedure by described jtag interface to FPGA.
Preferably, in above-mentioned networking agreement serial ports testing apparatus, also comprise for regulating the function button of the operating state of described interface unit and the sample frequency of described FPGA;
The output of described function button is connected with the IO pin of described FPGA.
Preferably, in above-mentioned networking agreement serial ports testing apparatus, also comprise for showing the demonstration LED of described interface unit state.
Preferably, in above-mentioned networking agreement serial ports testing apparatus, also comprise the power control switch opening and closing for controlling described power subsystem.
In technique scheme, there is following beneficial effect:
Known via above-mentioned technical scheme, compared with prior art, the utility model.
The utility model embodiment provides the number of the interface unit of testing apparatus to be at least two, therefore this testing apparatus can meet and tests the mutual requirement of a plurality of board under test protocol signals simultaneously, in addition, during traditional object test, switch need to be set or be board under test configuration radio frequency unit, and the utility model is without the function that switch and radio frequency unit are set can realize object test, owing to need not being equipped with switch and radio frequency unit, the utility model embodiment provides the cost of testing apparatus lower, in addition, compared to the mode that is equipped with switch and radio frequency unit, structure is also simple.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, other accompanying drawing can also be provided according to the accompanying drawing providing.
Fig. 1 is a kind of structural representation of the disclosed networking agreement of the utility model serial ports testing apparatus;
Fig. 2 is another structural representation of the disclosed networking agreement of the utility model serial ports testing apparatus;
Fig. 3 is a kind of application schematic diagram of the disclosed networking agreement of the utility model serial ports testing apparatus.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
Referring to Fig. 1, the utility model discloses a kind of networking agreement serial ports testing apparatus, interface unit 110 is connected with treating side plate for receiving the interface unit 110 of protocol signal to be measured to comprise at least two,, level shifting circuit 120 identical with interface unit 110 numbers and that be connected with interface unit 110; Also comprise high-frequency clock 130, power module 140, FPGA(Field-Programmable Gate Array, field programmable gate array) 150, deposit the configuration module 160 of FPGA operation code.
The utility model embodiment provides the number of the interface unit of testing apparatus to be at least two, therefore this testing apparatus can meet and tests the mutual requirement of a plurality of board under test protocol signals simultaneously, in addition, during traditional object test, switch need to be set or be board under test configuration radio frequency unit, and the utility model is without the function that switch and radio frequency unit are set can realize object test, owing to need not being equipped with switch and radio frequency unit, the utility model embodiment provides the cost of testing apparatus lower, in addition, compared to the mode that is equipped with switch and radio frequency unit, structure is also simple.
Preferably, the output of power module 140 is connected with FPGA150, configuration module 160, level shifting circuit 120 and the power pins of high-frequency clock 130, for these 4 parts provide required power supply.Further, power module 140 can comprise alternating current-direct current voltage transformation unit and direct voltage conversion chip, wherein, alternating current-direct current voltage transformation unit converts 220V alternating current to 5V DC power supply, direct voltage conversion chip is converted to 5V DC power supply stable 3.3V and 1.2V DC power supply, for FPGA150, configuration module 160 and level shifting circuit 120 provide corresponding working power.
Preferably, the output of configuration module 160 is connected with the configuration pin of FPGA, and dispensing unit 160 is selected the configuring chip supporting with FPGA, deposits FPGA operation code.The output of high-frequency clock 130 is connected with the input end of clock of FPGA, and high-frequency clock 130 can adopt high speed crystal oscillator or crystal circuit.
Protocol signal to be measured is connected to this testing apparatus by interface unit 110, level shifting circuit 120 by the incoming level of interface unit 110 be fitted to FPGA interface level same levels after, send into the IO pin of FPGA.Further, interface unit 110 is connected with level shifting circuit 120 is two-way, and protocol signal to be measured IO pin by FPGA after the level adapted of level shifting circuit 120 is connected with FPGA is two-way.
When system powers on, FPGA is first by the configured port access configuration module 160 on FPGA, reads executive program after the operation code of depositing in configuration module 160.After system powers on, high-frequency clock 130 can produce cycle clock signal, outputs to the input end of clock of FPGA, to FPGA, provides work clock.FPGA is according to the operation code of configuration module 160, in the rising edge moment of cycle clock signal, the protocol signal to be measured of docking port unit 110 is sampled, after shaping, output to after filtering on the IO output pin that other interface units are corresponding, the IO output pin of FPGA is connected with level shifting circuit, output signal, after level shifting circuit is converted to the serial ports level with interface unit adaptation, sends on interface unit, has so just realized low delay between interface unit, totally interconnected.Testing apparatus of the present utility model, when work, only requires measured signal to access with serial mode, in addition, does not need node to be tested to carry out any signal processing and protocol conversion, applied widely.
Low delay is carried out to detailed explanation below, protocol signal to be measured is from the input of one of them interface unit again to the signal output of other interface units, and its signal delay is mainly postponed to form by sampling delay and the processing forward of FPGA.On the one hand, above-mentioned processing forward postpones not relate to the variation of agreement, so processing forward delay is irrelevant with speed and the quantity of the protocol signal to be measured of input, and the delay of processing forward is very low; On the other hand, sampling delay is all not more than a high-frequency clock cycle when input, output, and therefore, the clock module that proportion is high can obtain less sampling delay.
In conjunction with above-mentioned processing forward postpone and sampling delay known, total forward delay of protocol signal to be measured is irrelevant with the quantity of the board under test of this device of access, also irrelevant with signaling rate and the data volume of board under test, relevant with the frequency of high-frequency clock.Therefore, can be referring to Fig. 3, the utility model support connects a plurality of boards under test simultaneously, and number of nodes increase the forward delay that can not increase protocol signal to be measured.But in actual environment for use, it should be noted that, the number of connection that this device is supported is decided by the internal resource of FPGA and the IO pin number of FPGA.Below in conjunction with Fig. 3, introduce a concrete Application Example of the present utility model, have 6 procotol plates to be measured, respectively board under test 1-6, board under test is by two-way connection of interface unit of self serial ports with this testing apparatus, after the sampling that the output signal of each board under test is installed after tested, filtering Shape correction, send to other boards under test, form fully-connected network.Each board under test is the information of other boards under test of sending and receiving simultaneously all.When the output signal of each board under test is during without conflict, testing apparatus can be transmitted to other boards under test strictly according to the facts by signal; During conflict on signal generation time, testing apparatus is with " uncertain " mode forward signal, and simulation is disturbed and produced, and by the procotol of moving on board under test, independently carries out collision detection and conflict is processed.Therefore, this testing apparatus not only can Test Networking protocol network layer the correctness of design, synchronous and MAC that can also test link layer designs correctness.
In this embodiment, level shifting circuit can be selected the MAX232 chip of MAXIM company, FPGA selects the XC3S50A chip of xilinx company, and configuration module is selected the M25P80flash of ST Microelectronics company, adopts common 220V electric main power supply.Testing apparatus has 6 DB9 serial port interface units, can support 6 protocol boards to be measured to access simultaneously.
In other embodiment of the utility model, configuration module also comprises jtag interface, and jtag interface is connected with the JTAG pin of FPGA, and PC carries out on-line debugging working procedure by jtag interface to FPGA.
Referring to Fig. 2, the utility model discloses a kind of networking agreement serial ports testing apparatus, comprises at least two interface units 110, level shifting circuit 120 identical with interface unit 110 numbers and that be connected with interface unit 110; Also comprise high-frequency clock 130, power module 140, FPGA(Field-Programmable Gate Array, field programmable gate array) 150, deposit the configuration module 160 of FPGA operation code.
Further, the testing apparatus in the utility model embodiment also comprises for regulating the function button 170 of the operating state of interface unit 110 and the sample frequency of FPGA150.The output of function button 170 is connected with the IO pin of FPGA.The utility model embodiment can carry out the operating state of each interface unit of regulating and controlling by function button is set, can also control in addition the sample frequency parameter of FPGA, and the setting of function button can so that easy to operate, also have been expanded the function of whole device simultaneously.Wherein, easy to operate being embodied in: if there is no operation keys, the program that " logical/short " state of each interface and the sample frequency of FPGA read from dispensing unit when being started by FPGA is definite, and can not change in the course of the work.If change above parameter, must stop the operation of FPGA, again write dispensing unit code, then restart can.And arrange after push-button unit, can under the condition without interrupting device operation, by button, directly change " on/off " and the sample frequency of FPGA of each interface, therefore can make test operation more convenient.Function Extension is embodied in: because arranging of push-button unit can change " on/off " state of each interface in real time, therefore, operating state under the totally interconnected scene of each node that originally can test, can also dynamically test the working condition under more scenes such as new node adds, existing node exits.Operating state test to baseband network agreement will be more comprehensive.In other embodiment of the utility model, referring to Fig. 2, also comprise the demonstration LED for display interface location mode.
In other embodiment of the utility model, referring to Fig. 2, also comprise the power control switch opening and closing for controlling power subsystem.The output of power control switch is connected with the input of described power module, for controlling the keying of this device.
In this specification, each embodiment adopts the mode of going forward one by one to describe, and each embodiment stresses is the difference with other embodiment, between each embodiment identical similar part mutually referring to.
Finally, also it should be noted that, in this article, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby the process, method, article or the equipment that make to comprise a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or be also included as the intrinsic key element of this process, method, article or equipment.The in the situation that of more restrictions not, the key element being limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises key element and also have other identical element.
Above-mentioned explanation to the disclosed embodiments, makes professional and technical personnel in the field can realize or use the utility model.To the multiple modification of these embodiment, will be apparent for those skilled in the art, General Principle as defined herein can, in the situation that not departing from spirit or scope of the present utility model, realize in other embodiments.Therefore, the utility model will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
It on the above, is only a specific embodiment of the present utility model; not in order to limit the utility model; all any modifications of making within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection range of the present utility model.
Claims (5)
1. a networking agreement serial ports testing apparatus, is characterized in that, comprises that at least two for receiving the interface unit of protocol signal to be measured, level shifting circuit identical with described interface unit number and that be connected with described interface unit;
Also comprise high-frequency clock, power module, FPGA, deposit the configuration module of described FPGA operation code;
Described level shifting circuit, configuration module, high-frequency clock, power module are all connected with described FPGA;
Described power module is also connected with described level shifting circuit, configuration module, high-frequency clock, and described power module is for providing required power supply to described level shifting circuit, FPGA, configuration module, high-frequency clock.
2. in networking agreement serial ports testing apparatus according to claim 1, it is characterized in that, described configuration module also comprises jtag interface, and described jtag interface is connected with the JTAG pin of described FPGA, and PC carries out on-line debugging working procedure by described jtag interface to FPGA.
3. in networking agreement serial ports testing apparatus according to claim 1, it is characterized in that, also comprise for regulating the function button of the operating state of described interface unit and the sample frequency of described FPGA;
The output of described function button is connected with the IO pin of described FPGA.
4. in networking agreement serial ports testing apparatus according to claim 1, it is characterized in that, also comprise for showing the demonstration LED of described interface unit state.
5. in networking agreement serial ports testing apparatus according to claim 1, it is characterized in that, also comprise the power control switch opening and closing for controlling described power subsystem.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320530093.XU CN203434992U (en) | 2013-08-28 | 2013-08-28 | Networking protocol serial port test device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320530093.XU CN203434992U (en) | 2013-08-28 | 2013-08-28 | Networking protocol serial port test device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203434992U true CN203434992U (en) | 2014-02-12 |
Family
ID=50064006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320530093.XU Expired - Lifetime CN203434992U (en) | 2013-08-28 | 2013-08-28 | Networking protocol serial port test device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203434992U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105577297A (en) * | 2015-12-16 | 2016-05-11 | 京信通信技术(广州)有限公司 | Radio frequency active product test apparatus, and test method and test system thereof |
| CN107490756A (en) * | 2017-06-23 | 2017-12-19 | 江苏艾科半导体有限公司 | A kind of logic control signal system of usb bus |
| CN113157630A (en) * | 2021-04-26 | 2021-07-23 | 上海国微思尔芯技术股份有限公司 | Networking detection method and networking detection system of programmable logic array system |
| CN115459860A (en) * | 2022-07-25 | 2022-12-09 | 中国电子科技集团公司第二十九研究所 | Automatic test system and test method for mixed signal processing module |
-
2013
- 2013-08-28 CN CN201320530093.XU patent/CN203434992U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105577297A (en) * | 2015-12-16 | 2016-05-11 | 京信通信技术(广州)有限公司 | Radio frequency active product test apparatus, and test method and test system thereof |
| CN105577297B (en) * | 2015-12-16 | 2018-09-14 | 京信通信系统（中国）有限公司 | Radio frequency active product tester and its test method and test system |
| CN107490756A (en) * | 2017-06-23 | 2017-12-19 | 江苏艾科半导体有限公司 | A kind of logic control signal system of usb bus |
| CN113157630A (en) * | 2021-04-26 | 2021-07-23 | 上海国微思尔芯技术股份有限公司 | Networking detection method and networking detection system of programmable logic array system |
| CN113157630B (en) * | 2021-04-26 | 2023-11-21 | 上海思尔芯技术股份有限公司 | Networking detection method and networking detection system of programmable logic array system |
| CN115459860A (en) * | 2022-07-25 | 2022-12-09 | 中国电子科技集团公司第二十九研究所 | Automatic test system and test method for mixed signal processing module |
| CN115459860B (en) * | 2022-07-25 | 2024-10-15 | 中国电子科技集团公司第二十九研究所 | Automatic test system and test method for mixed signal processing module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104865457B (en) | Universal detection board card | |
| CN104348673B (en) | A kind of method of commissioning, master control borad and business board | |
| CN102347786B (en) | Power line narrowband carrier field test device applied to low voltage centralized meter reading system | |
| CN105573239A (en) | High speed backboard bus communication control device and method | |
| CN203434992U (en) | Networking protocol serial port test device | |
| CN103713214A (en) | Intelligent transformer station relay protection closed loop test system | |
| CN109814061B (en) | Information safety reliability detection method and device for metering terminal and intelligent electric meter | |
| CN205070993U (en) | Power line communication module testing arrangement | |
| CN203405523U (en) | Novel intelligent transformer station hand-held digital tester | |
| CN202998098U (en) | Optical module port test device | |
| CN103532618A (en) | Device and method for testing error code of optical module | |
| CN103529327B (en) | A kind of full station equipment for monitoring power quality and monitoring method being suitable for Intelligent transformer station | |
| CN202309742U (en) | Institute of electrical and electronic engineers (IEEE) 1588 tester for intelligent substation | |
| CN205004841U (en) | Intelligence substation equipment and data transmission system thereof | |
| CN105204485A (en) | Digital electric power stability control system tester | |
| CN220084922U (en) | Multi-protocol frequency hopping filter measurement control circuit and test system | |
| CN209879495U (en) | Information safety and reliability detection device for intelligent terminal and electricity meter | |
| CN204679570U (en) | Secondary equipment of intelligent converting station Commissioning Analysis platform | |
| CN202268901U (en) | Distributed controller for simple communication | |
| CN114221676A (en) | Advanced function detection platform of HPLC (high performance liquid chromatography) intelligent meter | |
| CN103063256A (en) | Railway signal measurement intelligent terminal | |
| CN110058142B (en) | 1553B bus interface circuit automatic fuse burning and adjusting plate and burning and adjusting method | |
| CN203759956U (en) | Special transformer collection information acquiring simulated training device | |
| CN203278857U (en) | Dual-path IEC61850 message receiving and transmitting device based on CRIO (Core-Router Integrated Overlay) platform | |
| CN202093391U (en) | Multifunctional digital signal input card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140212 |
|
| CX01 | Expiry of patent term |