CN107490756A - A kind of logic control signal system of usb bus - Google Patents
A kind of logic control signal system of usb bus Download PDFInfo
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- CN107490756A CN107490756A CN201710488948.XA CN201710488948A CN107490756A CN 107490756 A CN107490756 A CN 107490756A CN 201710488948 A CN201710488948 A CN 201710488948A CN 107490756 A CN107490756 A CN 107490756A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Sources (AREA)
Abstract
The invention discloses a kind of logic control signal system of usb bus, including power panel, FPGA plates and interface board；Described FPGA plates are responsible for the realization of USB2.0 bus communication protocols function, the output of multichannel output control agreement realization of decoding, multilevel logic signal is realized；Described power panel provides the various magnitudes of voltage required for normal work, and Different Logic change-over circuit operational voltage value for fpga chip in FPGA plates；Described interface board is the output pinboard of multiple independent logical passages.The logic control signal system of the usb bus of the present invention, not only industrial USB2.0 bus protocols interface all advantages are inherited, secondary development has also been carried out on this industrial bus protocol basis and with the addition of multichannel logical signal control protocol, has been that a plug and play, traffic rate reach 480MHZ while controllable more than 400 individual autonomous channels, multilevel logic signal control system.Tested simultaneously especially suitable for the more site of integrated circuit testing platform, greatly improve integrated circuit testing efficiency and integrated circuit testing speed.
Description
Technical field
The invention belongs to the control signal transmission technique field of USB2.0 data/address bus, and in particular to a kind of usb bus
Logic control signal system.
Background technology
As electronic product is penetrated into people's life every aspect, integrated circuit is flourished, thereupon
It is that more rigors are proposed to integrated circuit testing efficiency and test speed.It is now integrated electric in order to improve test speed
Solution designers are more and more tends to more site while test for drive test examination, and this just has to multichannel multilevel logic signal control system
Very tight demand desire.
Present integrated circuit test device is mostly total using PXI buses, gpib bus, usb bus, I2C, UART, network
Line etc., but they are not to provide unity logic passage or a small amount of logical channel control, are just to provide a whole set of and integrate more site
Test equipment, often its cost is very expensive, and at least more than 100 ten thousand, it is at most millions of or even more than 1,000 ten thousand.This is to many medium and small
It is a very high front capital cost input for type integrated circuit testing company, its risk factor is very high, is unfavorable for integrating
The development of electrical circuit test industry steadily, sound.
The content of the invention
The purpose of the present invention is in view of the deficienciess of the prior art, providing a kind of logic control signal system of usb bus
System, reach 480MHZ while controllable more than 400 individual autonomous channels, multilevel logic signal control system for plug and play, traffic rate
System, meet the use demand of the more site of integrated circuit testing platform while test.
Technical scheme is used by the present invention solves the above problems：
A kind of logic control signal system of usb bus, including power panel, FPGA plates and interface board；Described FPGA plates are responsible for
The realization of USB2.0 bus communication protocols function, the output of multichannel output control agreement realization of decoding, multilevel logic signal are realized；It is described
Power panel various magnitudes of voltage required for normal work, and Different Logic change-over circuit are provided for fpga chip in FPGA plates
Operational voltage value；Described interface board is the output pinboard of multiple independent logical passages.
Described power panel and FPGA plates link that terminal is orthogonal to be linked by edges of boards five to 4.2 spacing white, FPGA
Plate is linked together with interface board by horizontal mode above and below seven double 100Pin DIN connectors；In power panel power input
The power supply adaptor of the external 48V/6A specification of interface, while the USB interface of FPGA plates is connected to by a USB data line
On PC USB, the logical signal of the output pin then controlled by PC computers, output channel will export corresponding to interface board
Desired logical signal.
Described power panel and FPGA plates is combined into one piece of composition Logic Core core.
Described power panel, FPGA plates and interface board is integrated into a monoblock circuit board.
400 passages are provided with described interface board, are drawn by 8 high speeds, the more IO linkers of high precision.
Described power panel is built using switching power source chip and adjustable LDO chips.
Usb bus control module, multichannel protocol-decoding control module, multichannel output mould are set on described FPGA plates
Block and clock distribution control module；Wherein, usb bus control module is realized to CY7C16083 chip logic SECO, real
Existing industrial USB2.0 bus communication protocols mechanism, multichannel protocol-decoding control module mainly parse the passage control that PC is transmitted
System order, and corresponding channel map order is transferred to multichannel output module, multichannel output module is that control is each
Channel logic characteristics of signals, clock distribution control module is whole fpga chip internal circuit clock source, passive by outside 50MHZ
Crystal oscillator provides 50MHZ clock sources, and then carry out different frequency dividings by the PLL circuit inside FPGA produces in fpga chip with frequency multiplication
The clock source of each functional module in portion.
The signal method of flow control of the logic control signal system of described usb bus：First, in host computer（PC）Input
After channel control command, the order of input is compiled into after binary file and transmitted by USB data line by PC according to certain rule
Give USB2.0 Bus Interface Chips；The order received is passed to fpga chip, fpga chip meeting by Bus Interface Chip immediately
Order to reception is analyzed and parses received order according to multi-way contral protocol resolution module and be transferred to
Multichannel output module, multichannel can export logically high low potential according to its order to corresponding GPIO pins mouth, last corresponding
GPI0 interfaces are with exporting corresponding logic voltage characteristic value under Different Logic change-over circuit collective effect.
Beneficial effect：Compared with prior art, the logic control signal system of usb bus of the invention, it is total based on USB
Line communicates with PC, not only inherits industrial USB2.0 bus protocols interface all advantages, is also assisted in this industrial bus
Secondary development has been carried out on view basis and with the addition of multichannel logical signal control protocol, is a plug and play, traffic rate
Reach 480MHZ while controllable more than 400 individual autonomous channels, multilevel logic signal control system.Surveyed especially suitable for integrated circuit
The examination more site of platform are tested in design simultaneously, and its transmission control command is very fast, every 200 microsecond transmission control command, and one
It is secondary to control individual autonomous channel, multilevel logic signal more than 400 simultaneously, greatly improve integrated circuit testing efficiency and integrated circuit
Test speed.Exportable more than the 400 individual autonomous channel of the present invention and channel logic characteristics of signals support three major types logic, both
" 3.5V/0V ", " 2.0V/0V ", " -5V/0V ", its driving force of each passage reach 40mA, but its number of active lanes and channel logic
Characteristics of signals can be customized and cut as needed.Those are flexibly met to logical channel number ratio in this advantages characteristic very much
The more and miscellaneous scheme Design of passage output logic signal Property comparison, such as the more landscape LED of market demand drive
Dynamic, various commercial advertisement lamp indicator lamp etc..
Brief description of the drawings
Fig. 1 is the structural representation of the logic control signal system of usb bus；
Fig. 2 is the flow chart of the logic control signal system of usb bus.
Embodiment
Below in conjunction with the accompanying drawings and specific embodiment, the present invention is furture elucidated, and the present embodiment is with technical solution of the present invention
Premised under implemented, it should be understood that these embodiments are only illustrative of the invention and is not intended to limit the scope of the invention.
As shown in figure 1, the logic control signal system of the usb bus of the present invention, mainly by three pieces of circuit board groups into both electric
Source plate, FPGA plates（Fpga chip）And interface board.FPGA plates are mainly responsible for the realization of USB2.0 bus communication protocols function, multichannel
Output control agreement realization of decoding, multilevel logic signal output realization etc..Power panel mainly provides for fpga chip in FPGA plates
Various magnitudes of voltage required for normal work, as core voltage 1.5V, GPIO pin operating voltage 3.5V, and Different Logic turn
Change circuit voltage value, magnitudes of voltage different with -5.0V such as 2.0V.Interface board is mainly individual independent logical passage more than 400
Output pinboard, according to need according to certain order arrangement more than 400 individual autonomous channels, it is to region be directly facing user.
Power panel and FPGA plates mainly link that terminal is orthogonal to be linked by edges of boards five to 4.2 spacing white, FPGA plates
With interface board linked together by horizontal mode above and below seven double 100Pin DIN connectors.In power panel power input
The power supply adaptor of the external 48V/6A specification of interface, while the USB interface of FPGA plates is connected to by a USB data line
On PC USB, the logical signal of the output pin then controlled by PC computers, output channel will export corresponding to interface board
Desired logical signal.
The logical channel number and logical signal of the present invention has customizable and can cut characteristic, determines its hardware configuration cloth
Office is that comparison is flexible, is cut and is customized according to later product topology requirement.Its hardware can be by when first three block circuit board
It is changed into two pieces, both power panel and FPGA plates were combined into one piece of composition Logic Core core, as long as under product dimensions of mechanical structures allows,
Three pieces are even combined into one piece of one monoblock circuit board of composition.
400 multichannels are drawn by the more IO linkers of 8 high speeds, high precision on interface board, such as the J1-J8 in Fig. 1, its
Logical signal characteristic arrangement all same, equivalent to 8 slots on each linker.In addition, the passage lead-out mode is also can be with
Any customization and cutting, are not limited to concrete form.
The circuit function of the logic control signal system of the usb bus, mainly by power unit, fpga chip part, connect
Mouth output par, c is formed.Power unit mainly uses the switching power source chip of TI companies（TPS54560）With adjustable LDO chips
（LM1117）Built Deng discrete device.The function of fpga chip part is completely by usb bus control module, multichannel agreement
Decoding control block, multichannel output module and clock distribution control module are realized；Usb bus control module is mainly realized pair
CY7C16083 chip logic SECO, realize industrial USB2.0 bus communication protocols mechanism, multichannel protocol-decoding control mould
Block mainly parses the channel control command that PC is transmitted, and corresponding channel map order is transferred to multichannel output mould
Block, multichannel output module are each channel logic characteristics of signals of control, and clock distribution control module is in whole fpga chip
Portion circuit clock source, it provides 50MHZ clock sources without source crystal oscillator by outside 50MHZ, then entered by the PLL circuit inside FPGA
The different frequency dividings of row produce the clock source of each functional module inside fpga chip with frequency multiplication.
The signal flow control process of the logic control signal system of the usb bus is：First, in host computer（PC）Input is logical
After road control command, the order of input is compiled into after binary file and is transferred to by USB data line by PC according to certain rule
USB2.0 Bus Interface Chips（CY7C16083）.The order received is passed to fpga chip by Bus Interface Chip immediately,
Fpga chip can be analyzed the order of reception and received life is parsed according to multi-way contral protocol resolution module
Making and be transferred to multichannel output module, multichannel can export logically high low potential according to its order to corresponding GPIO pins mouth,
Last corresponding GPI0 interfaces are with exporting corresponding logic voltage characteristic value under Different Logic change-over circuit collective effect.
For order compiling rule on PC as shown in Fig. 2 its framework is divided into three layers, first layer is by ClsADIO_USB class structures
Into, and the base class of whole logic control signal system.It includes four member functions, respectively USBConnect,
InitSetting, Enable and SignalControlSet.Tri- members of its USBConnect, InitSetting and Enable
Function is mainly used to describe USB device correlation base attribute, and SignalControlSet member functions are mainly used to describe USB
Functions of the equipments characteristic.USBConnect member functions are mainly used to judge whether its USB device is mounted on PC usb bus,
InitSetting member functions are mainly used to initialize USB device relevant default attribute, and Enable member functions are mainly used to make
Can USB equipment, SignalControlSet member functions be to one of USB device function extension, for realize multichannel,
Multilevel logic signal control system.
The second layer be by ClsSwitch_RDT, ClsSwitch_HDT, ClsSwitch_WDT, ClsSwitch_SDT,
Seven subclasses such as ClsSwitch_S3T, ClsSwitch_H4T and ClsSwitch_MTX are formed.This layer mainly realizes basic unit's number
According to data converting function between the pure hardware physical layer of bottom, both with being established in pure hardware physical characteristic on base layer data level
One mapping mechanism one by one, realize multichannel, multilevel logic signal control unique function control.ClsSwitch_XXX subclasses are all
Inherit in member function SignalControlSet from first layer ClsADIO_USB base class.ClsSwitch_XXX subclasses
Above-mentioned more independent logical port numbers according to alias in the base layer data that is grouped of its hardware circuit control distinct device.According to
Demand second layer subclass can be arbitrarily individual, tentative to be divided into seven classes according to control function on actual hardware.
Third layer is several logical by Iswitch_SP2T, Iswitch_SP3T, Iswitch_SP4T, Iswitch_SP6T etc.
Formed with class, this layer is exactly pure hardware physical layer.2,3,4,6 numerals in its Iswitch_SPXT selected by " X " are tables
It is shown with several autonomous channel numbers.The member function of Iswitch_SPXT (X=2,3,4,6) several general class is by an Init
（）With several RFX0 ()（X=2、3、4、6）Form.Its Init（）Member function is primarily used to initialize related hardware acquiescence
Characteristic, RFX0 ()（X=2、3、4、6）Function provides different channel logic electrical characteristics.
The logic control signal system of the usb bus of the present invention, is a general, multichannel, and multilevel logic signal controls
System.The present invention uses FPGA technology, and using the more characteristics of fpga chip GPIO pins, simultaneously basis cascade by three pieces of chips
Demand is in the different logical transition circuit of FPGA GPIO pin carries, it is possible to realizes multichannel, multilevel logic signal output spy
Property.Three major types voltage logic value can be supported at present（Its logically high low amplitude characteristic be respectively " 3.5V/0V ", " 2.0V/0V ",
“0V/-5V”）, more than 400 individual independent logical passages.But in theory, as long as changing according to demand more logical inside existing fpga chip
Road protocol-decoding control module, multichannel output module and the desired passage of fpga chip can realization for cascading varying number
Number, both port number was infinite expanding, and plug-in logical transition circuit carry Different Logic can also change electricity according to demand
Different Logic signal output characteristic is realized on road, and both output logic signal characteristic was also expansible such as 3.3V, 1.8V, 1.5V
Logic, or even single-ended it is converted into differential logic.
The logic control signal system of the usb bus of the present invention, is to be communicated based on usb bus with PC, its USB
Bus is using inside a CY7C68013A chips in CYPRESS companies EZ-USB FXL2LP series and fpga chip
The buses of USB 2.0 are realized in the combination of usb bus control module.It not only inherits industrial USB2.0 bus protocols interface, and all are excellent
Gesture, such as traffic rate reach 480MHZ, Interfaces connectivity supports plug and play, also in the enterprising of this industrial bus protocol basis
Secondary development of having gone with the addition of multichannel logical signal control protocol, be that a plug and play, traffic rate reach 480MHZ, same
When controllable more than 400 individual autonomous channels, multilevel logic signal control system.
The logic control signal system of the usb bus of the present invention, is mainly used for the more site of integrated circuit testing platform
Test simultaneously in design.Its transmission control command is very fast, and every 200 microsecond transmits control command, can once control simultaneously
Individual autonomous channel, multilevel logic signal more than 400, greatly improve integrated circuit testing efficiency and integrated circuit testing speed.
Exportable more than the 400 individual autonomous channel of the present invention and channel logic characteristics of signals supports three major types logic, both " 3.5V/
0V ", " 2.0V/0V ", " -5V/0V ", its driving force of each passage reaches 40mA, but its number of active lanes and channel logic signal are special
Property can be customized and cut as needed.This advantages characteristic be flexibly met very much those it is relatively more to logical channel number with
The miscellaneous scheme Design of passage output logic signal Property comparison, such as the driving of the more landscape LED of the market demand, various
Commercial advertisement lamp indicator lamp etc..
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (8)
- A kind of 1. logic control signal system of usb bus, it is characterised in that：Including power panel, FPGA plates and interface board；It is described FPGA plates be responsible for the realization of USB2.0 bus communication protocols function, multichannel output control agreement realization of decoding, multilevel logic signal Output is realized；Described power panel provides the various magnitudes of voltage required for normal work for fpga chip in FPGA plates, and not With logical transition circuit voltage value；Described interface board is the output pinboard of multiple independent logical passages.
- 2. the logic control signal system of usb bus according to claim 1, it is characterised in that：Described power panel with FPGA plates are double by seven with interface board to the white link orthogonal link of terminal of 4.2 spacing, FPGA plates by edges of boards five Horizontal mode links together 100Pin DIN connectors up and down；In the external 48V/6A specification of power panel power input interface Power supply adaptor, while the USB interface of FPGA plates is connected on PC USB by a USB data line, then passes through PC electricity The logical signal of the output pin of brain control, output channel will export desired logical signal corresponding to interface board.
- 3. the logic control signal system of usb bus according to claim 1, it is characterised in that：Described power panel and FPGA plates are combined into one piece of composition Logic Core core.
- 4. the logic control signal system of usb bus according to claim 1, it is characterised in that：Described power panel, FPGA plates and interface board are integrated into a monoblock circuit board.
- 5. the logic control signal system of usb bus according to claim 1, it is characterised in that：In described interface board 400 passages are provided with, are drawn by 8 high speeds, the more IO linkers of high precision.
- 6. the logic control signal system of usb bus according to claim 1, it is characterised in that：Described power panel is adopted Built with switching power source chip and adjustable LDO chips.
- 7. the logic control signal system of usb bus according to claim 1, it is characterised in that：In described FPGA plates On set usb bus control module, multichannel protocol-decoding control module, multichannel output module and clock distribution control mould Block；Wherein, usb bus control module is realized to CY7C16083 chip logic SECO, realizes industrial USB2.0 bus communications Protocol, multichannel protocol-decoding control module mainly parse the channel control command that PC is transmitted, and corresponding Channel map order is transferred to multichannel output module, and multichannel output module is each channel logic characteristics of signals of control, when Clock distribution control module is whole fpga chip internal circuit clock source, and 50MHZ clocks are provided without source crystal oscillator by outside 50MHZ Source, then carry out different frequency dividings by the PLL circuit inside FPGA and produce each functional module inside fpga chip with frequency multiplication Clock source.
- 8. the signal method of flow control of the logic control signal system of the usb bus described in claim 1, it is characterised in that：It is first First, in host computer（PC）After input channel control command, the order of input is compiled into binary file by PC according to certain rule USB2.0 Bus Interface Chips are transferred to by USB data line afterwards；Bus Interface Chip immediately passes to the order received Fpga chip, fpga chip can be analyzed the order of reception and parsed according to multi-way contral protocol resolution module and be connect The order that receives simultaneously is transferred to multichannel output module, and multichannel can export logically high according to its order to corresponding GPIO pins mouth Low potential, last corresponding GPI0 interfaces are with exporting corresponding logic voltage characteristic value under Different Logic change-over circuit collective effect.
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| CN114510447A (en) * | 2021-05-12 | 2022-05-17 | 广东高云半导体科技股份有限公司 | Method and apparatus for providing a SERDES block for an FPGA that facilitates high speed data transfer |
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| CN114510447A (en) * | 2021-05-12 | 2022-05-17 | 广东高云半导体科技股份有限公司 | Method and apparatus for providing a SERDES block for an FPGA that facilitates high speed data transfer |
| CN114510447B (en) * | 2021-05-12 | 2024-05-17 | 广东高云半导体科技股份有限公司 | Method and apparatus for providing SERDES blocks for FPGAs that facilitate high speed data transfer |
| CN114430287A (en) * | 2022-01-27 | 2022-05-03 | 杭州长川科技股份有限公司 | Control method of multi-channel control system and multi-channel control system |
| CN114430287B (en) * | 2022-01-27 | 2024-03-01 | 杭州长川科技股份有限公司 | Control method of multichannel control system and multichannel control system |
| CN114860635A (en) * | 2022-07-07 | 2022-08-05 | 北京智芯半导体科技有限公司 | General input/output interface control method, device, storage medium and circuit board |
| CN115575792A (en) * | 2022-09-08 | 2023-01-06 | 杭州国磊半导体设备有限公司 | ATE test equipment with multi-backboard architecture |
| CN115575792B (en) * | 2022-09-08 | 2023-06-30 | 杭州国磊半导体设备有限公司 | ATE test equipment with multi-backboard framework |
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Application publication date: 20171219 |