The utility model content
The purpose of the utility model provides a kind of IEEE1588 tester that is used for intelligent substation; Not enough to solve current intelligent substation IEEE1588 product test means in IEEE1588 stipulations uniformity test, functional test, performance test, a series of difficult problems such as location of mistake difficulty during the narrower and test of abnormality test coverage rate.
For realizing above-mentioned purpose, a kind of IEEE1588 tester that is used for intelligent substation of the utility model comprises:
The test main control module; Reach the fpga chip, SDRAM chip and the FLASH chip that are connected with its communication by dsp chip and constitute, this test main control module is used to receive and dispatch IEEE1588 message, the various forms of input/output signals of analyzing and processing, processing satellite clock signal and carries out the IEEE1588 test function;
The optical Ethernet module is used for the test interface as IEEE1588, through pps pulse per second signal alignment test main control module output pulse per second (PPS) time signal, sends IEEE1588 message timestamp information through the time order wire to the test main control module respectively;
The electricity ethernet module is as the debugging interface of IEEE1588 tester;
The signal input/output module is used for importing various forms of pulse per second (PPS)s and opening into leaving signal to the test main control module, and the signal that sent by the test main control module of output;
The satellite clock signal receiving module is used to receive outside satellite clock signal, and this signal is sent to the test main control module;
Display module is used to show temporal information and indicator light information;
Said optical Ethernet module, electric ethernet module, signal input/output module, satellite clock signal receiving module, display module link to each other with the test main control module respectively.
Further, said optical Ethernet module is two.
Said signal input/output module comprise the BNC signal open into leave module, the signal of telecommunication is opened into leaving module and light signal and is opened into leaving module.
Said satellite-signal receiver module comprises the gps satellite receiver module.
Said display module comprises 7 sections charactrons and at least 8 LED lights that time showing is used.
Dsp chip adopts the TMS320DM642A type in the said test main control module, and fpga chip adopts the XC3S500E type.
The physical chip of said optical Ethernet module adopts the DP83640 chip, and the pulse per second (PPS) delivery outlet that the general input and output pin GPIO that sets this DP83640 chip is the chip clock outputs to the respective pins of testing FPGA in the main control module.
A kind of IEEE1588 tester that is used for intelligent substation of the utility model comprises test main control module and coupled optical Ethernet module, electric ethernet module, signal input/output module, satellite clock signal receiving module and display module; The test main control module can in time be received and dispatched IEEE1588 message, the various forms of input/output signals of analyzing and processing, processing satellite clock signal and carry out the IEEE1588 test function; The IEEE1588 tester can be used as the testing tool of IEEE1588 stipulations uniformity test, performance test and abnormality test; Efficiently solve IEEE1588 product test means deficiency in the current intelligent substation; A series of difficult problems such as the narrower and when test location of mistake difficulty of abnormality test coverage rate have important practical value.
Embodiment
Specify with the technical scheme of instantiation with reference to the accompanying drawings the utility model.
As shown in Figure 1, the IEEE1588 tester that is used for intelligent substation by 101,2 of main control modules of test have the optical Ethernet communication module 102 of IEEE1588 time synchronized function, common electrical ethernet module 103, signal input/output module 104, satellite clock signal receiving module 105 and a display module 106 are formed.
Test main control module 101 links to each other with 2 optical Ethernet communication modules with IEEE1588 time synchronized function 102, common electrical ethernet module 103, signal input/output module 104, satellite clock signal receiving module 105 and a display module 106 respectively, and test main control module 101 is received and dispatched IEEE1588 messages, the various forms of input/output signals of analyzing and processing, processing satellite clock signal and carried out all IEEE1588 test functions.
Test main control module 101 has between the optical Ethernet communication module 102 of IEEE1588 time synchronized function with each and is provided with: 1) pps pulse per second signal line is used for the ethernet communication module and exports the pulse per second (PPS) time signal to the test main control module; 2) time order wire is used for the ethernet communication module and sends IEEE1588 message timestamp information to the test main control module.
Ethernet communication module 102 with IEEE1588 time synchronized function links to each other with test main control module 101, as the test interface of IEEE1588 tester.
Common electrical ethernet module 103 links to each other with test main control module 101, as the debugging interface of IEEE1588 tester.
Signal input/output module 104 links to each other with test main control module 101, be used for importing various clock signals and opening into leaving signal to the test main control module, and output is by testing the various signals that main control module sends.
Satellite clock signal receiving module 105 links to each other with test main control module 101, is used to receive outside satellite clock signal, and this signal is sent to the test main control module.
Display module 106 links to each other with test main control module 101, shows temporal information and indicator light information.
Test main control module 101 comprises dsp chip, fpga chip, SDRAM chip, FLASH chip at least, and communication is connected dsp chip as shown in the figure with the FLASH chip with fpga chip, SDRAM chip respectively.The hardware structure of test main control module adopts the high performance DSP TMS320DM642A (dominant frequency 600M) and the Spartan-3E Series FPGA chip XC3S500E that matches company of SEL of Texas Instruments, adopts that this framework communication speed is fast, system stability is reliable.Establish the IEEE1588 testing engine in the dsp chip; All test this tester under all control of system controlling software on computers, are responsible for specifically carrying out and will testing real time data and execution result by the IEEE1588 testing engine Executive Module on the tester and are sent to system controlling software demonstration or analysis.The IEEE1588 testing engine is supported IEEE1588-2008 standard and IEEE C37.238 standard (power industry IEEE1588 Profile); Support the smart machine of any support IEEE1588 agreement in the intelligent substation; Therefore this IEEE1588 tester is applicable to power industry, especially intelligent substation.
Each physical chip of luminiferous ether network interface with ethernet module 102 of IEEE1588 time synchronized function adopts the DP83640 chip of National Semiconductor; Can catch the accurate transmission of IEEE1588 message or receive markers; Markers resolution is 8ns, can satisfy the testing requirement of supporting the intelligent apparatus of IEEE1588 agreement in the intelligent substation fully; The pulse per second (PPS) delivery outlet that the general input and output pin GPIO of definable DP83640 chip is the chip clock; Output in the FPGA respective pins in the test main control module; Can be used to keep watch on this pulse per second (PPS) during test; When for example the conduct of light network interface was from clock, the time difference between the pulse per second (PPS) rising edge of pulse per second (PPS) rising edge and IEEE1588 master clock was exactly that this is from the clock jitter of clock with respect to the IEEE1588 master clock.1 RJ45 electricity Ethernet interface is used as test interface, can be connected to the personal computer network interface.
Signal input/output module 104 is connected through DIN connector with test main control module 101.Signal input/output module 104 comprises that BNC opens into leaving module, establishes by cable into leaving module, and light is opened into leaving module.Consider the principle that strong and weak electricity separates, side circuit can be divided into BNC when realizing and open into the digital output circuit plate, establishes by cable into digital output circuit plate, light and open into the digital output circuit plate; Open the digital output circuit plate for these 3 and be connected, after level conversion, deliver to signal in the FPGA pin of test main control module from panel interface through DIN connector with various switching value input/output interfaces on the tester front panel.
GPS receiver module in the satellite clock signal receiving module 105 is also delivered to test main control module 101 to GPS pps pulse per second signal that receives and serial ports time signal, supplies dsp chip and fpga chip to handle; Big Dipper receiver module spare interface in the satellite clock signal receiving module 105.
Display module 106 comprises 7 sections charactrons and at least 8 LED lights that time showing is used.The time showing charactron shows the time from " date " form of gps satellite signal, LED light display synchronization, step-out, satellite-signal pulse per second (PPS), light network interface A master state, light network interface A slave state, light network interface B master state, light network interface B slave state.
When using, tester needs to realize test function that the test analysis software of IEEE1588 tester is installed on the computer, and computer is connected through the RJ45 twisted-pair feeder with tester, test main control module in the tester and test analysis software communication by means of computer.
As shown in Figure 2, the test operation flow process of the utility model IEEE1588 tester is following:
Step 10: test environment is prepared;
At first connect IEEE1588 tester and equipment under test, connect the network interface of IEEE1588 test analysis software place computer and the debugging electricity mouth of IEEE1588 tester with optical fiber.
Step 20: in IEEE1588 test analysis software, select category of test;
Step 30: in selected category of test, select concrete test cases;
Step 40: carry out selected test cases;
In test process, tester is delivered to IEEE1588 test analysis software to test process information, can keep watch on whole test process through the software graphic interface, possibly need the user to confirm to make test to proceed in case of necessity.
Step 50:IEEE1588 test analysis software provides the conclusion whether test cases passes through;
After test is accomplished; IEEE1588 test analysis software provides the conclusion of this test cases through still not passing through; If do not pass through, provide the intransitable reason of this test cases, and provide the clause that the IEEE1588 agreement realizes and the IEEE1588 agreement is not inconsistent of equipment under test.
Step 60: carry out next test cases if desired, to step 30, otherwise to step 70.
Step 70:IEEE1588 test analysis software generates test report.
After all test cases that the user selects were accomplished, IEEE1588 test analysis software can produce a test report, can save as electronic document and also can print.
The detailed description of step 20 is following in the above-mentioned test operation flow process:
As shown in Figure 3, get into IEEE1588 uniformity test interfaces 210 by the main interface of test 201, master clock uniformity test module 211 times, select certain test cases after, begin to carry out this test cases; From clock uniformity test module 212 times, select certain test cases after, begin to carry out this test cases; Transparent clock uniformity test module 213 times, at first selecting transparent clock to be tested is E2E transparent clock or P2P transparent clock, selects corresponding test cases then, gets into test process.
When getting into IEEE1588 functional test interface 220 by the main interface 201 of test; Master clock functional test module 221 times; Can carry out the master clock functional test,, can carry out from the clock functional test from clock functional test module 222 times; Transparent clock functional test module 223 times, can carry out the transparent clock functional test.
When getting into IEEE1588 performance test interface 230 by the main interface 201 of test; Master clock performance test module 231 times; Can carry out master clock precision and time receiving performance test,, can carry out from clock precision and time receiving performance test from clock performance test module 232 times; Transparent clock performance test module 233 times, can carry out the test of transparent clock residence time.
Above content is the further explain that combines concrete preferred implementation that the utility model is done, and can not assert that the practical implementation of the utility model is confined to these explanations.Those of ordinary skill for technical field under the utility model; Under the prerequisite that does not break away from the utility model design, make some alternative or obvious modification that are equal to; And performance or purposes are identical, then should be regarded as belonging to the protection range that the utility model is confirmed by claims of being submitted to.