CN106776467A - For the SPI FLASH control chips of order reception system - Google Patents
For the SPI FLASH control chips of order reception system Download PDFInfo
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- CN106776467A CN106776467A CN201611156694.3A CN201611156694A CN106776467A CN 106776467 A CN106776467 A CN 106776467A CN 201611156694 A CN201611156694 A CN 201611156694A CN 106776467 A CN106776467 A CN 106776467A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
- G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
- G06F15/7846—On-chip cache and off-chip main memory
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a kind of SPI FLASH control chips for order reception system, state machine module instruction FLASH interface modules carry out read operation to outside SPI FLASH；FLASH interface modules receive digital data and pass to dual port RAM module by word receiver module；By data check module checking signal correctly or incorrectly, if mistake, FLASH interface modules carry out reading data manipulation to state machine module to outside SPI FLASH again；If correct, state machine module instruction decoding chip interface module carries out data read operation to dual port RAM module.The present invention disclosure satisfy that the application demand of receiver instruction system, and flexibility is stronger, and transmission stabilization, transmission signal line is few, and area is small and application is simple, has taken into account the requirement of the device inside utilization of resources, power consumption and batch production.
Description
Technical field
The invention belongs to technical field of electronic components, more particularly to a kind of digit chip, and in particular to order receives system
System SPI FLASH control chips, can realize the need of order reception system inside handshake data flexible configuration by the control chip
Ask.
Background technology
Existing order reception system is collectively formed by power management module, decoding chip and receiver, the work between three
Make principle as shown in Figure 1.Realized according to this set system, decoding chip receives serial data, exported by the data lines of SPI tri- and held
Whether consistent hand data message, receiver sets by contrasting handshake data information and inside, it is determined whether reply decoding chip
Response operation.Then had the following disadvantages in the system application：
1st, because receiver receives manufacturing process, the difference of method during batch production, number of being shaken hands inside it is caused
It is believed that breath is different, and if then decoding chip cannot be communicated with receiver module using fixed handshake data information so that
System is caused not respond to.
2nd, controller chip function is realized using the high power consumption component such as FPGA, single-chip microcomputer, the level of resources utilization is relatively low, is sealed
Dress volume is also big compared with common IC chip.The high and low power consumption of design resource utilization, the component of small size are lifting military equipment realities
With the developing direction of property.
3rd, using external device, the system is directly applied to, there is risk on using confidentiality, and face the wind of embargo
Danger.Therefore the SPI FLASH control chips of the independent development system, significant in component production domesticization.
The content of the invention
In order to overcome the deficiencies in the prior art, the present invention to provide a kind of SPI FLASH controls for order reception system
Chip, has the advantages that data transfer is stable, area is small, holding wire is few, by controlling outside decoding chip according to SPI FLASH
SPI FLASH come realize decoding chip inside handshake data configuration, so as to realize decoding chip in order reception system
Application requirement.
The technical solution adopted for the present invention to solve the technical problems is：A kind of SPI for order reception system
FLASH control chips, including frequency division module, dual port RAM module, data check module, FLASH interface modules, state machine module
With decoding chip interface module.
Described FLASH interface modules include shift register, word receiver module and reading instruction sending module；Described solution
Code chip interface module includes reading address sending module and shift register；Described frequency division module is produced using decoding chip clock
Raw frequency-dividing clock, there is provided to dual port RAM module, data check module, FLASH interface modules, state machine module and decoding chip
Interface module；Described state machine module sends reading instruction signal and gives FLASH interface modules, the reading instruction of FLASH interface modules
Sending module exports three SPI signals, including piece choosing, clock and data input, and read operation is carried out to outside SPI FLASH；
The shift register of FLASH interface modules is believed outside SPI FLASH data outputs according to SPI clocks, the chip selection signal for producing
Number sampled and serioparallel exchange, finish receiving a digital data and pass to word receiver module；Word receiver module is connect by word
Harvest into digital data signal by digital data pass to dual port RAM module carry out digital data reception store；Data receiver is completed
Afterwards, state machine module passes through data check module checking signal correctly or incorrectly, if check errors, state machine module is indicated
FLASH interface modules close write enable signal, resend SPI FLASH read operations instruction, and outside SPI FLASH are read
Data manipulation；If verification is correct, state machine module is opened and reads to enable signal, indicates decoding chip interface module to prepare to twoport
RAM module carries out data read operation, and decoding chip interface module reads address by providing, and coordinates and reads clock and read to enable letter
The digital data of number control dual port RAM module output storage, reads address sending module receives the output of dual port RAM module and line number
According to, the shift register of decoding chip interface module is passed to, three SPI signals are produced, meet decoding chip handshake data and write
Enter timing requirements, so as to realize the purpose of internal data configuration.
The beneficial effects of the invention are as follows：
1) present invention is due to by the way of SPI FLASH and control chip, overcoming decoding chip inside handshake data
The deficiency that information cannot be changed, disclosure satisfy that the application demand of receiver instruction system, and flexibility is stronger.
2) present invention is because by the way of SPI FLASH and control chip, wherein SPI FLASH have data transfer steady
Fixed, transmission signal line is few, area is small and applies simple advantage, while meeting SPI FLASH and the reading of decoding chip SPI data
Write the timing requirements between sequential so that SPI FLASH can be directly applied to order reception system.
3) present invention is due to by the way of SPI FLASH and controller chip, on the one hand ensure that order reception system
The localization rate of parts and components of application requirement, has on the other hand taken into account the requirement of the device inside utilization of resources, power consumption and batch production.
Brief description of the drawings
Fig. 1 is order reception system fundamental diagram；
Fig. 2 is SPI FLASH control chip application block diagrams of the present invention；
Fig. 3 is SPI FLASH control chip theory diagrams.
Specific embodiment
The present invention is further described with reference to the accompanying drawings and examples, and the present invention includes but are not limited to following implementations
Example.
SPI FLASH control chips of the invention, be integrated with frequency division module, dual port RAM module, data check module,
FLASH interface modules, state machine module and decoding chip interface module.When frequency division module produces frequency dividing using decoding chip clock
Clock, there is provided give control chip inside modules；State machine module reading instruction signal designation FLASH interface modules send reading and refer to
Order, three SPI signals (piece choosing, clock, data input) of output carry out read operation to outside SPI FLASH；Reading instruction has sent
Into state machine module write enable signal indicates dual port RAM module to open and receives enable, is ready for digital data reception；Data connect
Harvest into, state machine module is read to enable signal designation dual port RAM module opening transmission enable, is ready for the transmission of digital data；
State machine module sends and enables signal designation decoding chip interface module opening data is activation enable, prepares three SPI letters of output
Number (piece choosing, clock, data input), handshake data write operation is carried out to decoding chip.FLASH interface modules export three
SPI signal (piece choosing, clock, data input) carries out read operation to outside SPI FLASH, by the conversion of SPI FLASH serial datas
It is parallel digital data.The digital data that data check module will be received is verified, and after having received all data, judges that data are
It is no correct.Dual port RAM module is enabled and the digital data that will receive of writing address signal is stored according to writing；Make and read according to reading
Data storage is exported and gives decoding chip interface module by address signal.The digital data that decoding chip interface module will be received is carried out
Parallel-serial conversion, exports three SPI data-signals (piece choosing, clock, data input), and handshake data write-in behaviour is carried out to decoding chip
Make.
Above-mentioned SPI FLASH control chips, realize the reading of SPI FLASH data, the write-in of decoding chip data, it is ensured that life
Make reception system handshake data set consistent with decoding chip inside handshake data, overcome because of manufacturing process error, SPI
Both handshaking informations are inconsistent caused by FLASH and decoding chip timing requirements such as are unsatisfactory at the reason, and order reception system cannot
The deficiency of normal work.
As shown in figure 3, the chip of the embodiment of the present invention includes frequency division module 1, dual port RAM module 2, FLASH interface modules
3rd, data check 4, state machine module 5 and decoding chip interface module 6.Wherein frequency division module 1 is provided using decoding chip
Clock input produces frequency-dividing clock, there is provided give control chip inside modules；Dual port RAM module 2 uses dual port RAM form,
For storing handshake data；FLASH interface modules 3 include that reading instruction sends 7, word receiver module 8 and shift register 9, read to refer to
Make sending module 7 for the transmission reading instruction signal of user equipment module 5, sent out to SPI FLASH by three SPI signal lines
Send reading instruction；Shift register 9 realizes the serioparallel exchange of SPI data, will receive input serial data signal and is converted into parallel
Digital data；The digital data that receiver module 8 will be received passes to dual port RAM module, carries out data storage.Data check module 4
The digital data that will be received is verified, and after having received all data, judges whether data are correct.State machine module 5 is by reading
Command signal indicates FLASH interface modules 3 to send reading instruction, and three SPI signals (piece choosing, clock, data input) of output are externally
Portion SPI FLASH carry out read operation；Reading instruction is sent completely, and the write enable signal of state machine module 5 indicates dual port RAM module 2 dozens
Open reception to enable, be ready for digital data reception；Data receiver is completed, and state machine module 5 is read to enable signal designation dual port RAM mould
Block 2 is opened to send and enabled, and is ready for the transmission of digital data；State machine module 5 enables signal designation decoding chip by sending
Interface module 6 is opened data is activation and is enabled, and prepares three SPI signals (piece choosing, clock, data input) of output, to decoding chip
Carry out handshake data write operation.Decoding chip interface module 6 includes reading address sending module 10 and shift register 11, reads ground
Location sending module 10 sends to dual port RAM module reads address signal, and receives digital data；Shift register 11 completes control chip
Internal parallel-serial conversion, output meets three SPI signals of decoding chip requirement (piece choosing, clock, data input) write timing.
The operation principle of whole chip is as follows：After electrification reset, state machine module 5 is by sending reading instruction signal designation
FLASH interface modules 3 send reading instruction, and it is right that reading instruction sending module 7 exports three SPI signals (piece choosing, clock, data input)
Outside SPI FLASH carry out read operation；Shift register 9 according to produce SPI clocks, chip selection signal, to outside SPI FLASH
Data output signal is sampled and serioparallel exchange；Shift register 9 finishes receiving a digital data and passes to word receiver module
8；Word receiver module 8 is finished receiving by word and digital data is passed into dual port RAM module 2 with digital data signal carries out digital data
Receive storage；After the completion of data receiver, state machine module 5 verifies correct/error signal designation state by data check module 4
Machine module 5 carries out data preservation or data abandon operation.Check errors, state machine module 5 indicates FLASH interface modules to close
Write enable signal, resends SPI FLASH read operations instruction, and reading data manipulation is re-started to outside SPI FLASH.Verification
Correctly, state machine module 5 opens reading enable signal designation decoding chip interface module 6 and prepares to carry out data to dual port RAM module 2
Read operation, decoding chip interface module 6 reads address by providing, and coordinates and reads clock and read to enable signal control dual port RAM
The digital data of the output storage of module 2, reads the parallel data that address sending module 10 receives the output of dual port RAM module 2, passes to shifting
Bit register 11 produces three SPI signals (piece choosing, clock, data input), and meeting decoding chip handshake data write timing will
Ask, so as to realize the purpose of internal data configuration.
Integrated chip of the present invention frequency division module, dual port RAM module, data check module, FLASH interface modules, state
Machine module and decoding chip interface module, logic is simple, area occupied is small, overcomes due to order reception system handshake data letter
Breath is uncertain and SPI FLASH and decoding chip SPI data write timing differences cause decoding chip and the receiver cannot to lead to
The deficiency of letter, enhances the flexibility of receiver instruction system application so that system and device batch production is possibly realized.
Claims (1)
1. a kind of SPI FLASH control chips for order reception system, including frequency division module, dual port RAM module, data school
Test module, FLASH interface modules, state machine module and decoding chip interface module, it is characterised in that：Described FLASH interfaces
Module includes shift register, word receiver module and reading instruction sending module；Described decoding chip interface module includes reading ground
Location sending module and shift register；Described frequency division module produces frequency-dividing clock using decoding chip clock, there is provided to twoport
RAM module, data check module, FLASH interface modules, state machine module and decoding chip interface module；Described state machine
Module sends reading instruction signal and exports three SPI letters to the reading instruction sending module of FLASH interface modules, FLASH interface modules
Number, including piece choosing, clock and data input, read operation is carried out to outside SPI FLASH；The shift LD of FLASH interface modules
Device is sampled and serioparallel exchange according to the SPI clocks, the chip selection signal that produce to outside SPI FLASH data output signals, is connect
It is to pass to word receiver module to harvest into a digital data；Word receiver module is finished receiving number of words with digital data signal by word
The reception storage of digital data is carried out according to dual port RAM module is passed to；After the completion of data receiver, state machine module passes through data check
Correctly or incorrectly, if check errors, state machine module indicates FLASH interface modules to close write enable signal to module checking signal,
SPI FLASH read operations instruction is resend, reading data manipulation is carried out to outside SPI FLASH；If verification is correct, state machine mould
Block is opened and reads to enable signal, indicates decoding chip interface module to prepare to carry out dual port RAM module data read operation, decodes core
Piece interface module reads address by providing, and coordinates and reads clock and read to enable the word of signal control dual port RAM module output storage
Data, read the parallel data that address sending module receives the output of dual port RAM module, pass to the displacement of decoding chip interface module
Register, produces three SPI signals, meets decoding chip handshake data write timing requirement, so as to realize that internal data is configured
Purpose.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611156694.3A CN106776467B (en) | 2016-12-15 | 2016-12-15 | SPI FLASH control chip for command receiving system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611156694.3A CN106776467B (en) | 2016-12-15 | 2016-12-15 | SPI FLASH control chip for command receiving system |
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| CN106776467A true CN106776467A (en) | 2017-05-31 |
| CN106776467B CN106776467B (en) | 2020-04-28 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111274755A (en) * | 2020-01-16 | 2020-06-12 | 合肥磐芯电子有限公司 | Multifunctional MCU interface circuit |
| CN111506529A (en) * | 2020-06-30 | 2020-08-07 | 深圳市芯天下技术有限公司 | High-speed SPI instruction response circuit applied to F L ASH |
| CN112542187A (en) * | 2020-12-31 | 2021-03-23 | 深圳市芯天下技术有限公司 | Circuit for reading ID and chip state at high speed and flash memory |
| CN112579486A (en) * | 2020-12-14 | 2021-03-30 | 上海创远仪器技术股份有限公司 | System for realizing cross-clock-domain communication based on dual-port RAM |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111274755A (en) * | 2020-01-16 | 2020-06-12 | 合肥磐芯电子有限公司 | Multifunctional MCU interface circuit |
| CN111274755B (en) * | 2020-01-16 | 2024-02-06 | 合肥磐芯电子有限公司 | Multi-functional MCU interface circuit |
| CN111506529A (en) * | 2020-06-30 | 2020-08-07 | 深圳市芯天下技术有限公司 | High-speed SPI instruction response circuit applied to F L ASH |
| CN112579486A (en) * | 2020-12-14 | 2021-03-30 | 上海创远仪器技术股份有限公司 | System for realizing cross-clock-domain communication based on dual-port RAM |
| CN112579486B (en) * | 2020-12-14 | 2023-02-21 | 上海创远仪器技术股份有限公司 | System for realizing cross-clock-domain communication based on dual-port RAM |
| CN112542187A (en) * | 2020-12-31 | 2021-03-23 | 深圳市芯天下技术有限公司 | Circuit for reading ID and chip state at high speed and flash memory |
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| CN106776467B (en) | 2020-04-28 |
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