CN105355229A - Write circuit and read circuit of asynchronous circuit system for synchronous random-access memory - Google Patents
Write circuit and read circuit of asynchronous circuit system for synchronous random-access memory Download PDFInfo
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- CN105355229A CN105355229A CN201510718532.3A CN201510718532A CN105355229A CN 105355229 A CN105355229 A CN 105355229A CN 201510718532 A CN201510718532 A CN 201510718532A CN 105355229 A CN105355229 A CN 105355229A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
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Abstract
The present invention provides a write circuit and a read circuit of an asynchronous circuit system for a synchronous random-access memory. The asynchronous circuit system uses a dual-track four-phase handshake protocol. The write circuit comprises: a circuit part of write allowance startup, a circuit part of write address and write data conversion and transmission, and a circuit part of write startup and write completion response. The read circuit comprises: a circuit part of read allowance startup, a circuit part of read address and read data conversion and transmission, and a circuit part of read startup and read completion response. After the write circuit and the read circuit provided by the present invention are connected, read and write of the asynchronous circuit system for the synchronous random-access memory completely meet the dual-track four-phase handshake protocol, and the synchronous random-access memory is completely inserted into a transmission chain of the four-phase dual-track handshake protocol. Further, a read data delay output is completely enclosed in the read circuit without adjusting the original asynchronous circuit system meeting the four-phase dual-track handshake protocol.
Description
Technical field
The invention belongs to interface circuit technical field, relate to a kind of interface circuit, especially write circuit and reading circuit.
Background technology
Current most of Design of Digital Circuit all adopts the method for synchronization, i.e. synchronizing circuit.The design of synchronizing circuit simplifies based on following two basic assumptions: all signals in circuit all adopt scale-of-two; All modules all share a public discrete time series, and this sequential is defined by the global clock signal be distributed in whole circuit.
And asynchronous digital circuits, be called for short asynchronous circuit, different with synchronizing circuit in essence; Although adopt binary signal yet, there is no public discrete time series, do not need global clock.Asynchronous circuit generally realizes data syn-chronization between different parts, communication and order of operation by Handshake Protocol.Compare with synchronizing circuit, asynchronous circuit does not have high frequency clock, and the upset of circuit is only carried out when inputting data and changing; Meanwhile, different with synchronizing circuit, asynchronous circuit does not need to carry out synchronously with the output of register pair combinational logic.Therefore, asynchronous circuit have low-power consumption, at a high speed, low electromagnetic noise radiation, easily modularization and the feature of easily reusing, be a kind of typical green circuit.
Because asynchronous circuit has above-mentioned advantage, recent years more and more comes into one's own, and some asynchronous cmos digital integrated circuit also dominate the market gradually, as smart card market, and heterogeneous multi-nucleus processor market etc.But asynchronous circuit remains the problem that the problem lacked in asynchronous IP module, particularly random access memory lack in the middle of CMOS integrated circuit (IC) design at present.Random access memory all will be used in most of asynchronous circuit system.Usually adopt in the middle of current CMOS Asynchronous integrated circuit design register or latch to carry out designing thus cause circuit complicated and power consumption is higher; Also can adopt the method design of full custom, this method design process very complicated, and need to carry out for specific integrated circuit fabrication process, portable poor.Meanwhile, the random access memory testability adopting these method design to obtain is poor, is unfavorable for large-scale production.
Therefore, if ripe, that there is better measurability synchronous random access memory module adopted in existing synchronizing circuit in asynchronous circuit system, the design and manufaction cost of asynchronous circuit system will greatly be reduced.
A kind of Handshake Protocol the most frequently used in asynchronous circuit is four phase double track Handshake Protocols.Four phase double track Handshake Protocols refer to and adopt coding and double track mode and four phase signals host-host protocols to carry out handshake communication.Coding and double track refers to that request signal and data-signal are put together by the mode of an information bit encodes by using two lines to represent, forming the signal for communicating, namely representing an information x with two wires.A wherein wire x.t presentation logic 1 (or true value), another wire x.f presentation logic 0 (or falsity).{ x.t, x.f}={1,0} are with { x.t, x.f}={0,1} are " effectively " state, represent 1 and 0 respectively; { x.t, x.f}={0,0} represent " sky " state; And { x.t, x.f}={1,1} do not use in the protocol.Four phase signals host-host protocols need to be put low level step and is level-sensitive, so be otherwise known as rz signal host-host protocol or level-sensitive signal transfer protocol.Four phase signals host-host protocols complete a handshake procedure needs four steps: transmitting terminal sends data and request signal is set to high level; Receiving end receives data and answer signal is set to high level; Request signal is also set to low level by transmitting terminal response receiving end; Answer signal is also set to low level by receiving end response transmitting terminal.Four phase double tracks shake hands passage as shown in Figure 1; The communication steps of four phase double track Handshake Protocols as shown in Figure 2.
First step transmitting terminal starts to send effective information, for the situation only having an information bit, namely sends { x.t, x.f}={1,0} or { x.t, x.f}={0,1} state.
After second step receiving end receives information, for the situation of multiple information bit, after needing to wait until that the passage of all information bits all becomes " effectively " state, answer signal is set to high level.
3rd step transmitting terminal receives answer signal (namely answer signal is for high) and sends " sky " status information afterwards, namely for the situation i.e. { x.t of single information bit, x.f}={0,0} state, situation for multiple information bit needs the passage of all information bits to be all set to " sky " state, as response.
Answer signal is set to low level and completes information transmission as response by last receiving end after all information bit passages of discovery are all " sky " status information.
Static RAM (SRAM) is a kind of data not needing refresh circuit can preserve its storage inside, can carry out the storer read and write according to random sequence.Static RAM have single port and dual-port point, single port only has a set of clock, address and FPDP, and dual-port has two cover clocks, address and FPDP.Usually its master control signal comprises:
ADD: address signal, represent (m+1) bit address signal with A [m:0], A [i] represents the i-th bit address signal;
: module select signal, usual low level represents that this memory module is selected;
: written allowance signal, usual low level represents that write operation is effective;
RE: read enable signal, usual high level represents that read operation is effective;
D_out: data output signal, represent that (n+1) bit data outputs signal with D_out [n:0], D_out [j] represents that jth bit data outputs signal;
D_in: data input signal, represent (n+1) bit data input signal with D_in [n:0], D_in [j] represents jth bit data input signal;
: data export and allow signal, Low level effective;
CLK: clock signal.
Summary of the invention
The object of the present invention is to provide a kind of interface circuit that can realize synchronous random access memory and apply in asynchronous circuit system.
In order to achieve the above object, solution of the present invention is:
A kind of asynchronous circuit system is to the write circuit of synchronous random access memory, described asynchronous circuit system adopts double track four phase Handshake Protocol, comprises writing allowing open circuit part, writing address and write data conversion and transmission circuit part, writing and start and write into answering circuit part; Described writing allows open circuit part to operate for the permission of writing of opening described synchronous random access memory according to the double track written allowance signal of described asynchronous circuit system; Said write address and write data conversion and transmission circuit part are used for the writing address signal and the write data-signal that the double track writing address signal of described asynchronous circuit system and write data-signal are converted to described synchronous random access memory; Described writing starts and writes into answering circuit part and write settling signal for sending to described synchronous random access memory to write enabling signal and send to described asynchronous circuit system.
Described writing allows open circuit part to comprise the first kind and door and first kind triple gate; The described first kind is connected two ports of the double track written allowance signal of described asynchronous circuit system respectively with two input ends of door, and output terminal connects the control Enable Pin of described first kind triple gate; The input end of described first kind triple gate connects the logical one signal port in the double track written allowance signal of described asynchronous circuit system, and output terminal connects the written allowance signal port of described synchronous random access memory.
Said write address and write data conversion and transmission circuit part comprise writing address conversion and transmission circuit; Said write address conversion and transmission circuit comprises the wire connected by write data address port corresponding with described synchronous random access memory for the logical one signal port of the double track writing address signal of described asynchronous circuit system.
Said write address and write data conversion and transmission circuit part comprise write data conversion and transmission circuit; Said write data conversion and transmission circuit comprises wire write FPDP corresponding with described synchronous random access memory for the logical one signal port of double track write data-signal in described asynchronous circuit system connected.
Described writing starts and writes into answering circuit part and comprise at least one first kind or door, at least one Equations of The Second Kind or door and first kind C element circuit; The input end of each first kind or door is connected with a pair address output end mouth of described asynchronous circuit system, the input end of each Equations of The Second Kind or door is connected with a pair data-out port of described asynchronous circuit system; The output terminal of each first kind or door and Equations of The Second Kind or door is all connected the different input ends of first kind C element circuit, and first kind C element circuit also has an input end to connect logic zero signal port in described asynchronous circuit system in double track written allowance signal; The output terminal of first kind C element circuit comprises two-way branch; One tunnel branch directly connects the clock signal port of described synchronous random access memory, another road branch connect to connect described asynchronous circuit system after the first delay circuit write into response port.
A kind of asynchronous circuit system is to the reading circuit of synchronous random access memory, described asynchronous circuit system adopts double track four phase Handshake Protocol, comprises and reads to allow open circuit part, reads address and read data conversion and transmission circuit part, reads open and run through answering circuit part; Described reading allows open circuit part to operate for the permission of reading of opening described synchronous random access memory according to the double track read enable signal of described asynchronous circuit system; Described reading address and reading data conversion and transmission circuit part are used for the double track reading address signal of described asynchronous circuit system being converted to the reading address signal of described synchronous random access memory and the signal read from described synchronous random access memory being converted to the dual-rail data signal of described asynchronous circuit system; Answering circuit part is opened and run through to described reading for sending reading enabling signal to described synchronous random access memory and sending reading settling signal to described asynchronous circuit system.
Describedly read to allow open circuit part to comprise Equations of The Second Kind and door and Equations of The Second Kind triple gate; Equations of The Second Kind is connected two ports of the double track read enable signal of described asynchronous circuit system respectively with two input ends of door, and output terminal connects the control Enable Pin of Equations of The Second Kind triple gate; The input end of Equations of The Second Kind triple gate connects the logical one signal port in the double track read enable signal of described asynchronous circuit system, and output terminal connects the read enable signal port of described synchronous random access memory.
Described reading address and reading data conversion and transmission circuit part comprise reading address conversion and transmission circuit; Described reading address conversion and transmission circuit comprises the wire reading the corresponding ports of address in the logical one signal port of the double track reading address signal directly connecting described asynchronous circuit system and described synchronous random access memory.
Described reading address and reading data conversion and transmission circuit part comprise reading data conversion and transmission circuit; Described reading data conversion and transmission circuit comprises (n1+1) individual branch circuit; Each branch circuit includes first kind phase inverter, Equations of The Second Kind C element circuit and two the 3rd classes and doors; In each described branch circuit, the input end of first kind phase inverter connects the jth 1 bit data signal of described synchronous random access memory reading; Equations of The Second Kind C element circuit comprises two input ports and an output port, the output opening and run through answering circuit part is read described in an input port connects, another input port connects the output terminal of Equations of The Second Kind phase inverter, output port connects an input end of two the 3rd classes and door, and the reading that the input end of Equations of The Second Kind phase inverter connects described asynchronous circuit system completes response port; First the 3rd class is connected the output terminal of first kind phase inverter with another input end of door, output terminal connects the logic zero signal port of jth 1 double track reading data of described asynchronous circuit system; Second the 3rd class is connected jth 1 readout data signal port of described synchronous random access memory with another input end of door, output terminal connects the logical one signal port of jth 1 double track reading data of described asynchronous circuit system; Wherein, (n1+1) is the figure place of the double track readout data signal of described asynchronous circuit system; 0≤j1≤n1.
Described reading is opened and is run through answering circuit part and comprise at least one the 3rd class or door, the 3rd class C element circuit; Often pair of double track of described asynchronous circuit system reads address port and connects the 3rd different classes or two input ends of door; The output terminal of each 3rd class or door connects the different input end of the 3rd class C element circuit respectively, and the 3rd class C element circuit also has an input end to connect logical one signal port in the double track read enable signal of described asynchronous circuit system; The output of the 3rd class C element circuit comprises three tunnel branches; First via branch directly connects the clock signal port of described synchronous random access memory, second tunnel branch connect to connect described asynchronous circuit system after the second delay circuit run through response port, form (n1+1) road branch after 3rd tunnel branch series connection the 3rd delay circuit, be connected with an input port of each Equations of The Second Kind C element circuit respectively.
Owing to adopting such scheme, the invention has the beneficial effects as follows: after adopting write circuit of the present invention to be connected with reading circuit, asynchronous circuit system meets four phase double track Handshake Protocols completely to the read-write of synchronous random access memory.When write operation, asynchronous circuit system is as the transmitting terminal of task, and write circuit is as receiving end.And when read operation, asynchronous circuit system is before this as task transmitting terminal, reading circuit transmits as receiving end and reads address; After synchronous random access memory exports DSR, reading circuit is again as task transmitting terminal, and asynchronous circuit system is as receiving end, transmit the data read from synchronous random access memory, thus intactly synchronous random access memory is inserted in the chain of four phase double track Handshake Protocols, data delay during reading is exported simultaneously and be encapsulated in completely in reading circuit, do not need to adjust original asynchronous circuit system meeting four phase double track Handshake Protocols.
Accompanying drawing explanation
Fig. 1 is that four phase double tracks are shaken hands the schematic diagram of passage;
Fig. 2 is the communication steps schematic diagram of four phase double track Handshake Protocols;
Fig. 3 is the structural representation of write circuit in the embodiment of the present invention;
The write data cube computation schematic diagram of the main signal port that Fig. 4 is the write circuit shown in Fig. 3 and asynchronous circuit system and synchronous random access memory;
Fig. 5 is the main process sequential chart that in the embodiment of the present invention, asynchronous circuit system writes the data of synchronous random access memory;
Fig. 6 is the structural representation of reading circuit in the embodiment of the present invention;
The reading data cube computation schematic diagram of the main signal port that Fig. 7 is the reading circuit shown in Fig. 6 and asynchronous circuit system and synchronous random access memory;
Fig. 8 be in the present invention in embodiment asynchronous circuit system to the main process sequential chart of the digital independent of synchronous random access memory.
Embodiment
Below in conjunction with accompanying drawing illustrated embodiment, the present invention is further illustrated.
The present invention proposes the interface circuit that a kind of asynchronous circuit system writes synchronous random access memory and reads, namely comprise write circuit and interface circuit.Wherein, this asynchronous circuit system adopts double track four phase Handshake Protocol.In the present embodiment, this synchronous random access memory is dual-port synchronous random access memory.To adopt the synchronous random access memory of interface circuit of the present invention and method of attachment seamlessly to access to adopt in the asynchronous circuit system of double track four phase Handshake Protocol and not destroy the Handshake Protocol chain of this asynchronous circuit system.
At asynchronous circuit system end, address and data acquisition coding and double track.Address and data-signal are expressed as follows:
D0_in [m1:0] and D1_in [m1:0] represents that asynchronous circuit system prepares (m1+1) position dual-rail data signal exported to synchronous random access memory.Wherein, D0_in [i1] and D1_in [i1] represents the i-th 1 dual-rail data, D0_in presentation logic 0 signal, D1_in presentation logic 1 signal; (m1+1) figure place of the double track write data-signal of asynchronous circuit system is represented, 0≤i1≤m1.
D0_out [n1:0] and D1_out [n1:0] represents (n1+1) the position coding and double track of the data acquisition that asynchronous circuit system reads to synchronous random access memory.Wherein, D0_out [j1] and D1_out [j1] represents jth 1 dual-rail data, D0_out presentation logic 0 signal, D1_out presentation logic 1 signal; (n1+1) figure place of the double track readout data signal of asynchronous circuit system is represented, 0≤j1≤n1.
A0 [m2:0] and A1 [m2:0] represents that asynchronous circuit system prepares (m2+1) position double track address signal to synchronous random access memory write data.Wherein, A0 [i2] and A1 [i2] represents the i-th 2 double track address signals, A0 presentation logic 0 signal, A1 presentation logic 1 signal; (m2+1) figure place of the double track writing address signal of asynchronous circuit system is represented, 0≤i2≤m2.
A0 [n2:0] and A1 [n2:0] represents that asynchronous circuit system prepares to read to synchronous random access memory (n2+1) position double track address signal of data.Wherein, A0 [j2] and A1 [j2] represents jth 2 double track address signals, A0 presentation logic 0 signal, A1 presentation logic 1 signal; (n2+1) figure place of the double track reading address signal of asynchronous circuit system is represented, 0≤j2≤n2.
The asynchronous circuit system that the present invention proposes carries out the structural representation of the write circuit writing data as shown in Figure 3 to synchronous random access memory.This write circuit comprises writing and allows open circuit part, writing address and write data converting transmission connecting circuit part, writes and start and write into answering circuit part.
Write and allow open circuit part to operate for the permission of writing of opening synchronous random access memory according to the double track written allowance signal of asynchronous circuit system.Write and allow open circuit part to comprise the first kind and door and first kind triple gate.This first kind and door comprise two input ends and an output terminal, and first kind triple gate comprises an input end, an output terminal and a control Enable Pin.The first kind is connected two ports of the double track written allowance signal of asynchronous circuit system respectively with two input ends of door, and output terminal connects the control Enable Pin of first kind triple gate.The input end of first kind triple gate connects the port WE1 of the logical one signal in the double track written allowance signal of asynchronous circuit system, and output terminal connects the written allowance signal port of synchronous random access memory.
Writing address and write data conversion and transmission circuit part comprise writing address conversion and transmission circuit and write data conversion and transmission circuit.Writing address conversion and transmission circuit is used for the writing address signal double track writing address signal of asynchronous circuit system being converted to synchronous random access memory.Write data conversion and transmission circuit is used for the write data-signal double track of asynchronous circuit system write data-signal being converted to synchronous random access memory.Writing address conversion and transmission circuit comprises the wire be connected by the i-th 2 bit ports writing data address in the logical one signal port of (m2+1) position double track writing address signal of asynchronous circuit system the i-th 2 and synchronous random access memory.Write data conversion and transmission circuit comprises the wire be connected by the i-th 1 bit ports of the logical one signal port of (m1+1) position double track write data-signal of asynchronous circuit system the i-th 1 and the write FPDP of synchronous random access memory.
Write and start and write into answering circuit part and write settling signal for sending to synchronous random access memory to write enabling signal and send to asynchronous circuit system.Write and start and write into answering circuit part and comprise the first kind C element circuit that Equations of The Second Kind or door that individual (m2+1) with asynchronous circuit system of the first kind that (m1+1) individual (m1+1) with asynchronous circuit system be connected data-out port or door, (m2+1) be connected address output port and have (m1+m2+3) individual input end.The output terminal of each first kind or door and Equations of The Second Kind or door is all connected the different input end of this first kind C element circuit, and this first kind C element circuit also has an input end to be connected with the logic zero signal port WE0 in the double track written allowance signal of asynchronous circuit system in addition.The output terminal of first kind C element circuit comprises two-way branch, and a road branch directly connects synchronous random access memory clock signal port, and another road branch connects and connects asynchronous circuit system after the first delay circuit and write into response port.
The connection of the main signal port of this write circuit and asynchronous circuit system and synchronous random access memory as shown in Figure 4.Wherein, synchronous random access memory
port directly can be controlled to be set to low level during write data by asynchronous circuit system, also directly can connect low level as shown in Figure 4.WE1 and the WE0 signal of asynchronous circuit system is the written allowance signal adopting coding and double track, wherein WE1 presentation logic 1 signal, WE0 presentation logic 0 signal; Addr_a is write answer signal port.
In write circuit, the written allowance signal of the coding and double track of asynchronous circuit system, outputs to through the first kind and door and first kind triple gate
port.When WE0 is high level and WE1 is low level,
export as low level; When WE0 is low level and WE1 is high level,
export as high level; When WE0 and WE1 is low level,
export as high-impedance state.In the data-signal of asynchronous circuit system coding and double track and address signal, the signal of presentation logic 1 directly outputs to the corresponding data of synchronous random access memory and address bit port through this write circuit, namely A1 [i2] and A [i2] is corresponding, and D1_in [i1] and D_in [i1] is corresponding.Meanwhile, in the data-signal of coding and double track and address signal, each group dual-rail output signal accesses the first kind or door and Equations of The Second Kind or door computing respectively, and then the first kind or door export with Equations of The Second Kind or door and access first kind C element circuit together with WE0 signal.When WE0 becomes high level, and when dual-rail data and address signal all become " effectively " state from " sky " state, the output terminal of first kind C element circuit becomes high level from low level, produces rising edge signal.This rising edge signal directly outputs to the CLK port of synchronous random access memory.Meanwhile, high level signal outputs to Addr_a port through time delay, as the response effectively received data and the address signal of asynchronous circuit system.When WE0 is low level, and dual-rail data and address signal are when all becoming " sky " state, first kind C element circuit output low level, this low level outputs to Addr_a port after time delay, as being the response that dummy status effectively detects to asynchronous circuit system data and address.
As shown in Figure 5, detailed process is the main process that asynchronous circuit system writes the data of synchronous random access memory:
A) WE1 is set to low level by asynchronous circuit system, and WE0 is set to high level, and the data that simultaneously will write and address put into D0_in [m1:0], D1_in [m1:0] and A0 [m2:0], A1 [m2:0] respectively.Asynchronous circuit system data adopts four phase double track Handshake Protocol codings.
B) step a) in signal changed by write circuit, make write circuit output terminal
for low level, A [m2:0] and D_in [m1:0] end places the address preparing write data and the data preparing write respectively.
C) after all DSRs in b) step, write circuit exports rising edge signal from CLK port, data are write synchronous random access memory, then the Addr_a port level of write circuit is drawn high according to four phase double track agreements by write circuit, as the response to asynchronous circuit system, represent and received the data and corresponding address that will write.
D) after asynchronous circuit systems axiol-ogy is high level to the incoming level of Addr_a port, according to four phase double track Handshake Protocols, D0_in [m1:0], D1_in [m1:0] and A0 [m2:0], A1 [m2:0] and WE1 and WE0 are all set to low level, write circuit
become high-impedance state accordingly.
E) write circuit detects D0_in [m1:0], D1_in [m1:0] and A0 [m2:0], A1 [m2:0] is all after low level, Addr_a port level is dragged down, as the outputting data signals to asynchronous circuit system according to four phase double track Handshake Protocols
For the response of sky, complete write-once task.
The invention allows for a kind of reading circuit adopting the asynchronous circuit system of double track four phase Handshake Protocol to carry out reading data to synchronous random access memory, its structural representation as shown in Figure 6.This reading circuit comprises to be read to allow open circuit part, read address and reads data conversion and transmission circuit part, read open and run through answering circuit part.
Read to allow open circuit part to operate for the permission of reading of opening synchronous random access memory according to the double track read enable signal of asynchronous circuit system.Read to allow open circuit part to comprise an Equations of The Second Kind and door and an Equations of The Second Kind triple gate.This Equations of The Second Kind and door comprise two input ends and an output terminal, and this Equations of The Second Kind triple gate comprises an input end, an output terminal and a control Enable Pin.This Equations of The Second Kind is connected two ports of the double track read enable signal of asynchronous circuit system respectively with two input ends of door, and an output terminal connects the control Enable Pin of Equations of The Second Kind triple gate.The input end of this Equations of The Second Kind triple gate connects the logical one signal port RE1 in the double track read enable signal of asynchronous circuit system, and output terminal connects the read enable signal port wire of synchronous random access memory.
Read address and read data conversion and transmission circuit part and comprise reading address conversion and transmission circuit and read data conversion and transmission circuit, be respectively used to the double track reading address signal of asynchronous circuit system be converted to the reading address signal of synchronous random access memory and be used for the signal read from synchronous random access memory to be converted to the dual-rail data signal of asynchronous circuit system.
Read the wire that address conversion and transmission circuit comprises jth 2 bit port of logical one signal port and the synchronous random access memory reading address directly connecting (n2+1) position double track reading address signal jth 2 in asynchronous circuit system.
Read data conversion and transmission circuit and comprise (n1+1) individual branch circuit.Each branch circuit comprises a first kind phase inverter, the two Equations of The Second Kind C element circuit inputted and two the 3rd classes and doors.The effect of jth 1 branch circuit is jth 1 the double track readout data signal jth 1 bit data signal that synchronous random access memory reads being converted to asynchronous circuit system.First kind phase inverter comprises an input end and an output terminal, and input end connects the jth 1 bit data signal that synchronous random access memory reads.Equations of The Second Kind C element circuit comprises two input ports and an output port.The reading of asynchronous circuit system connects an input port of Equations of The Second Kind C element circuit in each branch circuit after completing and replying port (D_out_a) wired in series Equations of The Second Kind phase inverter, be connected another input port of the Equations of The Second Kind C element circuit of each branch circuit reading data conversion and transmission circuit after reading output port wired in series the 3rd delay circuit of the 3rd class C element circuit opening and run through answering circuit part.The output terminal of Equations of The Second Kind C element circuit comprises Liang Ge branch, and respectively with two the 3rd classes are connected with an input end of door.First the 3rd class is connected with the output terminal of another input end of door with the first kind phase inverter in this branch circuit, and the logic zero signal port that output terminal reads data with jth 1 double track of asynchronous circuit system is connected; Second the 3rd class is connected jth 1 readout data signal of synchronous random access memory with another input end of door, output terminal connects the logical one signal port of jth 1 double track reading data of asynchronous circuit system.
Read to open and run through answering circuit part read enabling signal for sending to synchronous random access memory and send reading settling signal to asynchronous circuit system.Read to open and run through answering circuit and comprise that (n2+1) is individual reads the 3rd class that address port is connected or door, a 3rd class C element circuit be connected with the output terminal of (n2+1) individual 3rd class or door with (n2+1) of asynchronous circuit system to double track respectively.Wherein, the 3rd class C unit power supply comprises (n2+2) individual input end, and the output terminal of each 3rd class or door is connected from the different input end of the 3rd class C element circuit respectively; 3rd class C element circuit also has the logical one signal port RE1 in the double track read enable signal of an input end connection asynchronous circuit system.The output terminal of the 3rd class C element circuit comprises three tunnel branches.One tunnel branch directly connects the clock signal port of synchronous random access memory; Another road branch connect to connect asynchronous circuit system after the second delay circuit run through response port; Form (n1+1) road branch after 3rd tunnel branch series connection the 3rd delay circuit, be connected with an input port of (n1+1) the individual Equations of The Second Kind C element circuit read in data conversion and transmission circuit respectively.
This reading circuit is connected as shown in Figure 7 with the main signal port of asynchronous circuit system and synchronous random access memory.Wherein, synchronous random access memory
with
directly can be controlled to be set to low level during reading data by asynchronous circuit system, also directly can connect low level as shown in Figure 7.RE1 and the RE0 signal of asynchronous circuit system is the read enable signal adopting coding and double track, wherein RE1 presentation logic 1 signal, RE0 presentation logic 0 signal; Addr_a is for reading answer signal port; D_out_a is that reading completes response port.
In reading circuit, the coding and double track read enable signal of asynchronous circuit system outputs to RE port through Equations of The Second Kind and door and Equations of The Second Kind triple gate.When RE0 is high level and RE1 is low level, RE exports as low level; When RE0 is low level and RE1 is high level, RE exports as high level; When RE0 and RE1 is low level, RE exports as high-impedance state.
In the address signal of the coding and double track of asynchronous circuit system, the signal of presentation logic 1 directly outputs to the corresponding address bit port of synchronous random access memory through this reading circuit, and namely A1 [j2] and A [j2] is corresponding.In the address signal of simultaneously coding and double track, each group dual-rail output signal accesses the 3rd class or door computing respectively, and then the output of the 3rd class or door accesses the 3rd class C unit together with RE1 signal.When RE1 becomes high level, and when double track address signal all becomes " effectively " state from " sky " state, the output terminal of the 3rd class C element circuit becomes high level from low level, produces rising edge signal.This rising edge signal directly outputs to the CLK port of synchronous random access memory.Meanwhile, this high level signal outputs to Addr_a port through time delay, as the response effectively received the address signal of asynchronous circuit system.When RE1 is low level, and double track address signal is when all becoming " sky " state, 3rd class C element circuit output low level, this low level outputs to Addr_a port after time delay, as being the response that dummy status effectively detects to asynchronous circuit system data and address.
The CLK signal that this reading circuit exports is after time delay, after the second phase inverter, input Equations of The Second Kind C element circuit with the data receiver answer signal D_out_a of asynchronous circuit system, produce the output control signal of the data-out port signal D_out [j1] to synchronous random access memory.When D_out_a is low level and after CLK time delay, signal is high level, Equations of The Second Kind C element circuit exports as high level, and now D0_out [j1] and D1_out [j1] signal correspond to the coding and double track signal of D_out [j1].When D_out_a is high level and after CLK time delay, signal is low level, no matter D_out [j1] why level, D1_out [j1] and D0_out [j1] all output low levels, become " sky " state.
To the main process of the digital independent of synchronous random access memory as shown in Figure 8, detailed process is asynchronous circuit system:
A) RE0 is set to low level by asynchronous circuit system, and RE1 is set to high level, and the address simultaneously will reading data is placed on A0 [n2:0], A1 [n2:0] respectively.Address date adopts double track protocol code.
B) step a) in signal by reading circuit, when reading circuit output terminal RE is high level, be converted to address A [n2:0] address signal that synchronous random access memory prepares to read data.
C) after all DSRs in b) step, reading circuit exports rising edge signal from CLK port, then the Addr_a port level of reading circuit is drawn high according to four phase double track agreements by reading circuit, represents the address receiving and will read data to asynchronous circuit system.
D), after asynchronous circuit systems axiol-ogy is high level to Addr_a port incoming level, according to four phase double track agreements by A0 [n2:0], A1 [n2:0] and RE1 and RE0 is all set to low level.
E) reading circuit after a period of delay, reads in data from D_out [n1:0] port of synchronous random access memory.Be greater than synchronous random access memory CLK end time delay after receiving rising edge signal to the interval getting out export data.Then, the data that D_out [n1:0] port reads in are converted to double track protocol code in D0_out [n1:0] and D1_out [n1:0] output by reading circuit.
F), after asynchronous circuit systems axiol-ogy has valid data to D0_out [n1:0] and D1_out [n1:0], data are read in; And according to four phase double track agreements, D_out_a port level is drawn high, as the response to reading circuit, represent that data receive.
G) reading circuit is after detecting that D_out_a port is high level, D0_out [n1:0] and D1_out [n1:0] port level is all dragged down according to four phase double track agreements.
H) asynchronous circuit systems axiol-ogy is all low to be dragged down by D_out_a port level according to four phase double track agreements afterwards to D0_out [n1:0] and D1_out [n1:0] port level, as the response to reading circuit, represent that data-signal is that dummy status receives, complete and once read task.
In sum, after adopting write circuit of the present invention to be connected with reading circuit, asynchronous circuit system meets four phase double track Handshake Protocols completely to the read-write of synchronous random access memory.When write operation, asynchronous circuit system is as the transmitting terminal of task, and write circuit is as receiving end.And when read operation, asynchronous circuit system is before this as task transmitting terminal, reading circuit transmits as receiving end and reads address; After synchronous random access memory exports DSR, reading circuit is again as task transmitting terminal, and asynchronous circuit system is as receiving end, transmit the data read from synchronous random access memory, thus intactly synchronous random access memory is inserted in the chain of four phase double track Handshake Protocols, data delay during reading is exported simultaneously and be encapsulated in completely in reading circuit, do not need to adjust original asynchronous circuit system meeting four phase double track Handshake Protocols.
Above-mentioned is can understand and apply the invention for ease of those skilled in the art to the description of embodiment.Person skilled in the art obviously easily can make various amendment to these embodiments, and General Principle described herein is applied in other embodiments and need not through performing creative labour.Therefore, the invention is not restricted to embodiment here, those skilled in the art, according to announcement of the present invention, do not depart from improvement that scope makes and amendment all should within protection scope of the present invention.
Claims (10)
1. an asynchronous circuit system is to the write circuit of synchronous random access memory, described asynchronous circuit system adopts double track four phase Handshake Protocol, it is characterized in that: comprise writing and allow open circuit part, writing address and write data conversion and transmission circuit part, write and start and write into answering circuit part;
Described writing allows open circuit part to operate for the permission of writing of opening described synchronous random access memory according to the double track written allowance signal of described asynchronous circuit system;
Said write address and write data conversion and transmission circuit part are used for the writing address signal and the write data-signal that the double track writing address signal of described asynchronous circuit system and write data-signal are converted to described synchronous random access memory;
Described writing starts and writes into answering circuit part and write settling signal for sending to described synchronous random access memory to write enabling signal and send to described asynchronous circuit system.
2. asynchronous circuit system according to claim 1 is to the write circuit of synchronous random access memory, it is characterized in that: described in write and allow open circuit part to comprise the first kind and door and first kind triple gate; The described first kind is connected two ports of the double track written allowance signal of described asynchronous circuit system respectively with two input ends of door, and output terminal connects the control Enable Pin of described first kind triple gate; The input end of described first kind triple gate connects the logical one signal port in the double track written allowance signal of described asynchronous circuit system, and output terminal connects the written allowance signal port of described synchronous random access memory.
3. asynchronous circuit system according to claim 1 is to the write circuit of synchronous random access memory, it is characterized in that: said write address and write data conversion and transmission circuit part comprise writing address conversion and transmission circuit;
Said write address conversion and transmission circuit comprises the wire connected by write data address port corresponding with described synchronous random access memory for the logical one signal port of the double track writing address signal of described asynchronous circuit system.
4. asynchronous circuit system according to claim 1 is to the write circuit of synchronous random access memory, it is characterized in that: said write address and write data conversion and transmission circuit part comprise write data conversion and transmission circuit;
Said write data conversion and transmission circuit comprises wire write FPDP corresponding with described synchronous random access memory for the logical one signal port of double track write data-signal in described asynchronous circuit system connected.
5. asynchronous circuit system according to claim 1 is to the write circuit of synchronous random access memory, it is characterized in that: described in write and start and write into answering circuit part and comprise at least one first kind or door, at least one Equations of The Second Kind or door and first kind C element circuit;
The input end of each first kind or door is connected with a pair address output end mouth of described asynchronous circuit system, the input end of each Equations of The Second Kind or door is connected with a pair data-out port of described asynchronous circuit system;
The output terminal of each first kind or door and Equations of The Second Kind or door is all connected the different input ends of first kind C element circuit, and first kind C element circuit also has an input end to connect logic zero signal port in described asynchronous circuit system in double track written allowance signal;
The output terminal of first kind C element circuit comprises two-way branch; One tunnel branch directly connects the clock signal port of described synchronous random access memory, another road branch connect to connect described asynchronous circuit system after the first delay circuit write into response port.
6. an asynchronous circuit system is to the reading circuit of synchronous random access memory, described asynchronous circuit system adopts double track four phase Handshake Protocol, it is characterized in that: comprise and read to allow open circuit part, read address and read data conversion and transmission circuit part, read open and run through answering circuit part;
Described reading allows open circuit part to operate for the permission of reading of opening described synchronous random access memory according to the double track read enable signal of described asynchronous circuit system;
Described reading address and reading data conversion and transmission circuit part are used for the double track reading address signal of described asynchronous circuit system being converted to the reading address signal of described synchronous random access memory and the signal read from described synchronous random access memory being converted to the dual-rail data signal of described asynchronous circuit system;
Answering circuit part is opened and run through to described reading for sending reading enabling signal to described synchronous random access memory and sending reading settling signal to described asynchronous circuit system.
7. asynchronous circuit system according to claim 6 is to the reading circuit of synchronous random access memory, it is characterized in that: described in read to allow open circuit part to comprise Equations of The Second Kind and door and Equations of The Second Kind triple gate;
Equations of The Second Kind is connected two ports of the double track read enable signal of described asynchronous circuit system respectively with two input ends of door, and output terminal connects the control Enable Pin of Equations of The Second Kind triple gate;
The input end of Equations of The Second Kind triple gate connects the logical one signal port in the double track read enable signal of described asynchronous circuit system, and output terminal connects the read enable signal port of described synchronous random access memory.
8. asynchronous circuit system according to claim 6 is to the reading circuit of synchronous random access memory, it is characterized in that: described reading address and reading data conversion and transmission circuit part comprise reading address conversion and transmission circuit;
Described reading address conversion and transmission circuit comprises the wire reading the corresponding ports of address in the logical one signal port of the double track reading address signal directly connecting described asynchronous circuit system and described synchronous random access memory.
9. asynchronous circuit system according to claim 6 is to the reading circuit of synchronous random access memory, it is characterized in that: described reading address and reading data conversion and transmission circuit part comprise reading data conversion and transmission circuit;
Described reading data conversion and transmission circuit comprises (n1+1) individual branch circuit; Each branch circuit includes first kind phase inverter, Equations of The Second Kind C element circuit and two the 3rd classes and doors;
In each described branch circuit, the input end of first kind phase inverter connects the jth 1 bit data signal of described synchronous random access memory reading; Equations of The Second Kind C element circuit comprises two input ports and an output port, the output opening and run through answering circuit part is read described in an input port connects, another input port connects the output terminal of Equations of The Second Kind phase inverter, output port connects an input end of two the 3rd classes and door, and the reading that the input end of Equations of The Second Kind phase inverter connects described asynchronous circuit system completes response port;
First the 3rd class is connected the output terminal of first kind phase inverter with another input end of door, output terminal connects the logic zero signal port of jth 1 double track reading data of described asynchronous circuit system; Second the 3rd class is connected jth 1 readout data signal port of described synchronous random access memory with another input end of door, output terminal connects the logical one signal port of jth 1 double track reading data of described asynchronous circuit system;
Wherein, (n1+1) is the figure place of the double track readout data signal of described asynchronous circuit system; 0≤j1≤n1.
10. asynchronous circuit system according to claim 9 is to the reading circuit of synchronous random access memory, it is characterized in that: described in read to open and run through answering circuit part and comprise at least one the 3rd class or door, the 3rd class C element circuit;
Often pair of double track of described asynchronous circuit system reads address port and connects the 3rd different classes or two input ends of door; The output terminal of each 3rd class or door connects the different input end of the 3rd class C element circuit respectively, and the 3rd class C element circuit also has an input end to connect logical one signal port in the double track read enable signal of described asynchronous circuit system;
The output of the 3rd class C element circuit comprises three tunnel branches; First via branch directly connects the clock signal port of described synchronous random access memory, second tunnel branch connect to connect described asynchronous circuit system after the second delay circuit run through response port, form (n1+1) road branch after 3rd tunnel branch series connection the 3rd delay circuit, be connected with an input port of each Equations of The Second Kind C element circuit respectively.
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