CN116866445B - Conversion device, chip and electronic equipment between four-phase double-track and two-phase double-track protocols - Google Patents
Conversion device, chip and electronic equipment between four-phase double-track and two-phase double-track protocols Download PDFInfo
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Abstract
The invention discloses a conversion device, a chip and electronic equipment between four-phase double-track and two-phase double-track protocols. In order to solve the difficult problem of high-efficiency and flexible communication between the existing asynchronous circuit using four-phase double-track protocol handshake and the asynchronous circuit using two-phase double-track protocol handshake, the conversion device of the invention comprises: a first conversion circuit for converting the four-phase double-track protocol signal into a two-phase double-track protocol signal, or/and a second conversion circuit for converting the two-phase double-track protocol signal into the four-phase double-track protocol signal. The invention adopts a simple gate circuit, a C unit and a trigger to realize an event-driven conversion circuit, has the characteristics of simple structure, modularization and high conversion efficiency, and has low power consumption. The invention is suitable for the fields of asynchronous circuits, internet of things, neuromorphic chips and the like.
Description
Technical Field
The invention relates to a conversion device between four-phase double-track and two-phase double-track protocols, in particular to a conversion device, a chip and electronic equipment for realizing conversion between four-phase double-track protocol data and two-phase double-track protocol data in an asynchronous circuit.
Background
The asynchronous circuit can quickly respond to input change without waiting for clock signals, does not need a global clock to synchronize the operation of each part, has the characteristic of low power consumption, can respond according to the actual input state, can not receive strict clock synchronization requirements, and is more flexible in processing different logics and conditions. Therefore, in application scenarios requiring low power consumption and fast response, asynchronous circuits are becoming increasingly favored and used.
Current asynchronous handshake protocols can be divided into a single track protocol (bundled data protocol) and a double track protocol according to the number of data lines. The single track protocol uses one line to represent one bit of information, highlights the timing relationship between the data (data) signal and the handshake signals (req, ack), and the double track protocol uses two lines to represent one bit of information, while the req signal and the data signal are put together to be encoded, forming a signal for communication. The dual-rail protocol is insensitive to wire delay, has higher safety, has diversity and flexibility, and can provide redundancy.
The dual-track protocol is further divided into a four-phase dual-track protocol and a two-phase dual-track protocol. The four-phase dual-track protocol can be regarded as a data stream in which valid codewords in a channel are separated by null codewords, and the handshake process in one communication period is as follows: a. the sender sends out a valid codeword; b. the receiving party receives the code word and pulls up the ack signal; c. the sender responds to the ack signal and sends out NULL value NULL code words; d. the receiver pulls ack low. The two-phase double-track protocol has information expressed in jump (event) mode, no null code word and no interval transmission code word.
The four-phase dual-rail protocol has more phases of operation, so that the circuit can respond to different input and control signals more flexibly, yet the transmission time is longer. The two-phase dual-rail protocol is fast and low in power consumption, but the response circuit is complex, so that the choice of whether to use the four-phase dual-rail protocol or the two-phase dual-rail protocol depends on the design requirements of the asynchronous circuit, the performance targets and the complexity of the circuit.
Some techniques consider the conversion between a four-phase dual-track protocol and a two-phase dual-track protocol, as in prior art 1 and prior art 2. However, these techniques include LEDR encoders, decoders, and controllers during conversion, which require decoding and then encoding, and are complex and limited in conversion efficiency. The latch is used in the conversion process, the stability is poor, a plurality of C units are used, and the circuit is complex and large in area.
Prior art 1: A. mitra, et al, "" Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication ", proc, IEEE int, symp, asynchronous Circuits Syst,", pp., 186-195, march 2007;
prior art 2: W.F. McLaughlin, et al, "Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication", IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol.17, no. 7, pp. 923-928, july 2009.
How to realize the conversion between the four-phase double-track protocol and the two-phase double-track protocol and further improve the communication efficiency between the modules is a problem to be solved urgently in the design of asynchronous circuits.
Disclosure of Invention
In order to solve or alleviate some or all of the above technical problems, the present invention is implemented by the following technical solutions:
a first type of conversion device for converting four-phase double-track protocol into two-phase double-track protocol data, comprising a first data signal converter and a first handshake signal converter;
the first data signal converter comprises N parallel first data signal conversion units, wherein N represents the communication bit number and is greater than or equal to 1;
the first data signal conversion unit is used for converting a pair of data signals representing one-bit information in the double-track protocol from a four-phase coding format to a two-phase coding format;
the first handshake signal converter converts a two-phase double-track response signal returned by the receiving end into a four-phase double-track response signal suitable for the transmitting end.
In some class of embodiments, the first data signal conversion unit includes a first exclusive or gate and a first logic section;
a first exclusive-OR gate for inputting any pair of numbersExclusive-or is carried out on the true value information and the false value information in the signal to obtain a logic operation resultWherein->An integer from 0 to N-1;
and the first logic part converts the true value information and the false value information which are adapted to the four-phase double-track protocol of the transmitting end into the true value information and the false value information which are adapted to the two-phase double-track protocol of the receiving end based on the output of the first exclusive OR gate and the true value information and the false value information in any pair of input data signals.
In certain embodiments, the first logic includes a first branch that converts true value information and a second branch that converts false value information.
In certain classes of embodiments, the first branch comprises a first and gate and a first D flip-flop;
the first AND gate carries out logic AND on the output of the first exclusive OR gate and the true value information in the corresponding data line, the output of the first AND gate is used as a clock control end of a first D trigger, and the output of the first D trigger is the true value information of the pair of data lines adapted to the two-phase double-track protocol;
the second branch circuit comprises a second AND gate and a second D trigger, the second AND gate carries out logic AND on the output of the first exclusive OR gate and false value information in the corresponding data line, the output of the second AND gate is used as a clock control end of the second D trigger, and the output of the second D trigger is the false value information of the pair of data lines adapted to the two-phase double-track protocol.
In some embodiments, the first handshake signal converter detects whether a two-phase dual-track response signal returned by the receiving end has a jump, generates a first indication when the jump is detected, and obtains a four-phase dual-track response signal adapted to the transmitting end based on the first indication and output of a first exclusive-or gate in the N parallel first data signal conversion units.
In some embodiments, an asynchronous edge detection circuit is used to detect whether a jump exists in a two-phase dual-rail response signal returned by the receiving end.
In some class of embodiments, the first handshake signal transformer includes a second logic and a first C-unit,
the second logic part is used for carrying out logic operation on the output of the first exclusive-OR gates in the N first data signal conversion units;
the first C unit is used for carrying out state tracking on the output of the second logic part and the output of the asynchronous edge detection circuit.
In certain classes of embodiments, the first or/and the second exclusive-or gate is replaced with an or gate.
In some embodiments, the second logic portion includes a plurality of C units, where the plurality of C units are divided into at least one stage, where an output of a first stage C unit is processed by a second stage C unit including a plurality of C units until a last stage C unit has only 1C unit, and an output of the last stage C unit is an output of the second logic portion;
the output of every two C units in the former stage C unit is used as the input of one C unit in the latter stage C unit; the output of 1C unit in the last stage C unit is used as a request signal in four-phase binding data protocol data.
A second type conversion device for converting two-phase double-track protocol into four-phase double-track protocol data, comprising a second data signal converter and a second handshake signal converter;
a second data signal converter including N parallel second data signal conversion units, N representing the number of communication bits, and N being greater than or equal to 1;
the second data signal conversion unit is used for converting a pair of data signals representing one-bit information in the double-track protocol from a two-phase coding format to a four-phase coding format;
the second handshake signal converter converts the four-phase double-track response signal returned by the receiving end into a two-phase double-track response signal which is suitable for the transmitting end.
In certain embodiments, the second data signal conversion unit includes a third branch that converts true value information and a fourth branch that converts false value information.
In certain classes of embodiments, the third branch includes a second edge detection circuit and a second C-cell;
the second edge detection circuit is used for monitoring whether the true value information in the corresponding data line is jumped or not, and generating a second indication if the true value information in the corresponding data line is jumped;
the second C unit generates true value information adapted to a four-phase double-track protocol based on the second indication and the inverse of the four-phase double-track response signal returned by the receiving end;
the fourth branch comprises a third edge detection circuit and a third C unit;
the third edge detection circuit is used for monitoring whether the false value information in the corresponding data line is jumped or not, and generating a third indication if the jump exists;
and the third C unit generates false value information adapted to a four-phase double-track protocol based on the third indication and the inverse of the four-phase double-track response signal returned by the receiving end.
In certain classes of embodiments, the second handshake signal transformer includes a third D flip-flop;
the clock control end of the third D trigger is coupled with the four-phase double-track response signal returned by the receiving end, and the output of the third D trigger is the two-phase double-track response signal which corresponds to the data line and is adapted to the transmitting end.
A chip comprising any of the conversion means of the first type as described above, or/and comprising any of the conversion means of the second type as described above.
In certain classes of embodiments, the chip is a neuromorphic chip or a chip designed based on event driving.
An electronic device comprising a chip as described above.
Some or all embodiments of the present invention have the following beneficial technical effects:
1) The invention realizes flexible conversion between the four-phase double-track protocol and the two-phase double-track protocol.
2) The logic gate, the C unit and the trigger are only used, the structure is simple, the implementation is easy, and the logic gate and the C unit have the characteristics of low power consumption and high conversion efficiency.
3) The protocol conversion circuit realizes flexible conversion between the four-phase double-track protocol and the two-phase double-track protocol with extremely low resource and cost.
4) The invention is realized based on an event-driven mechanism, has outstanding modularization, low comprehensive and verification difficulty and easy test.
Further advantageous effects will be further described in the preferred embodiments.
The above-described technical solutions/features are intended to summarize the technical solutions and technical features described in the detailed description section, and thus the ranges described may not be exactly the same. However, these new solutions disclosed in this section are also part of the numerous solutions disclosed in this document, and the technical features disclosed in this section and the technical features disclosed in the following detailed description section, and some contents in the drawings not explicitly described in the specification disclose more solutions in a reasonable combination with each other.
The technical scheme combined by all the technical features disclosed in any position of the invention is used for supporting the generalization of the technical scheme, the modification of the patent document and the disclosure of the technical scheme.
Drawings
FIG. 1 is a schematic diagram of a protocol conversion circuit according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a first converting circuit according to an embodiment of the invention;
FIG. 3a is a schematic diagram of a first data signal converter;
FIG. 3b is a schematic diagram of a first handshake signal converter;
FIG. 4 is a schematic diagram of a second logic portion according to some embodiments of the present invention;
FIG. 5 is a schematic diagram of a second converting circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a second converting circuit according to another embodiment of the present invention;
FIG. 7 is a timing diagram of a first switching circuit according to an embodiment of the invention;
fig. 8 is a timing diagram of a second switching circuit according to another embodiment of the invention.
Detailed Description
Since various alternatives are not exhaustive, the gist of the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. Other technical solutions and details not disclosed in detail below, which generally belong to technical objects or technical features that can be achieved by conventional means in the art, are limited in space and the present invention is not described in detail.
Except where division is used, any position "/" in this disclosure means a logical "or". The ordinal numbers "first", "second", etc., in any position of the present invention are used merely for distinguishing between the labels in the description and do not imply an absolute order in time or space, nor do they imply that the terms preceded by such ordinal numbers are necessarily different from the same terms preceded by other ordinal terms.
The present invention will be described in terms of various elements for use in various combinations of embodiments, which elements are to be combined in various methods, products. In the present invention, even if only the gist described in introducing a method/product scheme means that the corresponding product/method scheme explicitly includes the technical feature.
The description of a step, module, or feature in any location in the disclosure does not imply that the step, module, or feature is the only step or feature present, but that other embodiments may be implemented by those skilled in the art with the aid of other technical means according to the disclosed technical solutions. The embodiments of the present invention are generally disclosed for the purpose of disclosing preferred embodiments, but it is not meant to imply that the contrary embodiments of the preferred embodiments are not intended to cover all embodiments of the invention as long as such contrary embodiments are at least one technical problem addressed by the present invention. Based on the gist of the specific embodiments of the present invention, a person skilled in the art can apply means of substitution, deletion, addition, combination, exchange of sequences, etc. to certain technical features, so as to obtain a technical solution still following the inventive concept. Such solutions without departing from the technical idea of the invention are also within the scope of protection of the invention.
The double-track protocol has fast data transmission rate, uses two lines (a pair) to represent 1-bit information, has good robustness and stability, and is not influenced by wire delay. Therefore, the invention focuses on flexible and rapid conversion between the four-phase double-track protocol and the two-phase double-track protocol so as to realize efficient data communication.
Fig. 1 is a schematic diagram of a protocol conversion circuit according to an embodiment of the present invention, which can convert a four-phase dual-track data protocol handshaking between a transmitting end 1 and a receiving end 1 into a two-phase dual-track protocol according to actual needs, for example, the conversion circuit 1, or/and convert a two-phase dual-track protocol handshaking between a transmitting end 2 and the receiving end 2 into a four-phase dual-track protocol, for example, the conversion circuit 2, so that a converted signal can be well adapted to the receiving end.
In the dual-rail protocol, line d.t represents a true (true) information or logic 1 signal for the corresponding bit, line d.f represents a false (false) information or logic 0 signal for the corresponding bit, and for an N-bit channel, corresponds to N pairs of lines { d.t, d.f } in parallel. Illustratively, only 1-bit lanes are shown in fig. 1, d.t _4_phase represents true value information adapted to a four-phase dual-track protocol, d.f _4_phase represents false value information adapted to the four-phase dual-track protocol, and correspondingly d.t _2_phase represents true value information adapted to a two-phase dual-track protocol, d.f _2_phase represents false value information adapted to the two-phase dual-track protocol, and ack_4_phase and ack_2_phase represent acknowledgement signals in the four-phase dual-track protocol and the two-phase dual-track protocol, respectively.
Fig. 2 is a schematic diagram of a first conversion circuit according to an embodiment of the present invention, where the first conversion is to convert a four-phase dual-rail protocol signal into a two-phase dual-rail protocol signal. The first converting circuit includes a first data signal converter and a first handshake signal converter, the transmitting end includes data lines d.t _4_phase, d.f _4_phase, and acknowledgement line ack_4_phase, and the receiving end includes data lines d.t _2_phase, d.f _2_phase, and acknowledgement line ack_2_phase.
This embodiment is illustrated with a 1 pair line of 1 bit lanes, the first data signal converter comprising an exclusive or gate 101 and a first logic section, wherein the first logic section comprises C cells 102, 103, d flip-flops 104, 105, inverters 106, 107. The first handshake signal converter comprises a C-unit 108 and an edge detection circuit 109.
The exclusive or gate 101 performs exclusive or operation on a pair of signals { d.t _4_phase, d.f_4_phase } representing 1-bit data sent from the transmitting terminal. The two inputs of AND gate 102 are respectively coupled to the data signal d.t _4_phase and the output of exclusive OR gate 101The output of the AND gate 102 is coupled to the clock control terminal (CK) of the D flip-flop 104, the output of the D flip-flop 104 is a data signal d.t _2_phase adapted to the two-phase dual-rail protocol, and the output of the D flip-flop 104 is coupled to the data terminal (D) of the D flip-flop 104 after being inverted by the inverter 106. The two input terminals of the and gate 103 are coupled to the output of the data signal d.f _4_phase and the output of the exclusive or gate 101, the output of the and gate 103 is coupled to the clock control terminal (CK) of the D flip-flop 105, the output of the D flip-flop 105 is the data signal d.f _2_phase adapted to the two-phase dual track protocol, and the output of the D flip-flop 105 is coupled to the data terminal (D) of the D flip-flop 105 after being inverted by the inverter 107.
Meanwhile, the first handshake signal converter detects whether the response signal ack_2_phase returned by the receiving end is hopped by using the edge detection circuit 109, and two input ends of the C unit 108 are respectively coupled with the output of the exclusive or gate 101 and the output of the edge detection circuit, so as to convert the response signal ack_2_phase in the two-phase dual-track protocol into the response signal ack_4_phase adapted to the four-phase dual-track protocol.
Alternatively, in some class of embodiments, the exclusive or gate 101 is replaced with an or gate.
Fig. 3a is a schematic diagram of a first data signal converter, which includes N parallel first data signal converting units, such as first data signal converting unit_1 to first data signal converting unit_n. The first data signal converter is configured to convert N-bit data signals { d0.t_4_phase, d0.f_4_phase } to { dn.t_4_phase, dn.f_4_phase } adapted to a four-phase dual-track protocol into N-bit data signals { d0.t_2_phase, d0.f_2_phase } to { dn.t_2_phase, dn.f_2_phase } adapted to a two-phase dual-track protocol, where N represents a communication bit number and the N-bit channel has N data lines { d.t, d.f }.
Wherein, for a pair of signals { d.t, d.f } representing each bit of data, one first data signal conversion unit is corresponding.
The first data signal conversion unit includes a first exclusive-or gate and a first logic portion (the first logic portion_1 or the first logic portion_n are stacked as shown), and is configured to convert a pair of data signals in the dual-track protocol from a four-phase encoding format to a two-phase encoding format.
A first exclusive OR gate for exclusive-or-ing the true value information and false value information in a pair of data lines to obtain a logic operation resultWherein->[0:N-1]I.e. i belongs to an integer between 0 and N-1.
The first logic part converts the true value information and the false value information which are adapted to the four-phase double-track protocol in the data line into the true value information and the false value information which are adapted to the two-phase double-track protocol based on the output of each first exclusive OR gate and the true value information and the false value information in the data line.
Illustratively, the first logic includes a first branch that converts true value information and a second branch that converts false value information.
The first branch circuit comprises a first AND gate and a first D trigger, the first AND gate carries out logic AND on the output of the first exclusive OR gate and the true value information in the data line, the output of the first AND gate is used as a clock control end of the first D trigger, and the output of the first D trigger is the true value information of the pair of data lines adapted to the two-phase double-track protocol.
The second branch circuit comprises a second AND gate and a second D trigger, the second AND gate carries out logic AND on the output of the first exclusive OR gate and false value information in the data line, the output of the second AND gate is used as a clock control end of the second D trigger, and the output of the second D trigger is the false value information of the pair of data lines which is adapted to the two-phase double-track protocol.
Fig. 3b is a schematic diagram of a first handshake signal converter for converting a two-phase dual-rail acknowledgement signal ack_2_phase returned by a receiving end into a four-phase dual-rail acknowledgement signal ack_4_phase. The first handshake signal converter includes an edge first edge detection circuit, a first C-cell, and a second logic.
The first edge detection circuit is used for detecting whether the two-phase double-track response signal ack_2_phase returned by the receiving end is in jump or not, and when the jump, namely the rising edge or/and the falling edge, of the two-phase double-track response signal ack_2_phase is detected, an indication is generated.
Optionally, the edge detection circuit of the present invention adopts an asynchronous circuit logic design, specifically, the present invention is incorporated by reference in its entirety into this prior art (application number: 202310862286.3, publication number: CN116582113a, publication date: 2023.08.11, name: asynchronous edge detection circuit, slave circuit and chip), based on an event driven mechanism. When the edge detection circuit detects a transition, an event (event), also called a pulse event (spike), is generated.
A second logic section based on the outputs of the first exclusive-OR gates in the N first data signal conversion unitsPerforming logic operation, wherein ∈R is marked>[0:N-1]The output out is obtained.
And the two input ends of the first C unit are respectively coupled with the output of the edge detection circuit and the output of the second logic part, and state tracking is performed based on the two input ends of the first C unit.
The C unit is a common basic unit in asynchronous circuit design, and the change of the output of the C unit can indicate or confirm the change condition of other signals. The advantage of using a C-cell in an asynchronous circuit is that even if the input changes very quickly, it can be recorded and tracked and responded in a timely manner. The output of the C cell remains unchanged when its two inputs a, b are not identical.
FIG. 4 is a schematic diagram of a second logic portion according to some embodiments of the invention. Parts (a) to (d) of fig. 4 correspond to the case where the first data signal converter converts 2-bit to 5-bit data signals, respectively.
The second logic part comprises a plurality of C units, the number of the C units is the number of the second logic part inputs minus 1, and the number of the second logic part inputs is equal to the number of the first exclusive-OR gates in the first data signal converter and is also equal to the number N of data signal bits required to be converted by the first data signal converter.
The plurality of C units in the second logic part are divided into at least one stage, wherein the output of the first stage C unit is processed by the second stage C unit comprising a plurality of C units until the last stage C unit has only 1C unit, and the output of the last stage C unit is the output out of the second logic part; the output of every two C units in the former stage C unit is used as the input of one C unit in the latter stage C unit; the output of 1C unit in the last stage C unit is used as a request signal in four-phase binding data protocol data.
FIG. 5 is a schematic diagram of a second conversion circuit according to an embodiment of the present invention, wherein the second conversion is to convert a two-phase dual-rail protocol signal into a four-phase dual-rail protocol signal. The second conversion circuit includes a second data signal converter and a second handshake signal converter, the transmitting end includes data lines d.t _2_phase, d.f _2_phase, and acknowledgement line ack_2_phase, and the receiving end includes data lines d.t _4_phase, d.f _4_phase, and acknowledgement line ack_4_phase.
This embodiment is exemplified with a 1 pair line of 1 bit lanes, and the second data signal converter comprises edge detection circuits 201 and 202, c cells 203 and 204.
The edge detection circuits 201 and 202 monitor whether a pair of signals { d.t _2_phase, d.f_2_phase } representing 1-bit data, respectively, have transitions, and generate an indication when the monitored signals have rising edges or/and falling edges.
The two input ends of the C unit 203 are coupled to the output of the edge detection circuit 201 and the inverse (i.e. the inversion signal: iack_4_phase) of the four-phase dual-track response signal returned by the receiving end, so as to obtain the true value information d.t _4_phase of the four-phase dual-track protocol, which is adapted to the corresponding bit.
The C unit 204 has two inputs coupled to the output of the edge detection circuit 202 and the inverse (i.e., the inversion signal: iack_4_phase) of the four-phase dual-track response signal returned by the receiving end, so as to obtain the dummy value information d.f _4_phase corresponding to the bit adaptation to the four-phase dual-track protocol.
The second handshake signal converter comprises a D trigger 205 and an inverter 206, wherein a four-phase double-track response signal ack_4_phase returned by a receiving end is coupled to a clock control end of the D trigger 205,
the output of the D flip-flop 205 is an acknowledge signal ack_2_phase adapted to the two-phase dual-track protocol, and the output of the D flip-flop 205 is coupled to the data terminal (D) of the D flip-flop 205 after being inverted by the inverter 206.
Fig. 6 is a schematic diagram of a second switching circuit according to another embodiment of the present invention, including a second data signal converter and a second handshake signal converter.
The second data signal converter includes N parallel second data signal converting units, such as second data signal converting unit_1 to second data signal converting unit_n. The second data signal converter is configured to convert N-bit data signals { d0.t_2_phase, d0.f_2_phase } to { dn.t_2_phase, dn.f_2_phase } adapted to the two-phase dual-track protocol into N-bit data signals { d0.t_4_phase, d0.f_4_phase } to { dn.t_4_phase, dn.f_4_phase } adapted to the two-phase dual-track protocol, where N represents a number of communication bits, is an integer greater than or equal to 1, and the N-bit channel has N-data lines { d.t, d.f }.
Similarly, for a pair of signals { d.t, d.f } representing each bit of data, one second data signal conversion unit is corresponding.
The second data signal converting unit comprises two branches, including a third branch for converting true value information and a fourth branch for converting false value information.
The third branch comprises a second edge detection circuit and a second C unit, wherein the second edge detection circuit monitors whether the true value information in a pair of data lines is in jump, and generates an indication when the jump, namely the rising edge or/and the falling edge, is detected.
The second C unit generates true value information suitable for the four-phase double-track protocol based on the indication of the second edge detection circuit and the inverse (namely, the inverse signal: iack_4_phase) of the four-phase double-track response signal returned by the receiving end.
The fourth branch comprises a third edge detection circuit and a third C unit, the third edge detection circuit monitors whether the false information in the pair of data lines is in jump or not, and when the jump, namely the rising edge or/and the falling edge is detected, an indication is generated.
The third C unit generates false value information suitable for the four-phase double-track protocol based on the indication of the third edge detection circuit and the inverse (namely, the inverse signal: iack_4_phase) of the four-phase double-track response signal returned by the receiving end.
The second handshake signal converter comprises a third D flip-flop. The four-phase dual-track response signal ack_4_phase returned by the receiving end is used as a clock control end of a third D trigger, and the output of the third D trigger is the response signal ack_2_phase of the pair of data lines adapted to the two-phase dual-track protocol of the transmitting end.
Alternatively, in some embodiments, the invention has been described above in terms of any D flip-flop in the embodiments being replaced with a latch. But preferably, using a D flip-flop with a high Yu Suocun performance, the latches are unstable and prone to glitches.
Optionally, in any of the foregoing embodiments, in the first conversion circuit or/and the second conversion circuit of the present invention, a buffer unit or a delay unit may be inserted at any position as required.
Optionally, for the xor gate at any position in the invention, at least one xor gate can be replaced by an or gate, and the or gate has lower complexity, smaller area and lower power consumption relatively. Preferably all exclusive or gates are replaced with or gates.
Fig. 7 is a timing diagram of a first switching circuit according to an embodiment of the present invention, taking a 2-bit data signal as an example, a transmitting end includes a data signal { d.t [1:0] _4_phase, d.f [1:0] _4_phase } and a four-phase dual-track response signal ack_4_phase adapted to a four-phase dual-track protocol, and a receiving end includes a data signal { d.t [1:0] _2_phase, d.f [1:0] _2_phase } and a two-phase dual-track response signal ack_2_phase adapted to a two-phase dual-track protocol.
The conversion process is approximately as follows: transmitting data by a transmitting end; the first conversion circuit converts the data sent by the sending end into a data format required by the receiving end, and the receiving end receives the data after finding that the data is effective; after receiving the valid data, the receiving end receives the two-phase double-track response signal ack_2_phase jump (rising edge or falling edge); when the two-phase double-track response signal is identified to be effective, the four-phase double-track response signal ack_4_phase returned to the transmitting end is pulled high (set to be effective at high level); the data of the transmitting end becomes empty; the transmitting end pulls down the four-phase double-track response signal ack_4_phase; thereby completing protocol conversion and one-time handshake.
Fig. 8 is a timing diagram of a second switching circuit according to another embodiment of the present invention, taking a 2-bit data signal as an example, the transmitting end includes data signals { d.t [1:0] _2_phase, d.f [1:0] _2_phase } and two-phase dual-track response signal ack_2_phase adapted to two-phase dual-track protocol, and the receiving end includes data signals { d.t [1:0] _4_phase, d.f [1:0] _4_phase } and four-phase dual-track response signal ack_4_phase adapted to four-phase dual-track protocol.
The conversion process is approximately as follows: the transmitting end starts to transmit data; after the receiving end finds that the data is valid, the receiving end starts to receive the data; after the receiving end receives the four-phase double-track response signal ack_4_phase, pulling high; when the four-phase double-track response signal is identified to be effective, returning a two-phase double-track response signal ack_2_phase jump to the transmitting end, and completing protocol conversion and handshake by the transmitting end; the receiving end data becomes empty; subsequently, the receiving end pulls down the four-phase double-track response signal ack_4_phase, and the receiving end completes protocol conversion and handshake.
In some embodiments, the protocol conversion circuit described in the previous embodiments of the present invention is applied to an interface.
In some embodiments, the protocol conversion circuit described in the previous embodiments of the present invention is applied to a chip. Optionally, the chip is a chip implemented based on an asynchronous circuit.
Because the asynchronous circuit is more attached to a biological reaction mechanism, more and more AI chips adopt asynchronous circuit designs, such as bionic visual sensors, rapidly feel dynamic information based on the change of light intensity in a visual field, and asynchronously output sparse event streams, such as event imaging devices; and the neuromorphic processor realizes neuron dynamics based on an asynchronous and event-driven mechanism, breaks through the traditional von neumann architecture, and has the characteristics of ultra-low power consumption and ultra-low delay.
Alternatively, the aforementioned chip is a neuromorphic chip or a chip designed based on event driving.
Preferably, the chip is a neuromorphic sensor or neuromorphic processor.
The invention relates to an electronic device comprising the chip. The electronic device may be various low power consumption devices.
In the present invention, "switching" means a switching direction of data to be transmitted, and is generally opposite to the direction of a response signal.
Although the present invention has been described with reference to specific features and embodiments thereof, various modifications, combinations, substitutions can be made thereto without departing from the invention. The scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but rather, the methods and modules may be practiced in one or more products, methods, and systems of the associated, interdependent, inter-working, pre/post stages.
The specification and drawings are, accordingly, to be regarded in an abbreviated manner as an introduction to some embodiments of the technical solutions defined by the appended claims and are thus to be construed in accordance with the doctrine of greatest reasonable interpretation and are intended to cover as much as possible all modifications, changes, combinations or equivalents within the scope of the disclosure of the invention while also avoiding unreasonable interpretation.
Further improvements in the technical solutions may be made by those skilled in the art on the basis of the present invention in order to achieve better technical results or for the needs of certain applications. However, even if the partial improvement/design has creative or/and progressive characteristics, the technical idea of the present invention is relied on to cover the technical features defined in the claims, and the technical scheme shall fall within the protection scope of the present invention.
The features recited in the appended claims may be presented in the form of alternative features or in the order of some of the technical processes or the sequence of organization of materials may be combined. Those skilled in the art will readily recognize that such modifications, changes, and substitutions can be made herein after with the understanding of the present invention, by changing the sequence of the process steps and the organization of the materials, and then by employing substantially the same means to solve substantially the same technical problem and achieve substantially the same technical result, and therefore such modifications, changes, and substitutions should be made herein by the equivalency of the claims even though they are specifically defined in the appended claims.
The steps and components of the embodiments have been described generally in terms of functions in the foregoing description to clearly illustrate this interchangeability of hardware and software, and in terms of various steps or modules described in connection with the embodiments disclosed herein, may be implemented in hardware, software, or a combination of both. Whether such functionality is implemented as hardware or software depends upon the particular application or design constraints imposed on the solution. Those of ordinary skill in the art may implement the described functionality using different approaches for each particular application, but such implementation is not intended to be beyond the scope of the claimed invention.
Claims (12)
1. The conversion device realizes the conversion from four-phase double-track protocol to two-phase double-track protocol data, and is characterized in that:
comprising a first data signal converter and a first handshake signal converter;
the first data signal converter comprises N parallel first data signal conversion units, wherein N represents the communication bit number and is greater than or equal to 1;
the first data signal conversion unit is used for converting a pair of data signals representing one-bit information in the double-track protocol from a four-phase coding format to a two-phase coding format;
the first handshake signal converter converts a two-phase double-track response signal returned by the receiving end into a four-phase double-track response signal suitable for the transmitting end;
the first data signal conversion unit comprises a first exclusive-or gate and a first logic part;
a first exclusive OR gate for exclusive-or-ing the true value information and false value information in any pair of input data signals to obtain logic operation resultWherein->An integer from 0 to N-1;
the first logic part converts the true value information and the false value information which are adapted to the four-phase double-track protocol of the transmitting end into the true value information and the false value information which are adapted to the two-phase double-track protocol of the receiving end based on the output of the first exclusive OR gate and the true value information and the false value information in any pair of input data signals;
the first handshake signal converter detects whether a two-phase double-track response signal returned by the receiving end has jump, generates a first indication when the jump is detected, and obtains a four-phase double-track response signal adapted to the transmitting end based on the first indication and the output of a first exclusive-OR gate in the N parallel first data signal conversion units.
2. The conversion device according to claim 1, wherein:
the first logic portion includes a first branch that converts true value information and a second branch that converts false value information.
3. The conversion device according to claim 2, wherein:
the first branch circuit comprises a first AND gate and a first D trigger;
the first AND gate carries out logic AND on the output of the first exclusive OR gate and the true value information in the corresponding data line, the output of the first AND gate is used as a clock control end of a first D trigger, and the output of the first D trigger is the true value information of the corresponding data line adapted to the two-phase double-track protocol;
the second branch circuit comprises a second AND gate and a second D trigger, the second AND gate carries out logic AND on the output of the first exclusive OR gate and false value information in the corresponding data line, the output of the second AND gate is used as a clock control end of the second D trigger, and the output of the second D trigger is the false value information which is adaptive to the two-phase double-track protocol for the corresponding data line.
4. The conversion device according to claim 1, wherein:
and detecting whether the two-phase double-track response signal returned by the receiving end has jump or not by using an asynchronous edge detection circuit.
5. The conversion device according to claim 4, wherein:
the first handshake signal converter comprises a second logic and a first C-unit,
the second logic part is used for carrying out logic operation on the output of the first exclusive-OR gates in the N first data signal conversion units;
the first C unit is used for carrying out state tracking on the output of the second logic part and the output of the asynchronous edge detection circuit.
6. The switching device according to any one of claims 1 to 5, wherein:
the first exclusive or gate is replaced by an or gate.
7. The switching device of claim 5, wherein:
the second logic part comprises a plurality of C units, the plurality of C units are divided into at least one stage, wherein the output of the first stage C unit is processed by the second stage C unit comprising a plurality of C units until the last stage C unit has only 1C unit, and the output of the last stage C unit is the output of the second logic part;
the output of every two C units in the former stage C unit is used as the input of one C unit in the latter stage C unit; the output of 1C unit in the last stage C unit is used as a request signal in four-phase binding data protocol data.
8. The conversion device realizes the conversion from two-phase double-track protocol to four-phase double-track protocol data, and is characterized in that:
comprising a second data signal converter and a second handshake signal converter;
a second data signal converter including N parallel second data signal conversion units, N representing the number of communication bits, and N being greater than or equal to 1;
the second data signal conversion unit is used for converting a pair of data signals representing one-bit information in the double-track protocol from a two-phase coding format to a four-phase coding format;
the second handshake signal converter converts the four-phase double-track response signal returned by the receiving end into a two-phase double-track response signal which is suitable for the transmitting end;
the second data signal conversion unit comprises a third branch for converting true value information and a fourth branch for converting false value information;
the third branch circuit comprises a second edge detection circuit and a second C unit;
the second edge detection circuit is used for monitoring whether the true value information in the corresponding data line is jumped or not, and generating a second indication if the true value information in the corresponding data line is jumped;
the second C unit generates true value information adapted to a four-phase double-track protocol based on the second indication and the inverse of the four-phase double-track response signal returned by the receiving end;
the fourth branch comprises a third edge detection circuit and a third C unit;
the third edge detection circuit is used for monitoring whether the false value information in the corresponding data line is jumped or not, and generating a third indication if the jump exists;
and the third C unit generates false value information adapted to a four-phase double-track protocol based on the third indication and the inverse of the four-phase double-track response signal returned by the receiving end.
9. The conversion device according to claim 8, wherein:
the second handshake signal converter comprises a third D flip-flop;
the clock control end of the third D trigger is coupled with the four-phase double-track response signal returned by the receiving end, and the output of the third D trigger is the two-phase double-track response signal which corresponds to the data line and is adapted to the transmitting end.
10. A chip, characterized in that:
comprising a conversion device according to any one of claims 1 to 7, or/and comprising a conversion device according to any one of claims 8 to 9.
11. The chip of claim 10, wherein:
the chip is a neuromorphic chip or a chip designed based on event driving.
12. An electronic device, characterized in that:
the electronic device comprising a chip as claimed in claim 10 or 11.
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| CN105355229A (en) * | 2015-10-29 | 2016-02-24 | 同济大学 | Write circuit and read circuit of asynchronous circuit system for synchronous random-access memory |
| CN116582113A (en) * | 2023-07-14 | 2023-08-11 | 深圳时识科技有限公司 | Asynchronous edge detection circuit, slave circuit and chip |
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| CN105355229A (en) * | 2015-10-29 | 2016-02-24 | 同济大学 | Write circuit and read circuit of asynchronous circuit system for synchronous random-access memory |
| CN116582113A (en) * | 2023-07-14 | 2023-08-11 | 深圳时识科技有限公司 | Asynchronous edge detection circuit, slave circuit and chip |
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