CN116582113A - Asynchronous edge detection circuit, slave circuit and chip - Google Patents

Asynchronous edge detection circuit, slave circuit and chip Download PDF

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Publication number
CN116582113A
CN116582113A CN202310862286.3A CN202310862286A CN116582113A CN 116582113 A CN116582113 A CN 116582113A CN 202310862286 A CN202310862286 A CN 202310862286A CN 116582113 A CN116582113 A CN 116582113A
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logic
output
edge detection
detection circuit
asynchronous
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CN116582113B (en
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张华秋
乔宁
白鑫
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Shenzhen Shizhi Technology Co ltd
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Shenzhen Shizhi Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses an asynchronous edge detection circuit, a slave circuit and a chip. To solve the problem of how to develop an edge detection circuit based on a traditional commercial EDA tool and capable of exerting the advantages of an asynchronous circuit in the prior art, the asynchronous edge detection circuit of the invention comprises: the first logic section I and the second logic section II generate instructions based on the input of the asynchronous edge detection circuit and the change of the output of the asynchronous edge detection circuit, the third logic section III resets and confirms the instructions generated by the first logic section and the second logic section, and the fourth logic section IV outputs events based on the instructions of the third logic section III. The invention has simple structure, outstanding modularization, high processing speed, low power consumption and strong anti-interference performance, and can carry out commercial design based on EDA tools. The invention is applicable to the field of asynchronous circuits or neuromorphics.

Description

Asynchronous edge detection circuit, slave circuit and chip
Technical Field
The present invention relates to an asynchronous edge detection circuit, a slave circuit, and a chip, and more particularly, to an asynchronous edge detection circuit, a slave circuit, and a chip that realize high speed and low power consumption using EDA.
Background
With the development of artificial intelligence technology, the processing speed and power consumption of a large-scale neural network face serious tests, and the neuromorphic engineering also gets more and more attention, and the neuromorphic engineering is more attached to a biological reaction mechanism than the traditional artificial intelligence technology. The neuromorphic vision sensor serving as a perception representative rapidly senses dynamic information based on the change of light intensity in a visual field and asynchronously outputs sparse event streams, such as an event camera; the brain-like computation, which is representative of processing or decision, breaks through the traditional von neumann architecture, utilizes pulse (spike) communication based on an asynchronous and event-driven mechanism, realizes neuron dynamics through a circuit, achieves excellent performance in the aspect of efficiently processing complex, sparse and noisy space-time information, and has remarkable advantages in power consumption, computational overhead and cost.
However, the asynchronous circuit has no clock and complex design, and the existing EDA tool cannot directly support the design of the asynchronous circuit, and under the compromise consideration, some technologies still develop a neuromorphic chip based on a synchronous circuit, or use an asynchronous-synchronous hybrid scheme, such as a brain-like chip TrueNorth of IBM, to adopt a design concept of global asynchronization and local synchronization. Although the technology reduces the design difficulty, the advantages of the asynchronous circuit such as rapidness, low power consumption, low cost, low noise, interference resistance and the like are avoided to a certain extent, and meanwhile, the performance of the synchronous circuit is approaching to the limit along with the fact that the semiconductor technology falls into the bottleneck.
How to develop a modular asynchronous circuit based on the traditional commercial EDA tool that can take advantage of the asynchronous circuit is a great challenge in the art.
Edge detection is the basic technology of communication, and is currently developed based on synchronous circuit technology, such as the prior art 1: WO2021199955A1, prior art 2: US20020196052A1, etc. How to develop an asynchronous edge detection circuit based on a commercial EDA tool so as to exert the advantages of the asynchronous circuit and realize stable, effective and low-power-consumption edge detection is a problem to be solved.
Disclosure of Invention
In order to solve or alleviate some or all of the above technical problems, the present invention is implemented by the following technical solutions:
the first type of asynchronous edge detection circuit comprises a first logic part I, a second logic part II, a third logic part III and a fourth logic part IV;
the first logic part I and the second logic part II are used for generating an instruction based on the input signal of the asynchronous edge detection circuit and the change of the output of the asynchronous edge detection circuit;
the third logic part III is coupled with the output of the first logic part and the output of the second logic part simultaneously and is used for resetting and confirming the change condition of the output of the first logic part and the output of the second logic part;
the fourth logic IV is coupled to the output of the third logic III, outputting an event based on the indication of the third logic III.
In some embodiments, the first logic section I includes a first C-cell, two inputs of the first C-cell are respectively coupled to an input signal of the asynchronous edge detection circuit and an inverse of an output of the asynchronous edge detection circuit, and generate a first indication;
the second logic section II comprises a second C unit, wherein two inputs of the second C unit are respectively coupled with the inverse of the input signal of the asynchronous edge detection circuit and the inverse of the output of the asynchronous edge detection circuit, and generate a second indication.
In certain classes of embodiments, the third logic III includes first and second multiplexers and a third C-unit;
the second input end of the first multiplexer is coupled with the output of the first C unit, the first input end of the first multiplexer is coupled with logic 0, and the output of the first multiplexer is coupled with the first input of the third C unit;
the second input terminal of the second multiplexer is coupled to the output of the second C-unit, the first input terminal of the second multiplexer is coupled to logic 0, the output of the second multiplexer is coupled to the second input of the third C-unit, and the output of the third C-unit is used as the output of the third logic section III.
In some class of embodiments, the third C unit is replaced with a third and gate.
In certain classes of embodiments, the third AND gate is a tri-state gate.
In some class of embodiments, the third AND gate is reset or/and the first multiplexer are reset.
In some class of embodiments, an inverse reset of the asynchronous edge detection circuit output is utilized.
In some class of embodiments, the asynchronous edge detection circuit outputs a third AND gate reset or/and the first multiplexer reset after being delayed by at least one buffer unit or delay unit.
In certain classes of embodiments, the third logic section III comprises a tri-state and gate;
the two input ends of the tri-state AND gate are respectively coupled with the outputs of the first C unit and the second C unit, and the output of the tri-state AND gate is the output of the third logic part III.
In some class of embodiments, the tri-state AND gate is reset with the inverse of the asynchronous edge detection circuit output.
In some types of embodiments, the fourth logic IV includes a first and a second and gate, and an or gate;
the first AND gate carries out logical AND on the output of the third C unit and the input signal of the asynchronous edge detection circuit and then outputs the output, and the second AND gate carries out logical AND on the output of the third C unit and the inverse of the input signal of the asynchronous edge detection circuit and then outputs the output;
the OR gate performs logic OR post output event on the outputs of the first AND gate and the second AND gate as the output of the asynchronous edge detection circuit.
In some class of embodiments, the fourth logic IV comprises a first and gate;
the first AND gate carries out logic AND on the output of the third C unit and the input signal of the asynchronous edge detection circuit and then outputs the output as the output of the asynchronous edge detection circuit.
In some class of embodiments, the fourth logic IV comprises a second and gate;
the second AND gate outputs the output of the third C unit and the inverse of the input signal of the asynchronous edge detection circuit as the output of the asynchronous edge detection circuit.
The second type of asynchronous edge detection circuit comprises a first logic part I, a second logic part II, a third logic part III and a fourth logic part IV;
the first logic part I and the second logic part II are used for indicating the change condition of an input signal of an asynchronous edge detection circuit and a confirmation signal returned to the asynchronous edge detection circuit by a later-stage circuit;
the third logic part III is coupled with the output of the first logic part and the output of the second logic part simultaneously and is used for resetting and confirming the change condition of the output of the first logic part and the output of the second logic part;
the fourth logic IV is coupled to the output of the third logic III, and indicates an event of a rising edge or a falling edge based on an instruction output of the third logic III.
In certain embodiments, the first logic section I includes a first C cell and the second logic section II includes a second C cell; the back-end circuit is coupled to the first input end of the first C unit and the first input end of the second C unit in a reverse-simultaneous manner of a confirmation signal returned to the asynchronous edge detection circuit;
the second input end of the first C unit is coupled with the input signal of the asynchronous edge detection circuit and generates a first indication; the second input terminal of the second C unit is coupled to the input signal of the asynchronous edge detection circuit and generates a second indication.
In certain classes of embodiments, the third logic III includes a first multiplexer, a second multiplexer, and a third C-unit;
the second input end of the first multiplexer is coupled with the output of the first C unit, the first input end of the first multiplexer is coupled with logic 0, and the output of the first multiplexer is coupled with the first input of the third C unit;
the second input terminal of the second multiplexer is coupled to the output of the second C-unit, the first input terminal of the second multiplexer is coupled to logic 0, the output of the second multiplexer is coupled to the second input of the third C-unit, and the output of the third C-unit is used as the output of the third logic section III.
In some class of embodiments, the third C unit is replaced with a third and gate.
In certain classes of embodiments, the third AND gate is a tri-state gate.
In some class of embodiments, the third AND gate is reset or/and the first multiplexer are reset.
In some class of embodiments, the reset is a reset of an acknowledge signal returned to the asynchronous edge detection circuit by the post-stage circuit.
In certain classes of embodiments, the third logic section III comprises a tri-state and gate;
the two input ends of the tri-state AND gate are respectively coupled with the outputs of the first C unit and the second C unit, and the output of the tri-state AND gate is the output of the third logic part.
In certain types of embodiments, the tri-state AND gate is reset with an acknowledge signal returned by the post-stage circuit to the asynchronous edge detection circuit.
In some class of embodiments, the fourth logic IV comprises a first and gate and a second and gate;
the first AND gate carries out logic AND on the output of the third C unit and an input signal of the asynchronous edge detection circuit and then outputs the output so as to indicate a rising edge event;
the second AND gate carries out logical AND on the output of the third C unit and the inverse of the input signal of the asynchronous edge detection circuit to output the output so as to indicate a falling edge event;
the confirmation signals returned to the asynchronous edge detection circuit by the back-stage circuit comprise a rising edge event confirmation signal and a falling edge event confirmation signal;
one of a rising-edge event acknowledge signal and a falling-edge event acknowledge signal is outputted by OR gate selection as an acknowledge signal returned from the post-stage circuit to the asynchronous edge detection circuit.
In some embodiments, the post-stage circuit is a circuit that returns a rising-edge event acknowledge signal and a falling-edge event acknowledge signal simultaneously; or the back-end circuit is two circuits, and respectively returns a rising edge event confirmation signal and a falling edge event confirmation signal.
In some class of embodiments, the fourth logic IV comprises a first and gate;
the first AND gate carries out logic AND on the output of the third C unit and an input signal of the asynchronous edge detection circuit and then outputs the output so as to indicate a rising edge event;
the confirmation signal returned by the back-end circuit to the asynchronous edge detection circuit is a rising edge event confirmation signal.
In some class of embodiments, the fourth logic IV comprises a second and gate;
the second AND gate carries out logic AND on the output of the third C unit and an input signal of the asynchronous edge detection circuit and then outputs the output so as to indicate a falling edge event;
the confirmation signal returned by the back-end circuit to the asynchronous edge detection circuit is a falling edge event confirmation signal.
A slave circuit, the slave circuit being an asynchronous slave circuit; the slave circuit implements edge detection using the asynchronous edge detection circuit described previously.
A chip comprising a slave circuit as hereinbefore described.
Some or all embodiments of the present invention have the following beneficial technical effects:
1) The edge detection circuit based on the logic design of the asynchronous circuit has the advantages of high processing speed, low power consumption and strong anti-interference performance, and can obviously exert the advantages of the asynchronous circuit.
2) The asynchronous edge detection circuit is realized based on an event-driven mechanism, has a simple structure and prominent modularization, and can be commercially designed based on an EDA tool.
3) The asynchronous edge detection circuit can effectively prevent the phenomena of metastability, competition, adventure and the like, and has high stability and reliability.
4) The asynchronous edge detection circuit has high precision, good detection effect, performance free from process limitation and easy test.
Further advantageous effects will be further described in the preferred embodiments.
The above-described technical solutions/features are intended to summarize the technical solutions and technical features described in the detailed description section, and thus the ranges described may not be exactly the same. However, these new solutions disclosed in this section are also part of the numerous solutions disclosed in this document, and the technical features disclosed in this section and the technical features disclosed in the following detailed description section, and some contents in the drawings not explicitly described in the specification disclose more solutions in a reasonable combination with each other.
The technical scheme combined by all the technical features disclosed in any position of the invention is used for supporting the generalization of the technical scheme, the modification of the patent document and the disclosure of the technical scheme.
Drawings
FIG. 1 is a schematic diagram of an asynchronous edge detection circuit according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of the logic relationship between input and output of a C cell (Muller C);
FIG. 3 is a waveform diagram of an asynchronous edge detection circuit according to a first embodiment of the present invention;
FIG. 4 is a schematic diagram of an asynchronous edge detection circuit according to a second embodiment of the present invention;
FIG. 5 is a waveform diagram of an asynchronous edge detection circuit according to a second embodiment of the present invention;
FIG. 6 is a schematic diagram of an asynchronous edge detection circuit according to a third embodiment of the present invention;
FIG. 7 is a waveform diagram of an asynchronous edge detection circuit according to a third embodiment of the present invention;
FIG. 8 is an asynchronous edge detection circuit of a fourth embodiment of the present invention;
fig. 9 is an exemplary waveform diagram of an asynchronous edge detection circuit of a fourth embodiment of the present invention;
FIG. 10 is a schematic diagram of an asynchronous edge detection circuit according to a fifth embodiment of the present invention;
FIG. 11 is a schematic diagram of an asynchronous edge detection circuit according to a sixth embodiment of the present invention;
FIG. 12 is a schematic diagram of an asynchronous edge detection circuit according to a seventh embodiment of the present invention;
FIG. 13 is a schematic diagram of an asynchronous edge detection circuit according to an eighth embodiment of the present invention;
FIG. 14 is a schematic diagram of an asynchronous edge detection circuit according to a ninth embodiment of the present invention;
fig. 15 is a schematic diagram of an asynchronous edge detection circuit according to a tenth embodiment of the present invention.
Detailed Description
Since various alternatives are not exhaustive, the gist of the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. Other technical solutions and details not disclosed in detail below, which generally belong to technical objects or technical features that can be achieved by conventional means in the art, are limited in space and the present invention is not described in detail.
Except where division is used, any position "/" in this disclosure means a logical "or". The ordinal numbers "first", "second", etc., in any position of the present invention are used merely for distinguishing between the labels in the description and do not imply an absolute order in time or space, nor do they imply that the terms preceded by such ordinal numbers are necessarily different from the same terms preceded by other ordinal terms.
The present invention will be described in terms of various elements for use in various combinations of embodiments, which elements are to be combined in various methods, products. In the present invention, even if only the gist described in introducing a method/product scheme means that the corresponding product/method scheme explicitly includes the technical feature.
The description of a step, module, or feature in any location in the disclosure does not imply that the step, module, or feature is the only step or feature present, but that other embodiments may be implemented by those skilled in the art with the aid of other technical means according to the disclosed technical solutions. The embodiments of the present invention are generally disclosed for the purpose of disclosing preferred embodiments, but it is not meant to imply that the contrary embodiments of the preferred embodiments are not intended to cover all embodiments of the invention as long as such contrary embodiments are at least one technical problem addressed by the present invention. Based on the gist of the specific embodiments of the present invention, a person skilled in the art can apply means of substitution, deletion, addition, combination, exchange of sequences, etc. to certain technical features, so as to obtain a technical solution still following the inventive concept. Such solutions without departing from the technical idea of the invention are also within the scope of protection of the invention.
The important technology for detecting signal change by signal edge detection is the basic technology of signal communication. Such as communication protocols PCI (Peripheral Component Interconnection), I2C (Inter-Integrated Circuit) common in interface systems, etc., signal edge detection, especially edge detection of clock lines, is essential. Meanwhile, most of neuromorphic chips with excellent performance are developed based on asynchronous circuits, and how to design an edge detection circuit based on an asynchronous technology for the neuromorphic chip is a technical starting point of the invention.
Fig. 1 is a schematic diagram of an asynchronous edge detection circuit according to a first embodiment of the present invention, which can perform double edge detection. Comprises a first logic part I, a second logic part II, a third logic part III and a fourth logic part IV,
the first logic part I and the second logic part II are used for indicating the change condition of an input signal (A) of the asynchronous edge detection circuit and the output of the asynchronous edge detection circuit.
The first logic section I includes a first C unit 101, and two inputs of the first C unit 101 are respectively coupled to an input signal (a) of the asynchronous edge detection circuit and an inverse (| out) of an output of the asynchronous edge detection circuit, and output a first instruction.
The second logic section II includes a second C unit 102, and two inputs of the second C unit 102 respectively receive an inverse (Σa) of an input signal of the asynchronous edge detection circuit and an inverse (Σout) of an output of the asynchronous edge detection circuit, and output a second instruction.
And the third logic part III is coupled with the first logic part output and the second logic part output at the same time and is used for resetting and confirming the change condition of the first logic part output and the second logic part output.
The third logic section III includes a first multiplexer MUX103, a second multiplexer MUX104, and a third C-unit 105.
A second input of the first multiplexer MUX103 is coupled to the output of the first C-cell 101, a first input of the first multiplexer MUX103 is coupled to a logic 0, and an output of the first multiplexer MUX103 is coupled to a first input of the third C-cell 105.
A second input of the second multiplexer MUX104 is coupled to the output of the second C-cell 102, a first input of the second multiplexer MUX104 is coupled to a logic 0, an output of the second multiplexer MUX104 is coupled to a second input of the third C-cell 105, and an output of the third C-cell 105 is provided as an output of the third logic section III.
Alternatively, the asynchronous edge detection circuit of the present invention is reset by resetting the first multiplexer MUX103, the second multiplexer MUX104.
Alternatively, the first multiplexer MUX103, the second multiplexer MUX104 are reset with the inverse (| out) of the asynchronous edge detection circuit output.
The fourth logic IV is coupled to the output of the third logic III (i.e. the output of the third C-cell 105) and outputs an event (event), also called pulse event (spike), based on the indication of the third C-cell 105.
The fourth logic section IV includes a first and gate 106, a second and gate 107, and an or gate 108. The first and gate 106 logically and outputs the output of the third C cell 105 and the asynchronous edge detection circuit input signal (a), the second and gate 107 logically and outputs the output of the third C cell 105 and the inverse (| a) of the asynchronous edge detection circuit input signal, and the or gate 108 logically or outputs the outputs of the first and second and gate 106 and 107 as the output of the asynchronous edge detection circuit.
Fig. 2 is a schematic diagram of a logic relationship between input and output of a C cell (Muller C), wherein fig. 2 (a) is a schematic diagram of a C cell symbol, and fig. 2 (b) is a state diagram of the C cell.
The C cell is also a logic circuit, a state holding element/circuit in an asynchronous circuit, whose output change can indicate or confirm the change of other signals. The advantage of using a C-cell in an asynchronous circuit is that even if the input changes very quickly, it can be recorded and tracked and responded in a timely manner.
The output y of the C unit remains unchanged when the two inputs a, b are different, and the relationship between the inputs and the outputs is: y is n =ab+(a+b)y n-1 Wherein n is a positive integer, y n Representing the current state, y n－1 Representing the previous state, y 0 ＝0。
Fig. 3 is a waveform diagram of an asynchronous edge detection circuit according to a first embodiment of the present invention. For example, initially the input waveform a is low (logic 0), the asynchronous edge detection circuit is reset, its output out is low (logic 0), its output inverse | out is high (logic 1), and the second C-cell 102 outputs high (logic 1).
When the input waveform a is shifted from low to high, the first C cell 101 outputs high (logic 1), the second C cell 102 maintains the previous state (state at the time of reset), the first multiplexer MUX103 outputs high (logic 1), and the second multiplexer MUX104 outputs high (logic 1). At this time, when the third C unit 103 is shifted to the high level (logic 1), the first and gate 106 and the second and gate 107 in the fourth logic unit IV output the high level, and the output (out) of the fourth logic unit IV is shifted to the high level (logic 1). Subsequently, the first multiplexer MUX103 and the second multiplexer MUX104 are reset by the inverse (| out) of the outputs, the third C-cell 103 outputs a low level (logic 0), the output (out) of the fourth logic IV is pulled low, and a first event event_1 indicating the rising edge of the input waveform is generated.
Subsequently, when the input waveform a transitions from a high level to a low level, the first C unit 101 maintains the previous state, i.e., a high level (logic 1), and the first logic section I outputs a high level (logic 1); both inputs of the second C cell 102 are high (logic 1), the second C cell 102 outputs high (logic 1), and the second logic section II outputs high (logic 1). At this time, the third C unit 103 outputs a high level (logic 1), the first and gate 106 outputs a low level and the second and gate 107 outputs a high level in the fourth logic section IV, and thereby the output (out) of the fourth logic section IV is pulled high (logic 1). Subsequently, the first multiplexer MUX103 and the second multiplexer MUX104 are reset with the inverse (| out) of the outputs, the third C-unit 103 outputs a low level (logic 0), the output (out) of the fourth logic IV is pulled low, and a second event event_2 indicating the rising edge of the input waveform is generated.
By analogy, the asynchronous edge detection circuit can accurately indicate or confirm the change of the input waveform.
Fig. 4 is a schematic diagram of an asynchronous edge detection circuit for rising edge detection according to a second embodiment of the present invention. The difference from the circuit of fig. 1 is that in the fourth logic section IV, the first and gate 106 logically and outputs the output of the third C cell 105 and the asynchronous edge detection circuit input signal (a) as the output of the asynchronous edge detection circuit.
Fig. 5 is a waveform diagram of an asynchronous edge detection circuit according to a second embodiment of the present invention.
For example, initially the input waveform a is low (logic 0), the asynchronous edge detection circuit is reset, its output out is low (logic 0), its output inverse | out is high (logic 1), and the second C-cell 102 outputs high (logic 1).
When the input waveform a is shifted from low to high, the first C cell 101 outputs high (logic 1), the second C cell 102 maintains the previous state (state at the time of reset), the first multiplexer MUX103 outputs high (logic 1), and the second multiplexer MUX104 outputs high (logic 1). At this time, the third C unit 103 is shifted to the high level (logic 1), and the first and gate 106 in the fourth logic section IV outputs the high level, whereby the output (out) of the fourth logic section IV is shifted to the high level (logic 1). Subsequently, the first multiplexer MUX103 and the second multiplexer MUX104 are reset with the inverse (| out) of the outputs, the output (out) of the fourth logic IV is pulled low, generating a first event event_1 indicating the rising edge of the input waveform.
When the input waveform a is shifted from high to low, the first and gate 106 in the fourth logic IV inevitably outputs low, and thus, the output (out) of the fourth logic IV inevitably maintains low, thereby realizing rising edge detection.
Fig. 6 is a schematic diagram of an asynchronous edge detection circuit for falling edge detection according to a third embodiment of the present invention. The difference from the circuit of fig. 1 is that the fourth logic section IV includes only the second and gate 107, the second and gate 107 logically and outputs the output of the third C cell 105 and the inverse (| a) of the input signal of the asynchronous edge detection circuit, and the output of the second and gate 107 is the output of the asynchronous edge detection circuit.
Fig. 7 is a waveform diagram of an asynchronous edge detection circuit according to a third embodiment of the present invention, in which an event is triggered when an input signal of the asynchronous edge detection circuit transitions from a high level to a low level.
Fig. 8 is an asynchronous edge detection circuit according to a fourth embodiment of the present invention, which performs double edge detection, and is different from the circuit of fig. 1 in the manner of coupling the blocks in the fourth logic IV. In this type of embodiment, the asynchronous edge detection circuit interacts with the post-stage module, the fourth logic IV has two outputs, out_p indicating that the input a has a rising edge and out __ n indicating a falling edge, respectively, and the outputs of the fourth logic IV can be used as the request signals req_p and req_n of the post-stage circuit. Meanwhile, the first multiplexer MUX103 and the second multiplexer MUX104 are reset based on the acknowledgement signals ack_p and ack_n returned from the subsequent circuit.
Optionally, the outputs out_p and out_n of the asynchronous edge detection circuit are output to the same post-stage circuit. Alternatively, the outputs out_p and out_n of the asynchronous edge detection circuit are respectively output to different post-stage circuits.
Optionally, the acknowledgement signals ack_p and ack_n are from the same post-stage circuit and are mutually inverted. Optionally, the acknowledgement signals ack_p and ack_n are respectively from different subsequent-stage circuits.
Alternatively, ack_p and ack_n are active high, but the invention is not limited in this regard.
Fig. 9 is an exemplary waveform diagram of an asynchronous edge detection circuit of a fourth embodiment of the present invention. Illustratively, the asynchronous edge detection circuit is reset and the output out_p is low (logic 0) and the second C-cell 102 outputs high (logic 1).
When the input waveform a is shifted from low to high, the first logic section I outputs high (logic 1), the second logic section II outputs high (logic 1), and the third logic section III outputs high (logic 1). At this time, the output out_p of the first and gate 106 in the fourth logic section IV is pulled high. Until the subsequent stage generates a valid ack_p signal, the first multiplexer MUX103 and the second multiplexer MUX104 are reset such that the output out_p of the fourth logic IV is pulled low, generating an event indicating the rising edge of the input waveform.
When the input waveform a is changed from high level to low level, the output of the first logic section I maintains high level (logic 1), the second logic section II outputs high level (logic 1), and the third logic section III outputs high level (logic 1). At this time, the output out_n of the second and gate 107 in the fourth logic section IV is pulled high. Until the subsequent stage generates a valid ack_n signal, the first multiplexer MUX103 and the second multiplexer MUX104 are reset such that the output out_n of the fourth logic IV is pulled low, generating an event indicating the falling edge of the input waveform.
Fig. 10 is a schematic diagram of an asynchronous edge detection circuit for rising edge detection according to a fifth embodiment of the present invention. The difference from the circuit of fig. 9 is that the fourth logic IV includes only the first and gate 106, and the first and gate 106 logically and outputs out_p after the output of the third C cell 105 and the asynchronous edge detection circuit input signal (a), generating an event indicating a rising edge.
Fig. 11 is a schematic diagram of an asynchronous edge detection circuit for performing falling edge detection according to a sixth embodiment of the present invention. The difference from the circuit of fig. 9 is that the fourth logic section IV includes only the second and gate 107, and the second and gate 107 logically and outputs out_n after the output of the third C cell 105 and the inverse (| a) of the input signal of the asynchronous edge detection circuit, generating an event indicating a falling edge.
Optionally, in any of the foregoing embodiments, the third logic section III includes the third and gate 110, and the original third C unit 105 is replaced by the third and gate 110, which has the advantage that, compared with using the C unit, the first multiplexer MUX103 and the second multiplexer MUX104 are not reset by additionally using the inverse of the output (| out), so that the circuit logic is simplified. In addition, the area and the power consumption of the AND gate are lower than those of the C unit, the response speed is higher, and the cost and the power consumption are saved.
Optionally, in any of the foregoing embodiments, after the output out or the inverse | out of the output of the asynchronous edge detection circuit is delayed by at least one buffer unit or delay unit, the first multiplexer MUX103 and the second multiplexer MUX104 are reset to adjust the width of the event to adapt to the requirement of the post-stage circuit.
Optionally, the third AND gate 110 is a tri-state AND gate, whereby either the third AND gate 110 or both multiplexers may be selectively reset.
Fig. 12 is a schematic diagram of an asynchronous edge detection circuit according to a seventh embodiment of the present invention, which can perform rising edge detection and/or falling edge detection. Unlike any of the alternative embodiments described above, the third logic section III comprises a fourth and gate 111, which is a tri-state and gate.
When the third logic unit III confirms the change condition of the output of the first logic unit I and the output of the second logic unit II by using the tri-state gate 111 only, the first multiplexer MUX103 and the second multiplexer MUX104 in the first logic unit I and the second logic unit II may be omitted, that is, two input terminals of the tri-state and gate 111 are respectively coupled to the output of the first logic unit I and the output of the second logic unit II, and the output of the tri-state and gate 111 is the output of the third logic unit. Compared with the previous embodiment, the circuit logic of the embodiment is simplified and the response speed is faster.
Alternatively, the tri-state AND gate 111 is reset with the inverse (| out) of the output.
Fig. 13 is a schematic diagram of an asynchronous edge detection circuit according to an eighth embodiment of the present invention, in which (a) of fig. 13 is used for rising edge detection and (b) of fig. 13 is used for falling edge detection.
Fig. 14 is a schematic diagram of an asynchronous edge detection circuit according to a ninth embodiment of the present invention, which interacts with a subsequent stage of the circuit while performing rising edge or/and falling edge detection.
Fig. 15 is a schematic diagram of an asynchronous edge detection circuit according to a tenth embodiment of the present invention, in which (a) of fig. 15 is used for rising edge detection and (b) of fig. 15 is used for falling edge detection.
Optionally, in any of the foregoing embodiments, a buffer unit or a delay unit is inserted at any position in the asynchronous edge detection circuit of the present invention to meet the timing requirement.
The asynchronous edge detection circuit of the present invention may be manufactured using any process, as the invention is not limited in this regard.
The invention also relates to a slave circuit which is an asynchronous slave circuit and which uses the aforementioned asynchronous edge detection circuit to realize edge detection. The asynchronous slave circuit realizes ultra-low power consumption.
For example, the host initiates data transfer and generates a clock signal allowing the transfer, the asynchronous slave circuit of the invention detects the rising edge or/and the falling edge of the clock signal sent by the host, and an event is generated when the rising edge or/and the falling edge corresponding to the clock signal is detected.
The asynchronous slave circuit of the present invention can be used with any type of chip to reduce power consumption.
Alternatively, the chip of the present invention is a neuromorphic chip or a chip designed based on event driving.
Although the present invention has been described with reference to specific features and embodiments thereof, various modifications, combinations, substitutions can be made thereto without departing from the invention. The scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but rather, the methods and modules may be practiced in one or more products, methods, and systems of the associated, interdependent, inter-working, pre/post stages. The coupling between adjacent elements or modules of the present invention is not limited to direct connection, and any reasonable elements or modules, such as delays, buffers, inverters, etc., may be interposed therebetween, which is not limiting in the present invention.
The specification and drawings are, accordingly, to be regarded in an abbreviated manner as an introduction to some embodiments of the technical solutions defined by the appended claims and are thus to be construed in accordance with the doctrine of greatest reasonable interpretation and are intended to cover as much as possible all modifications, changes, combinations or equivalents within the scope of the disclosure of the invention while also avoiding unreasonable interpretation.
Further improvements in the technical solutions may be made by those skilled in the art on the basis of the present invention in order to achieve better technical results or for the needs of certain applications. However, even if the partial improvement/design has creative or/and progressive characteristics, the technical idea of the present invention is relied on to cover the technical features defined in the claims, and the technical scheme shall fall within the protection scope of the present invention.
The features recited in the appended claims may be presented in the form of alternative features or in the order of some of the technical processes or the sequence of organization of materials may be combined. Those skilled in the art will readily recognize that such modifications, changes, and substitutions can be made herein after with the understanding of the present invention, by changing the sequence of the process steps and the organization of the materials, and then by employing substantially the same means to solve substantially the same technical problem and achieve substantially the same technical result, and therefore such modifications, changes, and substitutions should be made herein by the equivalency of the claims even though they are specifically defined in the appended claims.
The steps and components of the embodiments have been described generally in terms of functions in the foregoing description to clearly illustrate this interchangeability of hardware and software, and in terms of various steps or modules described in connection with the embodiments disclosed herein, may be implemented in hardware, software, or a combination of both. Whether such functionality is implemented as hardware or software depends upon the particular application or design constraints imposed on the solution. Those of ordinary skill in the art may implement the described functionality using different approaches for each particular application, but such implementation is not intended to be beyond the scope of the claimed invention.

Claims (12)

1. An asynchronous edge detection circuit, characterized by:
the device comprises a first logic part, a second logic part, a third logic part and a fourth logic part;
the first logic part and the second logic part are used for generating an instruction based on the input signal of the asynchronous edge detection circuit and the change of the output of the asynchronous edge detection circuit;
the third logic part is coupled with the output of the first logic part and the output of the second logic part simultaneously and is used for resetting and confirming the indication condition of the output of the first logic part and the output of the second logic part;
the fourth logic is coupled to the output of the third logic and outputs an event.
2. The asynchronous edge detection circuit of claim 1, wherein:
the first logic part comprises a first C unit, wherein two inputs of the first C unit are respectively coupled with the inverse of an input signal of the asynchronous edge detection circuit and an output of the asynchronous edge detection circuit, and generate a first indication;
the second logic portion includes a second C cell having two inputs coupled to an inverse of the input signal of the asynchronous edge detection circuit and an inverse of the output of the asynchronous edge detection circuit, respectively, and generating a second indication.
3. The asynchronous edge detection circuit of claim 2, wherein:
the third logic part comprises a first multiplexer, a second multiplexer and a third C unit;
the second input end of the first multiplexer is coupled with the output of the first C unit, the first input end of the first multiplexer is coupled with logic 0, and the output of the first multiplexer is coupled with the first input of the third C unit;
the second input end of the second multiplexer is coupled to the output of the second C unit, the first input end of the second multiplexer is coupled to logic 0, the output of the second multiplexer is coupled to the second input of the third C unit, and the output of the third C unit serves as the output of the third logic portion.
4. An asynchronous edge detection circuit according to claim 3, wherein:
the third C unit is replaced with a third and gate.
5. The asynchronous edge detection circuit of claim 2, wherein:
the third logic portion comprises a tri-state AND gate;
the two input ends of the tri-state AND gate are respectively coupled with the outputs of the first C unit and the second C unit, and the output of the tri-state AND gate is the output of the third logic part.
6. The asynchronous edge detection circuit of any of claims 1-5, wherein:
the fourth logic part is one of the following structures:
i) The fourth logic part comprises a first AND gate, a second AND gate and an OR gate;
the first AND gate carries out logical AND on the output of the third logic part and the input signal of the asynchronous edge detection circuit and then outputs the output, and the second AND gate carries out logical AND on the output of the third logic part and the inverse of the input signal of the asynchronous edge detection circuit and then outputs the output;
the OR gate carries out logic OR post output event on the outputs of the first AND gate and the second AND gate as the output of the asynchronous edge detection circuit;
ii) the fourth logic comprises a first and gate;
the first AND gate carries out logic AND on the output of the third logic part and an input signal of the asynchronous edge detection circuit and then outputs the output as the output of the asynchronous edge detection circuit;
iii) The fourth logic portion includes a second AND gate;
the second AND gate outputs the output of the third logic part and the inverse of the input signal of the asynchronous edge detection circuit as the output of the asynchronous edge detection circuit.
7. An asynchronous edge detection circuit, characterized by:
the device comprises a first logic part, a second logic part, a third logic part and a fourth logic part;
the first logic part and the second logic part are used for indicating the change condition of an input signal of the asynchronous edge detection circuit and a confirmation signal returned to the asynchronous edge detection circuit by a later-stage circuit;
the third logic part is coupled with the output of the first logic part and the output of the second logic part simultaneously and is used for resetting and confirming the indication of the output of the first logic part and the output of the second logic part;
the fourth logic is coupled to an output of the third logic, and the fourth logic is configured to output an event indicating a rising edge or a falling edge based on an indication of the third logic.
8. The asynchronous edge detection circuit of claim 7, wherein:
the first logic part comprises a first C unit, and the second logic part comprises a second C unit; the back-end circuit is coupled to the first input end of the first C unit and the first input end of the second C unit in a reverse-simultaneous manner of a confirmation signal returned to the asynchronous edge detection circuit;
the second input end of the first C unit is coupled with the input signal of the asynchronous edge detection circuit and generates a first indication; the second input terminal of the second C unit is coupled to the input signal of the asynchronous edge detection circuit and generates a second indication.
9. The asynchronous edge detection circuit of claim 8, wherein:
the third logic part comprises a first multiplexer, a second multiplexer and a third C unit;
the second input end of the first multiplexer is coupled with the output of the first C unit, the first input end of the first multiplexer is coupled with logic 0, and the output of the first multiplexer is coupled with the first input of the third C unit;
the second input end of the second multiplexer is coupled to the output of the second C unit, the first input end of the second multiplexer is coupled to logic 0, the output of the second multiplexer is coupled to the second input of the third C unit, and the output of the third C unit serves as the output of the third logic portion.
10. The asynchronous edge detection circuit according to any of claims 7-9, wherein:
the fourth logic part is one of the following structures:
i) The fourth logic part comprises a first AND gate and a second AND gate;
the first AND gate carries out logic AND on the output of the third logic part and an input signal of the asynchronous edge detection circuit and then outputs the logic AND so as to indicate a rising edge event;
the second AND gate carries out logical AND on the output of the third logic part and the inverse of the input signal of the asynchronous edge detection circuit to output the output so as to indicate a falling edge event;
the confirmation signals returned to the asynchronous edge detection circuit by the back-stage circuit comprise a rising edge event confirmation signal and a falling edge event confirmation signal;
outputting one of a rising edge event confirm signal and a falling edge event confirm signal by using OR gate selection as a confirm signal returned to the asynchronous edge detection circuit by the post-stage circuit;
ii) the fourth logic comprises a first and gate;
the first AND gate carries out logic AND on the output of the third logic part and an input signal of the asynchronous edge detection circuit and then outputs the logic AND so as to indicate a rising edge event;
the confirmation signal returned to the asynchronous edge detection circuit by the later-stage circuit is a rising edge event confirmation signal;
iii) The fourth logic portion includes a second AND gate;
the second AND gate carries out logic AND on the output of the third logic part and an input signal of the asynchronous edge detection circuit and then outputs the logic AND so as to indicate a falling edge event;
the confirmation signal returned by the back-end circuit to the asynchronous edge detection circuit is a falling edge event confirmation signal.
11. A slave circuit, characterized in that:
the slave circuit is an asynchronous slave circuit;
the slave circuit implements edge detection using the asynchronous edge detection circuit of any one of claims 1 to 10.
12. A chip, characterized in that:
the chip comprising the slave circuit of claim 11.
CN202310862286.3A 2023-07-14 2023-07-14 Asynchronous edge detection circuit, slave circuit and chip Active CN116582113B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116866445A (en) * 2023-08-31 2023-10-10 深圳时识科技有限公司 Conversion device, chip and electronic equipment between four-phase double-track and two-phase double-track protocols
CN116886786A (en) * 2023-09-05 2023-10-13 深圳时识科技有限公司 Conversion device, chip and electronic equipment between two-phase binding and four-phase double-track protocol

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110169525A1 (en) * 2008-06-27 2011-07-14 Gennette Delaine Gill Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits
CN105806198A (en) * 2015-01-15 2016-07-27 英飞凌科技股份有限公司 Asynchronous output protocol
CN206894616U (en) * 2017-06-28 2018-01-16 湖南机电职业技术学院 A kind of FUSION WITH MULTISENSOR DETECTION logic circuit
US20200132759A1 (en) * 2018-10-30 2020-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Asynchronous circuits and test methods
CN115225082A (en) * 2022-09-20 2022-10-21 上海芯炽科技集团有限公司 Low-delay asynchronous clock frequency division circuit with edge detection
CN115622538A (en) * 2022-10-12 2023-01-17 上海泗爻微电子技术有限公司 Circuit for asynchronous data transmission

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110169525A1 (en) * 2008-06-27 2011-07-14 Gennette Delaine Gill Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits
CN105806198A (en) * 2015-01-15 2016-07-27 英飞凌科技股份有限公司 Asynchronous output protocol
CN206894616U (en) * 2017-06-28 2018-01-16 湖南机电职业技术学院 A kind of FUSION WITH MULTISENSOR DETECTION logic circuit
US20200132759A1 (en) * 2018-10-30 2020-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Asynchronous circuits and test methods
CN115225082A (en) * 2022-09-20 2022-10-21 上海芯炽科技集团有限公司 Low-delay asynchronous clock frequency division circuit with edge detection
CN115622538A (en) * 2022-10-12 2023-01-17 上海泗爻微电子技术有限公司 Circuit for asynchronous data transmission

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116866445A (en) * 2023-08-31 2023-10-10 深圳时识科技有限公司 Conversion device, chip and electronic equipment between four-phase double-track and two-phase double-track protocols
CN116866445B (en) * 2023-08-31 2023-11-21 深圳时识科技有限公司 Conversion device, chip and electronic equipment between four-phase double-track and two-phase double-track protocols
CN116886786A (en) * 2023-09-05 2023-10-13 深圳时识科技有限公司 Conversion device, chip and electronic equipment between two-phase binding and four-phase double-track protocol
CN116886786B (en) * 2023-09-05 2023-11-21 深圳时识科技有限公司 Conversion device, chip and electronic equipment between two-phase binding and four-phase double-track protocol

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