CN115622538A - Circuit for asynchronous data transmission - Google Patents
Circuit for asynchronous data transmission Download PDFInfo
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- CN115622538A CN115622538A CN202211250963.8A CN202211250963A CN115622538A CN 115622538 A CN115622538 A CN 115622538A CN 202211250963 A CN202211250963 A CN 202211250963A CN 115622538 A CN115622538 A CN 115622538A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
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Abstract
The application provides a circuit of asynchronous data transmission, includes: a data input terminal for inputting data; a first clock domain circuit comprising a first clock, an OR gate, a first flip-flop, and a first edge detection circuit; the second clock domain circuit comprises a second clock, a second trigger, a third trigger, a fourth trigger and a second edge detection circuit; and the data output end is used for receiving the data output by the second edge detection circuit of the second clock domain circuit. The asynchronous data transmission circuit can effectively prevent metastable state and can also effectively prevent over-sampling and missing sampling.
Description
Technical Field
The present application relates to the field of integrated circuit technology, and more particularly, to a circuit for asynchronous data transmission.
Background
In a digital integrated circuit design, because the setup time or the hold time of a flip-flop is not satisfied, the flip-flop enters a metastable state, so that the output of the unit cannot be predicted, and the instability is propagated in cascade along each flip-flop of a signal path, so that the circuit fails. When signals are transferred from two different clock domains, metastability is more likely to result due to the uncertain timing relationship between the incoherent clocks. In addition, when the effective width of the pulse signal output from the fast clock domain is smaller than the slow clock period, the slow clock domain directly collects the narrow pulse signal, and signal transmission is missed. Conversely, the direct acquisition of the wide pulse signal from the fast clock domain by the fast clock domain may result in repeated data fetches. Therefore, data transfer between different clock domains needs to be synchronized.
Disclosure of Invention
The application aims to provide an asynchronous data transmission circuit to solve the problems of data transmission of clock domain crossing, data over-sampling, data missing, data metastable state crossing and the like in the asynchronous data transmission circuit in the prior art.
In order to solve the above technical problem, the present application provides a circuit for asynchronous data transmission, including:
a data input terminal for inputting data;
a first clock domain circuit including a first clock, an or gate, a first flip-flop, and a first edge detection circuit, wherein the first edge detection circuit captures an edge of a pulse signal when the edge of the pulse signal occurs and generates another pulse signal and outputs the other pulse signal to the or gate; two input ends of the OR gate are respectively connected with the data input end and the output end of the first edge detection circuit, and the output end of the OR gate is connected with the input end of the first trigger; the same-direction output end of the first trigger is connected with the first input end of the first edge detection circuit; the first clock is connected with the trigger end of the first trigger;
the second clock domain circuit comprises a second clock, a second trigger, a third trigger, a fourth trigger and a second edge detection circuit, wherein the input end of the second trigger is connected with the same-direction output end of the first trigger, and the same-direction output end of the second trigger is simultaneously connected with the second input end of the first edge detection circuit and the input end of the third trigger; the same-direction output end of the third trigger is connected with the input end of the fourth trigger, and the same-direction output end of the fourth trigger and the same-direction output end of the third trigger are respectively connected with the input end of the second edge detection circuit; the second edge detection circuit is used for capturing the edge of the pulse signal when the edge of the pulse signal appears and generating another pulse signal and outputting the other pulse signal to the data output end; the second clock is simultaneously connected with the triggering ends of the second trigger, the third trigger and the fourth trigger;
and the data output end is used for receiving the data output by the second edge detection circuit of the second clock domain circuit.
In the embodiment of the present application, the pulse frequencies of the first clock and the second clock are different.
In the embodiment of the application, the circuit further comprises a reset signal which is simultaneously connected with reset ends of the first flip-flop, the second flip-flop, the third flip-flop and the fourth flip-flop.
In the embodiment of the present application, the input data is a random high-level or low-level signal.
In the embodiment of the present application, the first edge detection circuit is composed of an inverter and a first and gate, wherein a signal at a second input terminal of the first edge detection circuit is connected to the first and gate after passing through the inverter.
In this embodiment of the application, the second edge detection circuit is composed of a second and gate and an inverting circuit, wherein a signal from the equidirectional output end of the fourth flip-flop is connected to the second and gate after passing through the inverting circuit.
In the embodiment of the present application, the first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop are D flip-flops.
The technical scheme of this application has following beneficial effect:
1. the circuit structure related by the application is completely composed of a digital circuit, can be conveniently realized in a Field Programmable Gate Array (FPGA) and an Application Specific Integrated Circuit (ASIC), and does not need special process conditions.
2. The circuit structure is simple, the frequency range from the first clock to the second clock does not need to be limited specifically, and the frequency of the first clock is different from that of the second clock.
3. The circuit can effectively prevent the metastable state and can also effectively prevent the over-sampling and the missing sampling.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
fig. 1 is a schematic circuit diagram according to an embodiment of the present disclosure;
FIG. 2 is a diagram illustrating a slow clock to fast clock synchronization waveform according to an embodiment of the present application;
fig. 3 is a diagram illustrating synchronization waveforms from a fast clock to a slow clock according to an embodiment of the present application.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.
It should be understood that "system" and "device" as used herein is a method for distinguishing between different components, elements, parts, portions or assemblies of different levels. However, other words may be substituted by other expressions if they accomplish the same purpose.
As used in this application and in the claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to include the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
The terminology used in the present application is for the purpose of describing particular example embodiments only and is not intended to be limiting. For example, as used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," and/or "including," when used in this specification, are intended to specify the presence of stated integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. When it is described in the specification that different components are related, a direct relationship or an indirect relationship may be used. For example, "A is on B" means that A is directly adjacent to (above or below) B, or alternatively, A is indirectly adjacent to B (i.e., A and B are separated by some material); "A is within B" means that A is either entirely within B or partially within B; the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through other components.
These and other features disclosed herein, as well as the operation and function of the related elements of structure and the combination of parts and economies of manufacture, may be significantly improved upon consideration of the following description. All of which form a part of the disclosure of this specification, with reference to the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the present disclosure. Flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, the various steps may be processed in reverse order or simultaneously. Meanwhile, other operations may be added to or removed from these processes.
The following description is presented to enable one of ordinary skill in the art to make and use the present disclosure. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present application will be described in detail below with reference to the embodiments and the accompanying drawings.
Fig. 1 is a schematic structural diagram of a circuit for asynchronous data transmission according to an embodiment of the present application. As shown in fig. 1, the circuit comprises a data input 10, a first clock domain circuit 20, a second clock domain circuit 30 and a data output 40.
In the embodiment of the present application, the data input terminal 10 is used for inputting data, for example, digital circuit data, such as data including a high level (digital "1") and a low level (digital "0"). The input data is a random high level or low level signal.
In the embodiment of the present application, the first clock domain circuit 20 includes a first clock 201, an or gate 202, a first flip-flop 203, and a first edge detection circuit 204.
In the embodiment of the present application, the data input terminal 10 is connected to a first data input terminal of the or gate 202.
In this embodiment, the first clock 201 is connected to a trigger end of the first flip-flop 203, and the first flip-flop 203 is, for example, a D flip-flop, and stores a value of an input end into a trigger edge of the first flip-flop when the trigger edge of the first flip-flop arrives. The jump of D between two valid pulse edges does not affect the value stored by the flip-flop, but the input D must have enough settling time before the pulse edge arrives to ensure the signal is stable.
The same-direction output (Q) of the first flip-flop is connected to both the first input of the first edge detection circuit 204 and the input (D) of the second flip-flop 301. The non-inverting output (Q) of the second flip-flop 301 is simultaneously connected to the input (D) of the third flip-flop 302 and to the second input of the first edge detection circuit 204. That is, the equidirectional output terminal (Q) of the first flip-flop and the equidirectional output terminal (Q) of the second flip-flop are respectively connected to the first input terminal and the second input terminal of the first edge detection circuit 204, the output terminal of the first edge detection circuit 204 is simultaneously connected to the two data input terminals of the or gate 202 together with the data input terminal 10 (from another perspective, the two input terminals of the or gate 202 are respectively connected to the data input terminal 10 and the output terminal of the first edge detection circuit 204), and the output terminal of the or gate 202 is further connected to the input terminal (D) of the first flip-flop 203.
In this embodiment, the first edge detection circuit 204 is configured to capture an edge of a pulse signal when the edge of the pulse signal occurs and generate another pulse signal to be output to the or gate 202; the number of the generated another pulse signal is the same as the number of the pulse signal edges captured by the another pulse signal, and if the captured pulse signal edges are from the slow clock to the fast clock, the another pulse signal generated by the another pulse signal is a narrow positive pulse, and the width of the narrow positive pulse is the width of the fast clock; if the captured pulse signal edge is from the fast clock to the slow clock, it generates another pulse signal that is a wide positive pulse whose width is the width of the slow clock.
Through the or gate 202, an input signal with a high level exists, that is, the input signal is output as a high level signal, for example, a high level signal and a low level signal are output as a high level signal after passing through the or gate 202.
In this embodiment, the first edge detection circuit 204 is composed of an not gate and a first and gate, wherein a signal at the second input terminal of the first edge detection circuit 204 passes through the not gate and then is connected to the first and gate. The second input end is the end connected with the same-direction output end (Q) of the second trigger.
In the embodiment of the present application, the second clock domain circuit 30 includes a second clock 305, a second flip-flop 301, a third flip-flop 302, a fourth flip-flop 303, and a second edge detection circuit 304.
Referring to fig. 1, an input terminal (D) of the second flip-flop 301 is connected to a unidirectional output terminal (Q) of the first flip-flop 203, and the unidirectional output terminal (Q) of the second flip-flop 301 is simultaneously connected to a second input terminal of the first edge detection circuit 201 and an input terminal (D) of the third flip-flop 302; the same-direction output end (Q) of the third flip-flop 302 is connected to the input end (D) of the fourth flip-flop 303, and the same-direction output end (Q) of the fourth flip-flop 303 and the same-direction output end (Q) of the third flip-flop 302 are respectively connected to the input end of the second edge detection circuit 304. That is, a first input terminal of the second edge detection circuit 304 is connected to the same-direction output terminal (Q) of the fourth flip-flop 303, and a second input terminal of the second edge detection circuit 304 is connected to the same-direction output terminal (Q) of the third flip-flop 302.
In the embodiment of the present application, the second flip-flop 301, the third flip-flop 302, and the fourth flip-flop 303 are D flip-flops, respectively. The second clock 305 is connected to the trigger terminals of the second flip-flop 301, the third flip-flop 302 and the fourth flip-flop 303 at the same time.
In this embodiment, the pulse frequencies of the first clock 201 and the second clock 305 are different, for example, when the first clock 201 is a slow clock, the second clock 305 is a fast clock, and when the first clock 201 is a fast clock, the second clock 305 is a slow clock.
In the embodiment of the present application, the second edge detection circuit 304 is configured to capture an edge of a pulse signal when the edge of the pulse signal occurs and generate another pulse signal and output the other pulse signal to the data output terminal.
In this embodiment, the number of the other pulse signals generated by the second edge detection circuit 304 is the same as the number of the captured pulse signal edges, and if the captured pulse signal edges are from the slow clock to the fast clock, the other pulse signals generated by the second edge detection circuit are narrow positive pulses, and the width of the narrow positive pulses is the width of the fast clock; if the captured edge of the pulse signal is from the fast clock to the slow clock, it generates another pulse signal that is a wide positive pulse whose width is the width of the slow clock.
In this embodiment, the second edge detection circuit 304 is composed of an and gate and an inverting circuit, wherein a signal from the equidirectional output end (Q) of the fourth flip-flop 303 is connected to the second and gate after passing through the inverting circuit, that is, a signal at the first input end of the second edge detection circuit 304 is connected to the second and gate after passing through the inverting circuit.
The circuit according to this embodiment of the application further comprises a data output 40 for receiving data output by the second edge detection circuit of the second clock domain circuit.
The data output from the data output 40 effectively detects the change in the asynchronous input signal.
In the embodiment of the application, the circuit further comprises a reset signal which is simultaneously connected with reset ends of the first flip-flop, the second flip-flop, the third flip-flop and the fourth flip-flop. The first flip-flop, the second flip-flop, the third flip-flop and the fourth flip-flop all comprise inverted output ends
Referring to fig. 2 and fig. 3 described in this embodiment, a schematic diagram of a synchronous waveform from a slow clock to a fast clock in the embodiment of the present application and a schematic diagram of a synchronous waveform from a fast clock to a slow clock in the embodiment of the present application are shown respectively, and it can be seen from the drawings that data transferred in two asynchronous clock domains are effectively transferred, and no matter the data is transferred from the fast clock domain to the slow clock domain or from the slow clock domain to the fast clock domain, no loss or over sampling occurs.
The embodiment of the application discloses a circuit for asynchronous data transmission, which can perform reliable data synchronization for data of different clock domains. The circuit structure related to the embodiment of the application is completely composed of a digital circuit, can be conveniently realized in an FPGA and an application-specific integrated circuit, and does not need special process conditions. The circuit has no limit on the clock frequency from two clock domains, and can effectively avoid errors such as data loss, repeated sampling, metastable state and the like in asynchronous data transmission.
In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
It should be understood that the term "and/or" as used in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Claims (7)
1. A circuit for asynchronous data transmission, comprising:
a data input terminal for inputting data;
a first clock domain circuit comprising a first clock, an OR gate, a first flip-flop, and a first edge detection circuit, wherein,
the first edge detection circuit is used for capturing the edge of the pulse signal when the edge of the pulse signal appears and generating another pulse signal and outputting the pulse signal to the OR gate;
two input ends of the OR gate are respectively connected with the data input end and the output end of the first edge detection circuit, and the output end of the OR gate is connected with the input end of the first trigger;
the same-direction output end of the first trigger is connected with the first input end of the first edge detection circuit;
the first clock is connected with the trigger end of the first trigger;
a second clock domain circuit comprising a second clock, a second flip-flop, a third flip-flop, a fourth flip-flop, and a second edge detection circuit, wherein,
the input end of the second trigger is connected with the equidirectional output end of the first trigger, and the equidirectional output end of the second trigger is simultaneously connected with the second input end of the first edge detection circuit and the input end of the third trigger;
the same-direction output end of the third trigger is connected with the input end of the fourth trigger, and the same-direction output end of the fourth trigger and the same-direction output end of the third trigger are respectively connected with the input end of the second edge detection circuit;
the second edge detection circuit is used for capturing the edge of the pulse signal when the edge of the pulse signal appears and generating another pulse signal and outputting the other pulse signal to the data output end;
the second clock is simultaneously connected with the triggering ends of the second trigger, the third trigger and the fourth trigger;
and the data output end is used for receiving the data output by the second edge detection circuit of the second clock domain circuit.
2. The circuit for asynchronous data transfer of claim 1, wherein the pulse frequency of the first clock and the second clock are different.
3. The circuit of claim 1, further comprising a reset signal coupled to reset terminals of the first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop.
4. The circuit of claim 1, wherein the input data is a random high or low signal.
5. The circuit for asynchronous data transmission according to claim 1, wherein the first edge detection circuit comprises an inverter and a first and gate, and wherein a signal at the second input terminal of the first edge detection circuit passes through the inverter and then is coupled to the first and gate.
6. The circuit of claim 1, wherein the second edge detection circuit comprises a second and gate and an inverting circuit, and wherein the signal from the same-direction output terminal of the fourth flip-flop is coupled to the second and gate after passing through the inverting circuit.
7. The circuit for asynchronous data transfer of claim 1, wherein the first flip-flop, second flip-flop, third flip-flop, and fourth flip-flop are D flip-flops.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211250963.8A CN115622538A (en) | 2022-10-12 | 2022-10-12 | Circuit for asynchronous data transmission |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211250963.8A CN115622538A (en) | 2022-10-12 | 2022-10-12 | Circuit for asynchronous data transmission |
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| CN115622538A true CN115622538A (en) | 2023-01-17 |
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| CN202211250963.8A Pending CN115622538A (en) | 2022-10-12 | 2022-10-12 | Circuit for asynchronous data transmission |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116582113A (en) * | 2023-07-14 | 2023-08-11 | 深圳时识科技有限公司 | Asynchronous edge detection circuit, slave circuit and chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116582113A (en) * | 2023-07-14 | 2023-08-11 | 深圳时识科技有限公司 | Asynchronous edge detection circuit, slave circuit and chip |
| CN116582113B (en) * | 2023-07-14 | 2024-02-06 | 深圳时识科技有限公司 | Asynchronous edge detection circuit, slave circuit and chip |
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