CN206894616U - A kind of FUSION WITH MULTISENSOR DETECTION logic circuit - Google Patents
A kind of FUSION WITH MULTISENSOR DETECTION logic circuit Download PDFInfo
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- CN206894616U CN206894616U CN201720765533.8U CN201720765533U CN206894616U CN 206894616 U CN206894616 U CN 206894616U CN 201720765533 U CN201720765533 U CN 201720765533U CN 206894616 U CN206894616 U CN 206894616U
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Abstract
A kind of FUSION WITH MULTISENSOR DETECTION logic circuit, including multiple sensors, d type flip flop and application of logic circuit module, the d type flip flop and the quantity of application of logic circuit module and the quantity of sensor are identical so that each sensor corresponds to a d type flip flop and application of logic circuit module；Application of logic circuit module includes I2 ends, I1 ends and these three ports of I0 ends；The C-terminal connection system clock of the d type flip flop, the D ends of d type flip flop connect the I2 ends of corresponding sensor and application of logic circuit module, the I1 ends of the Q ends connection application of logic circuit module of d type flip flop；The I0 ends connecting valve of application of logic circuit module.Electronic component needed for the utility model circuit is few；User can set respective sensor to trigger type according to different sensors by switching, and increase the application of circuit；Sensor voltage input range is wider；Logic circuit processing speed is very fast, can be changed with fast response transducer, and delay is less.
Description
Technical field
Detection circuit field is the utility model is related to, particularly a kind of FUSION WITH MULTISENSOR DETECTION logic circuit.
Background technology
Existing sensor detection circuit causes user by switching rising edge detection or trailing edge can not be set to detect, and is needing
When detecting multiple sensor signals simultaneously, traditional detection circuit does not adapt to the demand of multisensor while detection, for existing
There is the shortcomings that sensor detection circuit, propose that FUSION WITH MULTISENSOR DETECTION logic circuit makes up the deficiency of available circuit.
Utility model content
The purpose of this utility model is to overcome the above-mentioned deficiency of prior art and provide a kind of applied widely, versatility
By force, the much faster sensor detection logic circuit of processing speed.
The technical solution of the utility model is：A kind of FUSION WITH MULTISENSOR DETECTION logic circuit, including multiple sensors, D triggering
Device and application of logic circuit module, the d type flip flop and the quantity of application of logic circuit module and the quantity of sensor are identical so that Mei Gechuan
The corresponding d type flip flop of sensor and application of logic circuit module；Application of logic circuit module includes I2 ends, I1 ends and these three ports of I0 ends；
The C-terminal connection system clock of the d type flip flop, the D ends of d type flip flop connect corresponding sensor and the I2 of application of logic circuit module
End, the I1 ends of the Q ends connection application of logic circuit module of d type flip flop；The I0 ends connecting valve of application of logic circuit module；
The application of logic circuit module includes phase inverter INV1 ~ INV3 and gate cell AND1 ~ AND4 and OR gate unit OR；
The inverted device INV1 connections in I1 ends of the application of logic circuit module and gate cell AND2 first input end, application of logic circuit module
The inverted device INV2 connections in I0 ends and gate cell AND2 the second input；The I2 ends connection of application of logic circuit module and gate cell
AND4 first input end, it is connected with gate cell AND2 output end and gate cell AND4 the second input；Logic circuit mould
The I1 ends connection of block and gate cell AND1 first input end, the I0 ends connection and the second of gate cell AND1 of application of logic circuit module
Input；The inverted device INV3 connections in I2 ends of application of logic circuit module and gate cell AND3 first input end, with gate cell
AND1 output end connection and gate cell AND3 the second input；The of gate cell AND3 output end connection OR gate unit OR
One input, OR gate unit OR the second input is connected with gate cell AND4 output end, and OR gate unit OR output end is defeated
Go out signal.
Further, phase inverter INV4, phase inverter INV4 input incoming level signal are included, phase inverter INV4's is defeated
Go out the CLR ends that end connects each d type flip flop.
Further, the quantity of the sensor is 2 ~ 8.
Further, the phase inverter INV1 ~ INV3 is integrated in same chip, and phase inverter chip is TTL hex inverter cores
Piece 7404.
Further, it is integrated in gate cell AND1 ~ AND4 in same chip, is 2 inputs four and door chip with door chip
74LS08。
Further, the OR gate unit OR is 2 four OR gate chips 7432 of input.
Further, one end of the I0 ends connecting valve of the application of logic circuit module, the other end ground connection of switch.
Further, the quantity of the switch and the quantity of application of logic circuit module are identical.
The beneficial effects of the utility model：Electronic component is few needed for circuit；User can be according to different sensors by opening
Close and set respective sensor to trigger type, increase the application of circuit；Sensor voltage input range is wider；At logic circuit
Speed is managed, can be changed with fast response transducer, delay is less.
Brief description of the drawings
Fig. 1 is the structural representation of the utility model embodiment；
The structural representation of Fig. 2 Fig. 1 shown implementation application of logic circuit module.
Embodiment
The utility model is described in further details below with reference to Figure of description and specific embodiment.
A kind of FUSION WITH MULTISENSOR DETECTION logic circuit, including three sensor H1 ~ H3, d type flip flop FF1 ~ FF3, logic circuit
Module U1 ~ U3 and switch K1 ~ K3, each sensor corresponding a d type flip flop, application of logic circuit module and switch.
Each application of logic circuit module includes I2 ends, I1 ends and these three ports of I0 ends；D type flip flop FF1 ~ FF3 C-terminal is equal
System clock is connected, the D ends of d type flip flop connect the I2 ends of corresponding sensor and application of logic circuit module, the Q ends of d type flip flop
Connect the I1 ends of application of logic circuit module；One end of the I0 ends connecting valve of application of logic circuit module, the other end ground connection of switch.
Application of logic circuit module includes phase inverter INV1 ~ INV3 and gate cell AND1 ~ AND4 and OR gate unit OR；Logic
The inverted device INV1 connections in I1 ends of circuit module and gate cell AND2 first input end, the I0 ends of application of logic circuit module are through anti-
Phase device INV2 connections and gate cell AND2 the second input；The I2 ends connection and the first of gate cell AND4 of application of logic circuit module
Input, it is connected with gate cell AND2 output end and gate cell AND4 the second input；The I1 ends of application of logic circuit module connect
Connect the first input end with gate cell AND1, the I0 ends connection of application of logic circuit module and gate cell AND1 the second input；Patrol
Collect the inverted device INV3 connections in I2 ends of circuit module and gate cell AND3 first input end, the output end with gate cell AND1
Connection and gate cell AND3 the second input；Gate cell AND3 output end connection OR gate unit OR first input end, with
Gate cell AND4 output end connection OR gate unit OR the second input, OR gate unit OR output end output signal.
The present embodiment also includes phase inverter INV4, phase inverter INV4 input incoming level signal, phase inverter INV4's
Output end connects the CLR ends of each d type flip flop.
The operation principle of the present embodiment is：
（1）When phase inverter INV4 input input high level reset signal, inverted rear d type flip flop, which is in, resets shape
State so that circuit can not detect the signal of multisensor output；
（2）When phase inverter INV4 input input low level reset signal, circuit is started working, and is specially：
A.D triggers FF1 C-terminal connection system clock, d type flip flop FF1 D ends connection sensor H1 and logic circuit mould
Block U1 I2 ends, sensor H1 output signal to d type flip flop FF1 D ends, according to the principle of d type flip flop itself, d type flip flop FF1
Output pin Q ends export a upper clock sensor signal to application of logic circuit module U1 I1 ends.
Similarly, sensor H2 outputs signal to d type flip flop FF2 D ends, and d type flip flop FF2 output pin Q ends export
One clock sensor signal is to application of logic circuit module U2 I1 ends；Sensor H3 outputs signal to d type flip flop FF3 D ends, D
Trigger FF3 output pin Q ends export a upper clock sensor signal to application of logic circuit module U3 I1 ends.
B. switch K1 ~ K3 connects application of logic circuit module U1 ~ U3 I0 ends respectively, is rising edge or trailing edge selection signal.
C. application of logic circuit module U1 operation principle is：I0 ends are rising edge or trailing edge selection signal, when I0 ends are low
During level, low level is exported with gate cell AND1, low level is exported with gate cell AND3, is passed through with gate cell AND2 output I1 ends
Phase inverter INV1 signals of the inverted, only I2 ends input signal（That is sensor output signal）For high level when, and I1 ends are defeated
Enter signal（That is the previous signal of sensor output）For low level when, with gate cell AND4 export high level, now be rise
Along detection pattern；
When I0 ends are high level, low level is exported with gate cell AND2, low level is exported with gate cell AND4, with door list
The signal at first AND1 output I1 ends, pass through phase inverter INV3 signals of the inverted, only I2 ends with gate cell AND3 output I2 ends
Input signal（That is sensor output signal）For low level when, and I1 ends input signal（That is the previous signal of sensor output）
For high level when, with gate cell AND3 export high level, be now trailing edge detection pattern.
In the present embodiment, described system clock can be crystal oscillator；Described is integrated in together with gate cell AND1 ~ AND4
Preferably it is 2 input four and door chip 74LS08 with door chip in one chip；Described phase inverter INV1 ~ INV3 is integrated in same
In chip, preferably phase inverter chip is TTL hex inverters chip 7404；Described OR gate unit OR is preferably the OR gate of 2 input four
Chip 7432；Described d type flip flop FF1 ~ FF3 is integrated in same chip, and preferably d type flip flop chip triggers for four rising edge D
Device 74HC175.Because the pin annexation and principle of each chip are that the present embodiment is not according to known to the chip handbook
Remake and specifically repeat.
In summary, the present embodiment has advantages below：Electronic component is few needed for circuit；User can be according to different sensings
Device sets respective sensor to trigger type by switching, and increases the application of circuit；Sensor voltage input range is wider；Patrol
Processing of circuit speed is collected, can be changed with fast response transducer, delay is less.
Claims (8)
1. a kind of FUSION WITH MULTISENSOR DETECTION logic circuit, it is characterised in that including multiple sensors, d type flip flop and logic circuit mould
Block, the d type flip flop and the quantity of application of logic circuit module and the quantity of sensor are identical so that each corresponding D of sensor
Trigger and application of logic circuit module；Application of logic circuit module includes I2 ends, I1 ends and these three ports of I0 ends；The C of the d type flip flop
End connection system clock, the D ends of d type flip flop connect the I2 ends of corresponding sensor and application of logic circuit module, the Q of d type flip flop
The I1 ends of end connection application of logic circuit module；The I0 ends connecting valve of application of logic circuit module；
The application of logic circuit module includes phase inverter INV1 ~ INV3 and gate cell AND1 ~ AND4 and OR gate unit OR；It is described
The inverted device INV1 connections in I1 ends of application of logic circuit module and gate cell AND2 first input end, the I0 ends of application of logic circuit module
Inverted device INV2 connections and gate cell AND2 the second input；The I2 ends connection of application of logic circuit module is with gate cell AND4's
First input end, it is connected with gate cell AND2 output end and gate cell AND4 the second input；The I1 of application of logic circuit module
End connection and gate cell AND1 first input end, the I0 ends connection of application of logic circuit module and gate cell AND1 the second input
End；The inverted device INV3 connections in I2 ends of application of logic circuit module and gate cell AND3 first input end, with gate cell AND1's
Output end connects the second input with gate cell AND3；Gate cell AND3 output end connection OR gate unit OR the first input
End, OR gate unit OR the second input, OR gate unit OR output end output signal are connected with gate cell AND4 output end.
2. FUSION WITH MULTISENSOR DETECTION logic circuit according to claim 1, it is characterised in that also including phase inverter INV4, instead
Phase device INV4 input incoming level signal, phase inverter INV4 output end connect the CLR ends of each d type flip flop.
3. FUSION WITH MULTISENSOR DETECTION logic circuit according to claim 1 or 2, it is characterised in that the quantity of the sensor
For 2 ~ 8.
4. FUSION WITH MULTISENSOR DETECTION logic circuit according to claim 1 or 2, it is characterised in that the phase inverter INV1 ~
INV3 is integrated in same chip, and phase inverter chip is TTL hex inverters chip 7404.
5. FUSION WITH MULTISENSOR DETECTION logic circuit according to claim 1 or 2, it is characterised in that described and gate cell AND1 ~
AND4 is integrated in same chip, is 2 input four and door chip 74LS08 with door chip.
6. FUSION WITH MULTISENSOR DETECTION logic circuit according to claim 1 or 2, it is characterised in that the OR gate unit OR is 2
Input four OR gate chips 7432.
7. FUSION WITH MULTISENSOR DETECTION logic circuit according to claim 1 or 2, it is characterised in that the application of logic circuit module
I0 ends connecting valve one end, switch the other end ground connection.
8. FUSION WITH MULTISENSOR DETECTION logic circuit according to claim 1 or 2, it is characterised in that the quantity of the switch with
The quantity of application of logic circuit module is identical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720765533.8U CN206894616U (en) | 2017-06-28 | 2017-06-28 | A kind of FUSION WITH MULTISENSOR DETECTION logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720765533.8U CN206894616U (en) | 2017-06-28 | 2017-06-28 | A kind of FUSION WITH MULTISENSOR DETECTION logic circuit |
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| Publication Number | Publication Date |
|---|---|
| CN206894616U true CN206894616U (en) | 2018-01-16 |
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| CN201720765533.8U Expired - Fee Related CN206894616U (en) | 2017-06-28 | 2017-06-28 | A kind of FUSION WITH MULTISENSOR DETECTION logic circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110319890A (en) * | 2019-08-16 | 2019-10-11 | 南阳理工学院 | Modular sensor |
| CN116582113A (en) * | 2023-07-14 | 2023-08-11 | 深圳时识科技有限公司 | Asynchronous edge detection circuit, slave circuit and chip |
| CN117275401A (en) * | 2023-11-03 | 2023-12-22 | 中山市智牛电子有限公司 | Image reduction circuit, LED display screen control card and image scaling method |
-
2017
- 2017-06-28 CN CN201720765533.8U patent/CN206894616U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110319890A (en) * | 2019-08-16 | 2019-10-11 | 南阳理工学院 | Modular sensor |
| CN116582113A (en) * | 2023-07-14 | 2023-08-11 | 深圳时识科技有限公司 | Asynchronous edge detection circuit, slave circuit and chip |
| CN116582113B (en) * | 2023-07-14 | 2024-02-06 | 深圳时识科技有限公司 | Asynchronous edge detection circuit, slave circuit and chip |
| CN117275401A (en) * | 2023-11-03 | 2023-12-22 | 中山市智牛电子有限公司 | Image reduction circuit, LED display screen control card and image scaling method |
| CN117275401B (en) * | 2023-11-03 | 2024-02-27 | 中山市智牛电子有限公司 | Image reduction circuit, LED display screen control card and image scaling method |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180116 Termination date: 20210628 |
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| CF01 | Termination of patent right due to non-payment of annual fee |