CN202309650U - Hardware phase discriminating circuit based on FPGA (Field Programmable Gate Array) - Google Patents
Hardware phase discriminating circuit based on FPGA (Field Programmable Gate Array) Download PDFInfo
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- CN202309650U CN202309650U CN2011204586288U CN201120458628U CN202309650U CN 202309650 U CN202309650 U CN 202309650U CN 2011204586288 U CN2011204586288 U CN 2011204586288U CN 201120458628 U CN201120458628 U CN 201120458628U CN 202309650 U CN202309650 U CN 202309650U
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Abstract
The utility model relates to a hardware phase discriminating circuit based on a FPGA (Field Programmable Gate Array). The hardware phase discriminating circuit comprises two D triggers, four NAND gates and four NOT gates; and all circuit functional circuits area realized by combining logic gates inside the FPGA and can be modified through software programming, and only one path of signal including the size and direction of the phase difference of two paths of signals is output; and positive and negative directions correspond to two conditions of signal advancing and signal lagging. When two paths of signals are advanced, lagged or unfixed, the hardware phase discriminating circuit can not accurately extract the phase difference of the two signals. By adjusting the initial phase difference of the two paths of signals, the initial phase difference equals to 180 degrees, the advancing, lagging or fixation can be effectively ensured, thereby the hardware phase discriminating circuit is facilitated to accurately extract the size and direction of the phase difference of the two paths of signals. The hardware phase discriminating circuit has the advantages of simple structure, ingenious design and good stability; and the hardware phase discriminating circuit is used in an FPGA application so that the phase difference of the two signals can be rapidly and accurately discriminated.
Description
Technical field
The utility model relates to a kind of measuring technique, particularly a kind of hardware phase discriminator based on FPGA.
Background technology
At present, based on the phase discriminator of FPGA two kinds of methods are arranged generally, all adopt two-way output: a kind of is one road outbound course, one tunnel output pulse; Another kind is one tunnel output direct impulse, one tunnel output reverse impulse.The circuit design relative complex, circuit output is not enough to be simplified.
Summary of the invention
The utility model is the frequency multiplier circuit complicated problems to Photoelectric angular position transducer FPGA, has proposed a kind of hardware phase discriminator based on FPGA, and the phase difference size and Orientation of two paths of signals is exported as one road signal simultaneously, simplifies output, optimizes circuit.
The technical scheme of the utility model is: a kind of hardware phase discriminator based on FPGA; Comprise four not gates, four NAND gates and two d type flip flops; Two input signal ends are connected to input 1 pin of first not gate and input 1 pin of second not gate respectively; Output 2 pin of first not gate are connected to input 2 pin with second not gate; With output 3 pin of first not gate be connected to respectively with input 1 pin of the 3rd not gate and first d type flip flop put 1 end, 3 pin; Input 1 pin and input end of clock 2 pin of first d type flip flop are held GND with being connected to; Output 4 pin of first d type flip flop be connected to respectively the 3rd not gate input 1 pin and with input 2 pin of the 3rd not gate, put 1 end, 3 pin with output 3 pin of the 3rd not gate are connected to second d type flip flop, input 1 pin and input end of clock 2 pin of second d type flip flop are held GND with being connected to; Output 4 pin of second d type flip flop be connected to respectively the 4th not gate input 1 pin, with input 2 pin and the lead-out terminal EPD of second not gate; Output 2 pin of the 4th not gate are connected to input 1 pin with first not gate, and output 2 pin of second not gate are connected to input 1 pin with second not gate, with output 3 pin of second not gate be connected to respectively first d type flip flop clear terminal 5 pin and with input 2 pin of the 4th not gate; Be connected to output 2 pin of the 3rd not gate with input 1 pin of the 4th not gate, be connected to clear terminal 5 pin of second d type flip flop with output 3 pin of the 4th not gate.
The beneficial effect of the utility model is: the utility model is exported the phase difference size and Orientation of two paths of signals based on the hardware phase discriminator of FPGA as one road signal, simplifies output, have simple in structure, design is ingenious, the advantage of good stability.
Description of drawings
Fig. 1 is the hardware phase discriminator figure of the utility model based on FPGA.
Embodiment
As shown in Figure 1; A kind of hardware phase discriminator based on FPGA; Input signal terminal PA, PB are connected to the input 1 of not gate A1 and the input 1 of not gate A2 respectively, and the output 2 of not gate A1 is connected to the input 2 of NAND gate B1, the output 3 of NAND gate B1 be connected to respectively NAND gate B3 input 1 and d type flip flop C1 put 1 end 3; Input 1 and the input end of clock 2 of d type flip flop C1 are held GND with being connected to; The output 4 of d type flip flop C1 is connected to the input 1 of not gate A3 and the input 2 of NAND gate B3 respectively, and the output 3 of NAND gate B3 is connected to 1 end 3 of putting of d type flip flop C2, and input 1 and the input end of clock 2 of d type flip flop C2 are held GND with being connected to; The output 4 of d type flip flop C2 is connected to the input 1 of not gate A4, input 2 and the lead-out terminal EPD of NAND gate B2 respectively; The output 2 of not gate A4 is connected to the input 1 of NAND gate B1, and the output 2 of not gate A2 is connected to the input 1 of NAND gate B2, and the output 3 of NAND gate B2 is connected to the clear terminal 5 of d type flip flop C1 and the input 2 of NAND gate B4 respectively; The input 1 of NAND gate B4 is connected to the output 2 of not gate A3, and the output 3 of NAND gate B4 is connected to the clear terminal 5 of d type flip flop C2.
All circuit function unit all have the combination of FPGA internal logic door to realize, and can revise through software programming.Have only one tunnel output, wherein, both comprised the phase difference size of two paths of signals, comprise the phase difference direction again, the leading and two kinds of situation of signal lag of the positive and negative respective signal on the direction.Leading when two paths of signals, when lagging behind not fixedly, this circuit can't accurately extract the phase difference of two paths of signals.But through the first phase potential difference of adjustment two paths of signals, make it to equal 180 degree, it is fixing to guarantee effectively in advance, lag behind, thereby utilizes this phase discriminator accurately to extract the phase difference size and Orientation of two paths of signals.
Claims (1)
1. hardware phase discriminator based on FPGA; It is characterized in that; Comprise four not gates, four NAND gates and two d type flip flops; Two input signal ends are connected to input 1 pin of first not gate and input 1 pin of second not gate respectively; Output 2 pin of first not gate are connected to input 2 pin with second not gate; With output 3 pin of first not gate be connected to respectively with input 1 pin of the 3rd not gate and first d type flip flop put 1 end, 3 pin, input 1 pin and input end of clock 2 pin of first d type flip flop are held GND with being connected to, output 4 pin of first d type flip flop be connected to respectively the 3rd not gate input 1 pin and with input 2 pin of the 3rd not gate; Put 1 end, 3 pin with output 3 pin of the 3rd not gate are connected to second d type flip flop; Input 1 pin and input end of clock 2 pin of second d type flip flop are held GND with being connected to, output 4 pin of second d type flip flop be connected to respectively input 1 pin of the 4th not gate, with input 2 pin and the lead-out terminal EPD of second not gate, output 2 pin of the 4th not gate are connected to input 1 pin with first not gate; Output 2 pin of second not gate are connected to input 1 pin with second not gate; With output 3 pin of second not gate be connected to respectively first d type flip flop clear terminal 5 pin and with input 2 pin of the 4th not gate, be connected to output 2 pin of the 3rd not gate with input 1 pin of the 4th not gate, be connected to clear terminal 5 pin of second d type flip flop with output 3 pin of the 4th not gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204586288U CN202309650U (en) | 2011-11-18 | 2011-11-18 | Hardware phase discriminating circuit based on FPGA (Field Programmable Gate Array) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204586288U CN202309650U (en) | 2011-11-18 | 2011-11-18 | Hardware phase discriminating circuit based on FPGA (Field Programmable Gate Array) |
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| Publication Number | Publication Date |
|---|---|
| CN202309650U true CN202309650U (en) | 2012-07-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011204586288U Withdrawn - After Issue CN202309650U (en) | 2011-11-18 | 2011-11-18 | Hardware phase discriminating circuit based on FPGA (Field Programmable Gate Array) |
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| CN (1) | CN202309650U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102364877A (en) * | 2011-11-18 | 2012-02-29 | 中国船舶重工集团公司第七○四研究所 | Field programmable gate array (FPGA)-based hardware phase discrimination circuit |
-
2011
- 2011-11-18 CN CN2011204586288U patent/CN202309650U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102364877A (en) * | 2011-11-18 | 2012-02-29 | 中国船舶重工集团公司第七○四研究所 | Field programmable gate array (FPGA)-based hardware phase discrimination circuit |
| CN102364877B (en) * | 2011-11-18 | 2013-08-28 | 中国船舶重工集团公司第七0四研究所 | Field programmable gate array (FPGA)-based hardware phase discrimination circuit |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20120704 Effective date of abandoning: 20130828 |
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| RGAV | Abandon patent right to avoid regrant |