CN202076997U - Timing optimization circuit of burr prevention clock selector - Google Patents

Abstract

The utility model relates to a timing optimization circuit of a burr prevention clock selector. The burr prevention clock selector is provided with two clock signal input terminals, a clock selection signal control terminal, a reset signal terminal, a negation gate, and first and second conjunction gates, wherein the first conjunction gate is subsequently connected with first and second registers, the second conjunction gate is subsequently connected with third and fourth registers, output of the second register and one input clock are taken as the input terminal of a third conjunction gate, the output of the fourth register and another input clock are taken as the input terminal of a fourth conjunction gate, output terminals of the third conjunction gate and the fourth conjunction gate are taken as the input terminal of an alternation gate, and the output terminal of the alternation gate is an output clock of the burr prevention clock selector. The timing optimization circuit is characterized in that the first, the second and the third conjunction and negation gates are used for respectively replacing the third conjunction gate, the fourth conjunction gate and the alternation gate.

Description

A kind of timing optimization circuit of anti-burr clock selector

Technical field

The utility model relates to the clock switch circuit that is used for asic chip in the digital integrated circuit field, relate in particular to a kind of timing optimization circuit of anti-burr clock selector, compared to traditional anti-burr clock selector commutation circuit, the rising, fall time with clock signal be the characteristics of symmetry more.

Background technology

Along with the high speed development of SoC and asic technology, the complexity and the integrated level of design also increase substantially.Become very general of the demand of using a plurality of clocks source at same system, the dynamic handoff functionality between the clock source is more and more common, and the clock switch circuit that therefore has anti-burr function just appears in the system in a large number.Shown in Figure 1 is the anti-burr clock selector circuit of this kind tradition, and its basic structure is: input A, B are the two-way input clock, and the S end is the clock selecting control end, and the Resetn end is that the reset terminal of clock selector, output Y are the output clock of clock selector.The front constituted the selection circuit of clock selector with door and two-stage register, the two-stage gate circuit of back has constituted the selection and the gating circuit of two-way clock.Its basic principle for when clock from one tunnel clock that switches to another road, select signal synchronous, the burr when so just effectively having eliminated the clock switching through the two-stage of clock signal.

Summary of the invention

The purpose of this utility model is to carry out structural optimization at traditional anti-burr clock selector, a kind of timing optimization circuit of anti-burr clock selector is provided, its technical scheme is: a kind of timing optimization circuit of anti-burr clock selector, anti-burr clock selector is provided with the two-way clock signal input terminal, the clock selection signal control end, the reset signal end, not gate and first, the second two with door, first is connected first with continuous behind the door, the second two-stage register, second is connected the 3rd with continuous behind the door, the 4th two-stage register, wherein, the output of second register and one road input clock as the 3rd with the door input, the output of the 4th register and another road input clock as the 4th with the door input, the 3rd with the door and the 4th with the door output as one or input, or the output of door is the output clock of anti-burr clock selector, it is characterized in that: with first, second, the 33 NAND gate replace respectively the 3rd with door, the 4th with door and or door, it is as follows that circuit connects:

One road input clock connects the input end of clock of first, second register and an input of first NAND gate respectively, the output of first register links to each other with the data input pin of second register, and the output of second register connects another input of first NAND gate; Another road input clock connects the input end of clock of the 3rd, the 4th register and an input of second NAND gate respectively, the output of the 3rd register links to each other with the data input pin of the 4th register, and the output of the 4th register connects another input of second NAND gate; Clock selection signal connects the not gate input, non-gate output terminal connect first with an input of door, first is connected the non-end of output of the 4th register with another input of door, first with output be connected the data input pin of first register; Clock selection signal also connects an input of second NAND gate, and another input of second NAND gate connects the non-end of output of second register; Reset signal connects the clear terminal that resets of first, second, third, fourth register respectively; The output of first, second NAND gate is as the input of the 3rd NAND gate, and the output of the 3rd NAND gate is the output clock of anti-burr clock selector.

Advantage of the present utility model and remarkable result: the utility model is by preventing the structural modification of burr clock switch circuit to tradition, realization makes the rise and fall time optimization of symmetry more of clock signal, in the system that clock rising edge and trailing edge are sampled simultaneously, can effectively improve system frequency when needed.The utility model has just carried out revising at the selection of the two-way clock of the anti-burr clock selector back of tradition and gating circuit structure to be replaced, and changes structure that two NAND gate as back level NAND gate import with door as the structure of back level or door input with two.According to the basic principle of Digital Logic, logical relation does not change before and after improving.

Description of drawings

Fig. 1 is the anti-burr clock selector circuit structure diagram of tradition;

Fig. 2 is the anti-burr clock selector circuit structure diagram of the utility model;

Fig. 3 is the last two-stage gate structure of tradition before improving;

Fig. 4 is the last two-stage gate structure after the utility model improves;

Fig. 5 is the register connection diagram that has positive negative edge sampling simultaneously.

Embodiment

Circuit structure after the utility model improves as shown in Figure 2, input clock A is connected in the input end of clock (CK end) of register 1,2, the output Q of register 1 links to each other with the data input pin D of register 2, and clock signal is selected the output non-end of S through not gate and register 2

With, link the data input pin D of register 1.Input clock B is connected in the input end of clock (CK end) of register 3,4, and the output Q of register 3 links to each other with the data input pin D of register 4, and clock signal is selected the non-end of output of S and register 4

With, link the data input pin D of register 3.The output Q of input clock A and register 2 does NOT-AND operation, constitutes signal J, and the output Q end of input clock B and register 4 is done NOT-AND operation, constitutes signal K.J, K obtain exporting clock Y through a NAND gate again.Reset signal Resetn links the reset terminal (CLR end) of register 1,2,3,4.

Because gap is all arranged the rise time of gate circuit and fall time, in the traditional structure before improvement, all be positive logic by the two-stage gate circuit, all be identical logic before and after its two-stage gate circuit.As shown in Figure 3, A1, B1 are identical with the logic of C (or A2, B2 and C).

In the utility model structure after improvement, when one road gating, through the two-stage inverter structure, promptly logic is identical before and after the two-stage NAND gate structure in clock signal for circuit equivalent, and two-stage NAND gate intermediate logic is opposite.As shown in Figure 4, A1 is identical with the C logic, it is opposite with the B1 logic that (or A2 is identical with the C logic, opposite with the B2 logic), like this from A1 hold rise time of rise time of C end (or hold C end from A2) and fall time all being a NAND gate and fall time sum, can well guarantee clock signal rise time and fall time coupling.

Need in the system of rising edge clock sampling and clock trailing edge sampling appearance simultaneously at some, not matching the rise time of clock signal and fall time to become the bottleneck of speed.As Fig. 5, register 1 and register 3 are the rising edge clock sample register, and register 2 is a clock trailing edge sample register.Clock signal differs one-period when A, C two point samplings, during the B point sampling and 2 phase difference of half cycles of A, C, when the clock rise and fall time is unmatched, can cause the time-delay allowance that the B point is ordered to C to diminish restriction system speed.So the utility model is used the system of rising edge clock sampling and trailing edge sampling at the same time, can improve the system works frequency.

Claims (1)

1. the timing optimization circuit of an anti-burr clock selector, anti-burr clock selector is provided with the two-way clock signal input terminal, the clock selection signal control end, the reset signal end, not gate and first, the second two with door, first is connected first with continuous behind the door, the second two-stage register, second is connected the 3rd with continuous behind the door, the 4th two-stage register, wherein, the output of second register and one road input clock as the 3rd with the door input, the output of the 4th register and another road input clock as the 4th with the door input, the 3rd with the door and the 4th with the door output as one or input, or the output of door is the output clock of anti-burr clock selector, it is characterized in that: with first, second, the 33 NAND gate replace respectively the 3rd with door, the 4th with door and or door, it is as follows that circuit connects:

One road input clock connects the input end of clock of first, second register and an input of first NAND gate respectively, the output of first register links to each other with the data input pin of second register, and the output of second register connects another input of first NAND gate; Another road input clock connects the input end of clock of the 3rd, the 4th register and an input of second NAND gate respectively, the output of the 3rd register links to each other with the data input pin of the 4th register, and the output of the 4th register connects another input of second NAND gate; Clock selection signal connects the not gate input, non-gate output terminal connect first with an input of door, first is connected the non-end of output of the 4th register with another input of door, first with output be connected the data input pin of first register; Clock selection signal also connects an input of second NAND gate, and another input of second NAND gate connects the non-end of output of second register; Reset signal connects the clear terminal that resets of first, second, third, fourth register respectively; The output of first, second NAND gate is as the input of the 3rd NAND gate, and the output of the 3rd NAND gate is the output clock of anti-burr clock selector.

Images