CN204615806U

CN204615806U - A kind of triplication redundancy voting circuit based on inverted logic

Info

Publication number: CN204615806U
Application number: CN201520338597.0U
Authority: CN
Inventors: 陈庆宇; 马徐瀚; 赵鲲鹏; 吴龙胜; 盛廷义
Original assignee: 771 Research Institute of 9th Academy of CASC
Current assignee: 771 Research Institute of 9th Academy of CASC
Priority date: 2015-05-22
Filing date: 2015-05-22
Publication date: 2015-09-02
Anticipated expiration: 2025-05-22

Abstract

The utility model provides a kind of TMR voting circuit hardware consumption low, the triplication redundancy voting circuit based on inverted logic that critical path shortens, and it comprises first liang of input nand gate, second liang of input nand gate, the 3rd liang of input nand gate and three input nand gates; Three inputs of triplication redundancy voting circuit are connected to the input of first liang of input nand gate, second liang of input nand gate, the 3rd liang of input nand gate between two respectively, the output of first, second and third NAND gate is connected to three inputs of three input nand gates respectively, and the output of three input nand gates exports the output signal of triplication redundancy voting circuit.While guarantee input and output are constant, circuit logic is optimized transformation, with meeting the logic voting circuit with the reverse expression formula of nand-type, make it the reverse feature that can not only meet cmos circuit output, and reduce hardware consumption, hardware consumption reduces by 30.7%, and the longest PMOS serial chain shortens original 1/3.

Description

A kind of triplication redundancy voting circuit based on inverted logic

Technical field

The utility model relates to digital circuit field, is specially a kind of triplication redundancy voting circuit based on inverted logic.

Background technology

At present, the extensive use in highly reliable CPU design of triplication redundancy (TMR) technology, TMR voting circuit realizes the Logic judgment of three acts two, needs to insert at each TMR Nodes, and its performance and hardware consumption affect very large on global design.

If three of TMR voting circuit are input as A, B and C, export as Y, the logical expression of voting circuit is Y=AB+AC+BC.Disclosed TMR voting circuit design is all directly map according to its logical expression, circuit structure as shown in Figure 1, the transistor level circuit of circuit structure shown in Fig. 1 as shown in Figure 2, circuit needs 26 metal-oxide-semiconductors altogether, three inputs or door introduce three series connection PMOS, cause the longest tandem paths in circuit to be 6 PMOS (in Fig. 2 201 ~ 206).Mobility due to hole is only 1/4 ~ 1/2 of electron mobility, and under the prerequisite of comparable size, the switch transmission rate based on the PMOS of hole conduction is only 1/4 ~ 1/2 of NMOS.The circuit structure of Fig. 1 does not consider that the output of CMOS is the feature of inverted logic, and PMOS serial chain longer in circuit structure can be caused to cause the performance loss of voting circuit.

Utility model content

For problems of the prior art, the utility model provides a kind of TMR voting circuit hardware consumption low, the triplication redundancy voting circuit based on inverted logic that critical path shortens.

The utility model is achieved through the following technical solutions:

Based on the triplication redundancy voting circuit of inverted logic, comprise first liang of input nand gate, second liang of input nand gate, the 3rd liang of input nand gate and three input nand gates; Three inputs of triplication redundancy voting circuit are connected to the input of first liang of input nand gate, second liang of input nand gate, the 3rd liang of input nand gate between two respectively, the output of first, second and third NAND gate is connected to three inputs of three input nand gates respectively, and the output of three input nand gates exports the output signal of triplication redundancy voting circuit.

Preferably, first, second and third two input nand gate is respectively the first gate be made up of four metal-oxide-semiconductors.

Further, the first gate comprises the upper trombone slide be made up of two PMOS in parallel, and the lower trombone slide of the NMOS tube composition of two series connection.

Preferably, three input nand gates are the second gate be made up of six metal-oxide-semiconductors.

Further, the second gate comprises the upper trombone slide be made up of three PMOS in parallel, and the lower trombone slide of the NMOS tube composition of three series connection.

Compared with prior art, the utility model has following useful technique effect:

The utility model is arranged by the combination of multiple NAND gate, while guarantee input and output are constant, circuit logic is optimized transformation, with meeting the reverse expression formula with nand-type logic voting circuits improvement meet with or the logic voting circuit of type forward logical expression Y=AB+BC+AC, make it the reverse feature that can not only meet cmos circuit output, and reduce hardware consumption, eliminate PMOS serial chain consuming time, hardware consumption reduces by 30.7%, and the longest PMOS serial chain shortens original 1/3; Rational in infrastructure, design ingenious, efficiency of transmission is high, and power consumption is little.

Further, by the expression formula of voting circuit being mapped respectively, by the setting of the metal-oxide-semiconductor of different structure and connection, meet the logic function of its each circuit part, structure is simple, arrangement convenience.

Accompanying drawing explanation

Fig. 1 is the circuit structure of TMR voting circuit in prior art.

Fig. 2 is PMOS serial chain schematic diagram in TMR voting circuit in prior art.

Fig. 3 is the schematic diagram of TMR voting circuit in the utility model.

Fig. 4 is the transistor-level structure schematic diagram of TMR voting circuit in the utility model.

In figure: A, B and C are respectively three inputs of triplication redundancy voting circuit, Y is that triplication redundancy voting circuit exports; 201,202,203,204,205 and 206 is that in prior art, in triplication redundancy voting circuit, the longest tandem paths is 6 PMOS; 301 is first liang of input nand gate, 302 is second liang of input nand gate, 303 is the 3rd liang of input nand gate, 304 is three input nand gates, first gate 405,406 and 407 is two PMOS of formation first gate, 408 and 409 is two NMOS tube of formation first gate, second gate 410,411,412 and 402 is three PMOS of formation second gate, 414,415 and 416 is three NMOS tube of formation second gate, and 401 is a PMOS in the longest PMOS serial chain of the utility model.

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in further detail, described in be to explanation of the present utility model instead of restriction.

A kind of triplication redundancy voting circuit based on inverted logic described in the utility model, by the anti-phase expression formula with nand-type , to TMR voting circuit with or type positive logical expression Y=AB+BC+AC be optimized, make it to meet the reverse feature that cmos circuit exports, inverted logic expression formula be mapped as the TMR voting circuit based on inverted logic.

Concrete, as shown in Figure 3, its circuit structure comprises first liang of input nand gate, 301, second liang of input nand gate 302, the 3rd liang of input nand gate 303 and three input nand gates 304.Three inputs A, B and C of TMR voting circuit, with wherein any two be divided into three groups of AB, AC and BC for unit, three groups of signals are connected to respectively the input of first liang of input nand gate, 301, second liang of input nand gate 302, the 3rd liang of input nand gate 303, and the output of first, second and third NAND gate is connected to three inputs of three input nand gates 304, the final output being TMR voting circuit of the output output of three input nand gates 304, namely its output signal Y needed.

With reference to figure 3 and Fig. 4, wherein, first, second and third two input nand gate is respectively the first basic gate 405 that four metal-oxide-semiconductors are formed; On in the first gate 405, trombone slide is two PMOS in parallel, and the label in figure is respectively 406 and 407, and the NMOS tube of lower trombone slide two series connection, the label in figure is respectively 408 and 409.

Wherein, three input nand gates 304 are the second basic gate 410 that six metal-oxide-semiconductors are formed; The PMOS that in the second gate 410, trombone slide three is in parallel, the label in figure is respectively 411,412 and 402, and the NMOS tube of lower trombone slide three series connection, the label in figure is respectively 414,415 and 416.

As shown in Figure 3 and Figure 4, disclosed in the utility model, a kind of triplication redundancy voting circuit based on inverted logic only needs 18 metal-oxide-semiconductors, the longest PMOS serial chain is 2 PMOS, number in the figure is 401 and 402, compared with the published circuit based on Y=AB+BC+AC as depicted in figs. 1 and 2, hardware consumption reduces by 30.7%, and the longest PMOS serial chain shortens original 1/3, shortens critical path.

Claims

1. based on the triplication redundancy voting circuit of inverted logic, it is characterized in that, comprise first liang of input nand gate (301), second liang of input nand gate (302), the 3rd liang of input nand gate (303) and three input nand gates (304);

Three inputs of triplication redundancy voting circuit are connected to the input of first liang of input nand gate (301), second liang of input nand gate (302), the 3rd liang of input nand gate (303) between two respectively, the output of first, second and third NAND gate (301,302,303) is connected to three inputs of three input nand gates (304) respectively, and the output of three input nand gates (304) exports the output signal of triplication redundancy voting circuit.

2. the triplication redundancy voting circuit based on inverted logic according to claim 1, it is characterized in that, described first, second and third two input nand gate (301,302,303) is respectively the first gate (405) be made up of four metal-oxide-semiconductors.

3. the triplication redundancy voting circuit based on inverted logic according to claim 2, is characterized in that, the first gate (405) comprises the upper trombone slide be made up of two PMOS in parallel, and the lower trombone slide of the NMOS tube composition of two series connection.

4. the triplication redundancy voting circuit based on inverted logic according to claim 1, is characterized in that, described three input nand gates (304) are the second gate (410) be made up of six metal-oxide-semiconductors.

5. the triplication redundancy voting circuit based on inverted logic according to claim 4, is characterized in that, the second gate (410) comprises the upper trombone slide be made up of three PMOS in parallel, and the lower trombone slide of the NMOS tube composition of three series connection.