CN104716940B - A kind of transistor level Low-Power CMOS AND/XOR gate circuits - Google Patents
A kind of transistor level Low-Power CMOS AND/XOR gate circuits Download PDFInfo
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Abstract
The invention discloses a kind of transistor level Low-Power CMOS AND/XOR gate circuits, feature is to utilize two bridge architectures, with reference to the advantage of static CMOS structure circuit, the structure of PMOS bridge-types one being made up of the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS and the 5th PMOS；The structure of NMOS bridge-types one being made up of the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube；The structure of PMOS bridge-types two that 4th PMOS and the 6th PMOS are constituted；The structure of NMOS bridge-types two that 5th NMOS tube and the 6th NMOS tube are constituted, it is to avoid the generation of short-circuit dissipation and subthreshold power consumption, significantly reduces the power consumption of circuit；The present invention compares the circuit of other identical functions, and power consumption improvement amount is up to 15%, and the improvement amount of Power dissipation delay (PDP) is up to 31%.
Description
Technical field
The present invention relates to a kind of AND/XOR gate circuits, more particularly, to a kind of transistor level Low-Power CMOS AND/XOR
Gate circuit.
Background technology
With the rapid raising of the complexity and integrated level of IC system, power consumption turns into after speed and area
Important indicator.Digital Logical Circuits can both use traditional boolean (Traditional Boolean, TB) based on AND-OR INVERTER
Logic realization, can also use Reed-Muller (RM) logic realization " with/XOR (AND/XOR) ".Relative to TB logics, RM
Logic has the advantages that the following aspects：(1) TB is compared with logical functions such as the arithmetical operation of RM logic realizations, odd and even parity functions
Logic is simply too much, such as the parity checker for a n variable, and 2 are needed with TB logic realizationsnIndividual word, and use RM logics
N word is then only needed to, this not only saves silicon area, and the advantage with potential power consumption and speed；(2) RM logics have
There is good measurability；(3) RM logic circuits are easy to be mapped to field programmable gate array (Filed Programmable
Gate Array, FPGA), this is due to that XOR gate will not cause extra area to increase in FPGA (such as table look-up FPGA).But
Why RM logics are not used widely as TB logics in industrial quarters, and it is comprehensive that one of its reason is a lack of suitable RM logics
The low-power consumption cell library of conjunction.In recent years, although be related to the research of AND/XOR, but be all use AND-gate and XOR/XNOR
Obtained structure is cascaded, there are problems that delay length, power consumption.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of on the premise of ensureing to have correct logic function, delay
The small transistor level Low-Power CMOS AND/XOR gate circuits of short, low in energy consumption, Power dissipation delay (PDP).
The present invention solve the technical scheme that is used of above-mentioned technical problem for：A kind of transistor level Low-Power CMOS AND/
XOR gate, by the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS, the 6th PMOS
Pipe, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube composition, institute
The source electrode for the first PMOS stated and the source electrode of the 4th described PMOS are connected to power input, the first described PMOS
Grid be connected with the inversion signal of the second input signal, the grid of described the 3rd PMOS is anti-phase with the first input signal
Signal is connected, and the grid of the 4th described PMOS is connected with the inversion signal of the 3rd input signal, the 3rd described PMOS
The drain electrode of source electrode and first PMOS and the source electrode of described the second PMOS and connect, the leakage of described the 3rd PMOS
Pole, the draining of the 4th described PMOS, the source electrode of the source electrode of the 5th described PMOS and the 6th described PMOS simultaneously connect,
The grid of the second described PMOS is connected with the second input signal, the grid and the 3rd input signal of described the 5th PMOS
Connection, the grid of the 6th described PMOS is connected with the first input signal, the draining of first NMOS tube, the described the 4th
The draining of NMOS tube, the draining of the drain electrode of the 6th described NMOS tube and the second described PMOS, the 5th described PMOS
Drain, the drain electrode of described 6th PMOS is connected to output end, the grid of described the first NMOS tube and the second input are believed
Number inversion signal connection, the grid of the 5th described NMOS tube is connected with the inversion signal of the 3rd input signal, described the
The grid of six NMOS tubes is connected with the inversion signal of the first input signal, the source electrode and described second of described the first NMOS tube
The draining of NMOS tube, the source electrode of the 3rd described NMOS tube simultaneously connect, the grid and the second input signal of described the second NMOS tube
Connection, the grid of the 3rd described NMOS tube is connected with the first input signal, the grid of described the 4th NMOS tube and the 3rd defeated
Enter signal connection, the source electrode of the second described NMOS tube is connected to ground, the described the 3rd with the source electrode of the 5th described NMOS tube
The draining of NMOS tube, the source electrode of the 4th described NMOS tube, the drain electrode of the 5th described NMOS tube and the 6th described NMOS tube
Source electrode and connect.
Compared with prior art, the advantage of the invention is that using two bridge architectures, with reference to static CMOS structure circuit
Advantage, it is proposed that a kind of AND/XOR gate circuits of the static CMOS structure of the bridge-type of transistor level, tested by HSPICE emulation
Card, circuit of the invention has correct logic function.The composition of wherein bridge architecture one is as follows：By the first PMOS, second
The structure of PMOS bridge-types one that PMOS, the 3rd PMOS, the 4th PMOS and the 5th PMOS are constituted；By the first NMOS tube,
The structure of NMOS bridge-types one that two NMOS tubes, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube are constituted；In the structure of bridge-type one
In, identical for two groups of output values, input signal has and only one is identical, in addition two all opposite numbers each other.Bridge-type knot
Structure two is consisted of：The structure of PMOS bridge-types two that 4th PMOS and the 6th PMOS are constituted；5th NMOS tube and the 6th
The structure of NMOS bridge-types two that NMOS tube is constituted；Identical for two groups of output values in the structure of bridge-type two, input signal has and only
Have two it is identical, a value either 0 or 1 does not affect corresponding logic function in addition.And each group of logic is only
Pipe is turned on correspondence all the way, output node voltage full swing, and other pipes are in the state being fully disconnected, so as to avoid
The generation of short-circuit dissipation and subthreshold power consumption, significantly reduces the power consumption of circuit；And circuit structure is symmetrical, is easy to the cloth of domain
Office；Further, since existing design is obtained by cmos nand gate and various classical XOR gate cascades, and the present invention is base
In the design of transistor level, the species of AND/XOR is more enriched.
Under HSPICE simulated environment, using 55nm CMOS technologies, the sub- size of PMOS takes 240nm/60nm, NMOS tube
Sub- size takes 120nm/60nm, and supply voltage takes VDD=1.2V, logical function verification is carried out to the circuit diagram 1 of the present invention first,
Simulation result is as shown in figure 4, wherein VA、VBAnd VCIt is three input signals, VOUTIt is output signal, as a result shows the electricity of the present invention
Road has correct logic function.Then circuit and the XOR by cmos nand gate and classics under 1GHz frequencies to the present invention
The circuit that gate leve connection is obtained carries out emulation comparison, and Fig. 6 gives the corresponding performance table of comparisons.Can be substantially from the table of comparisons
Arrive, performance of the invention is better than the circuit of other identical functions, power consumption improvement amount is up to 15%, and Power dissipation delay (PDP's) changes
Kind amount up to 31%.
Brief description of the drawings
Fig. 1 is the transistor level bridge-type static state CMOS of present invention AND/XOR gate structure schematic diagrames；
Fig. 2 is the logic true value table of AND/XOR gate circuits；
Fig. 3 distinguishes corresponding input signal ABC situation table when being output signal Y=0 and Y=1；
Fig. 4 is the logical simulation waveform diagram of the AND/XOR gate circuits of the present invention；
Fig. 5 is the schematic diagram of bridge circuit；
The circuit simulation performance pair that Fig. 6 obtains for the circuit of the present invention and by cmos nand gate with classical XOR gate cascade
According to table.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing embodiment.
As shown in figure 1, a kind of transistor level Low-Power CMOS AND/XOR gate circuits, by the first PMOS P1, second
PMOS P2, the 3rd PMOS P3, the 4th PMOS P4, the 5th PMOS P5, the 6th PMOS P6, the first NMOS tube N1,
Two NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5 and the 6th NMOS tube N6 compositions, the first PMOS
Pipe P1 source electrode and the 4th PMOS P4 source electrode are connected to power input VDD, the first PMOS P1 grid and second input
Signal B inversion signal connection, the 3rd PMOS P3 grid is connected with the first input signal A inversion signal, the 4th PMOS
Pipe P4 grid is connected with the 3rd input signal C inversion signal, the 3rd PMOS P3 source electrode, the first PMOS P1 leakage
Pole, the second PMOS P2 source electrode simultaneously connect, the 3rd PMOS P3 drain electrode, the 4th PMOS P4 drain electrode, the 5th PMOS P5
Source electrode and the 6th PMOS P6 source electrode and connect, the second PMOS P2 grid is connected with the second input signal B, the 5th PMOS
Pipe P5 grid is connected with the 3rd input signal C, and the 6th PMOS P6 grid is connected with the first input signal A, the first NMOS
Pipe N1 drain electrode, the 4th NMOS tube N4 drain electrode, the 6th NMOS tube N6 drain electrode drained with the second PMOS P2, the 5th PMOS
Pipe P5 drain electrode, the 6th PMOS P6 drain electrode are connected to output end Y, the first NMOS tube N1 grid and the second input signal B
Inversion signal connection, the 5th NMOS tube N5 grid is connected with the 3rd input signal C inversion signal, the 6th NMOS tube N6's
Grid is connected with the first input signal A inversion signal, the first NMOS tube N1 source electrode and the second NMOS tube N2 drain electrode, the 3rd
NMOS tube N3 source electrode is simultaneously connect, and the second NMOS tube N2 grid is connected with the second input signal B, the 3rd NMOS tube N3 grid with
First input signal A connections, the 4th NMOS tube N4 grid is connected with the 3rd input signal C, the second NMOS tube N2 source electrode with
5th NMOS tube N5 source electrode is connected to ground, the 3rd NMOS tube N3 drain electrode, the 4th NMOS tube N4 source electrode, the 5th NMOS tube N5
Drain electrode and the 6th NMOS tube N6 source electrode and connect.
A kind of design of transistor level low-power consumption bridge-type static state CMOS AND/XOR gate circuits proposed by the present invention, its is basic
Principle is：By truth table Fig. 2, combined according to the corresponding varying input signal of output Y value different in Fig. 3, it is proposed that bridge
The realization of formula structure, and then advantage according to static CMOS structure designs Fig. 1 circuit structure.And use HSPICE emulation tools
Functional simulation checking is carried out, is compared with existing CMOS AND-gates and XOR gate cascade structure performance.Its specific steps is such as
Under：
Step is 1.：By truth table Fig. 2, combined according to the corresponding varying input signal of output Y value different in Fig. 3,
Bridge architecture is obtained, as shown in Figure 5.It can be obtained by Fig. 5, two lines have a public input signal A in bridge architecture
Value, and other two input signals opposite number each other.Specially as Y=0 and A=1, the BC He of value 00 can be now taken
11 be one group of composition, one bridge；As Y=1 and A=1, the value 01 and 10 that can now take BC is one group of composition, one bridge；
Step is 2.：Step 1. in only account for ABC for 100 and 111,101 and 110 four kind input situation, in addition
Four kinds of situations can be obtained by following form：It can be obtained as A=C=0 by analysis, no matter B=0 or B=1, now Y is
0；It can similarly obtain, as A=0 and C=1, no matter B=0 or B=1, now Y is 1, can now obtain other two
Bridge；
Step is 3.：Low-power consumption realization based on static CMOS structure, each group of input signal route only corresponding with one
Transistor turns, and each state provides energy by VDD or GND, it is to avoid caused by the saltus step of input signal
NMOS, PMOS simultaneously turn on formed by power supply to ground path produced by short-circuit dissipation；M signal and output signal
All it is full swing, it is to avoid subthreshold power consumption caused by threshold value loss；
With reference to step 1., step bridge-type thought 2. and circuit is designed using the advantage of CMOS structure, finally
To circuit as shown in figure 1, the circuit belongs to static CMOS structure, by the bridge-type one including the left side and the bridge-type on the right two and three
Individual phase inverter, totally 18 transistors composition, symmetrical configuration is easy to domain to realize；
Step is 4.：Under 55nm CMOS technologies, the sub- size of PMOS takes 240nm/60nm, and the sub- size of NMOS tube takes
120nm/60nm, supply voltage takes VDD=1.2V, functional simulation checking is carried out with HSPICE, and simulation result is as shown in Figure 4.Wherein
VA、VBAnd VCIt is three input signals, VOUTIt is output signal, simulation result shows that the circuit proposed has correct logic work(
Energy；
Step is 5.：Performance comparision is carried out to the circuit that circuit shown in Fig. 1 and existing CMOS AND-gates and XOR gate are cascaded,
The sub- size of PMOS all takes 240nm/60nm, and the sub- size of NMOS tube takes 120nm/60nm, and supply voltage takes VDD=1.2V, frequency takes
1GHz.As a result comparative result as shown in fig. 6, show that the improvement amount of power consumption reaches 15%, the improvement amount of Power dissipation delay reaches
31%.
Claims (1)
1. a kind of transistor level Low-Power CMOS AND/XOR gate circuits, it is characterised in that by the first PMOS, the second PMOS,
3rd PMOS, the 4th PMOS, the 5th PMOS, the 6th PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube,
4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube composition, the source electrode and the 4th described PMOS of described the first PMOS
The source electrode of pipe is connected to power input, and the grid of the first described PMOS is connected with the inversion signal of the second input signal,
The grid of the 3rd described PMOS is connected with the inversion signal of the first input signal, the grid and of described the 4th PMOS
The inversion signal connection of three input signals, the described source electrode of the 3rd PMOS and the drain electrode of first PMOS and described
The source electrode of second PMOS simultaneously connects, the draining of described the 3rd PMOS, the draining of the 4th described PMOS, the described the 5th
The source electrode of PMOS and the source electrode of the 6th described PMOS simultaneously connect, the grid and the second input signal of described the second PMOS
Connection, the grid of the 5th described PMOS is connected with the 3rd input signal, the grid of described the 6th PMOS and first defeated
Enter signal connection, the draining of first NMOS tube, the draining of the 4th described NMOS tube, the drain electrode of the 6th described NMOS tube
Drain electrode with the draining of the second described PMOS, the draining of the 5th described PMOS, the 6th described PMOS is connected to
Output end, the grid of the first described NMOS tube is connected with the inversion signal of the second input signal, described the 5th NMOS tube
Grid is connected with the inversion signal of the 3rd input signal, the grid and the anti-phase letter of the first input signal of described the 6th NMOS tube
The draining of number connection, the source electrode of described the first NMOS tube and the second described NMOS tube, the source electrode of the 3rd described NMOS tube
And connect, the grid of the second described NMOS tube is connected with the second input signal, the grid of described the 3rd NMOS tube and first defeated
Enter signal connection, the grid of the 4th described NMOS tube is connected with the 3rd input signal, the source electrode of described the second NMOS tube and
The source electrode of the 5th described NMOS tube is connected to ground, the draining of described the 3rd NMOS tube, the source electrode of the 4th described NMOS tube,
The source electrode of the drain electrode of the 5th described NMOS tube and the 6th described NMOS tube simultaneously connects.
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| CN201410843654.0A CN104716940B (en) | 2014-12-30 | 2014-12-30 | A kind of transistor level Low-Power CMOS AND/XOR gate circuits |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1050968A1 (en) * | 1999-05-06 | 2000-11-08 | Matsushita Electric Industrial Co., Ltd. | CMOS semiconductor integrated circuit |
| CN103236837A (en) * | 2013-04-08 | 2013-08-07 | 宁波大学 | Sub-circuit extracting method of digital logic circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1050968A1 (en) * | 1999-05-06 | 2000-11-08 | Matsushita Electric Industrial Co., Ltd. | CMOS semiconductor integrated circuit |
| CN103236837A (en) * | 2013-04-08 | 2013-08-07 | 宁波大学 | Sub-circuit extracting method of digital logic circuit |
Non-Patent Citations (1)
| Title |
|---|
| A comparative performance analysis of various CMOS;MISHRA S S, AGRAWAL A K, NAGARIA R K;《International Journal on Emerging Technologies》;20101231;第1卷(第1期);全文 * |
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