CN103078629A - Full-adder circuit based on 7 different or same transistors or units - Google Patents
Full-adder circuit based on 7 different or same transistors or units Download PDFInfo
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- CN103078629A CN103078629A CN2012105816040A CN201210581604A CN103078629A CN 103078629 A CN103078629 A CN 103078629A CN 2012105816040 A CN2012105816040 A CN 2012105816040A CN 201210581604 A CN201210581604 A CN 201210581604A CN 103078629 A CN103078629 A CN 103078629A
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Abstract
The invention discloses a full-adder circuit based on 7 different or same transistors or units. The circuit comprises 7 different or same transistors or units, a full-adding module and a carry module, wherein the output ends of the 7 different or same transistors or units are connected with the input end of the full-adding module, and the output ends of the 7 different or same transistors or units are also connected with the input end of the carry module. The full-adder circuit based on 7 different or same transistors or units adopts less number of transistors, a circuit design with full voltage swing, low power consumption and low power consumption delay product is realized, and the high-speed low power consumption requirements of a super-large-scale integrated circuit are satisfied. The full-adder circuit based on 7 different or same transistors or units can be widely applied in the field of integrated circuit design.
Description
Technical field
The present invention relates to the integrated circuit (IC) design field, especially a kind of based on 7 pipe XORs with or the full adder circuit of unit.
Background technology
VLSI is the abbreviation of very lagre scale integrated circuit (VLSIC) (Very Large Scale Integration), refers on several millimeters square silicon chips integrated up to ten thousandly to 1,000,000, and body pipe, live width are at the integrated circuit below 1 micron.
The integrated level of very lagre scale integrated circuit (VLSIC) has reached 6,000,000 transistors at present, and live width reaches 0.3 micron.With the electronic equipment that very lagre scale integrated circuit (VLSIC) is made, volume is little, lightweight, low in energy consumption, reliability is high.Utilize very large scale integration technology with an electronics subsystem and even whole electronic system " integrated " on chip piece, to finish the several functions such as information gathering, processing, storage.
Most important performance parameter is speed and power consumption in the VLSI system.Power consumption-time-delay long-pending (PDP) is the result who power consumption and critical path time-delay is comprehensively weighed a quantification that obtains, it is a just performance metric, through being usually used in often planting the optimum results of circuit design, assessment adopts the circuit working of different process in the performance of different frequency different situations.Therefore, what the power consumption that tool reduces-time-delay was long-pending is the key that improves the VLSI performance, also is the key index of full adder circuit design.
Full adder is the circuit unit of a kind of key of the VLSI systems such as microprocessor, storage address maker, digital signal processor, and it often is in the critical path of these systems.Therefore the performance of full adder significantly impacts the performance of whole system.Can be obtained the function of one-bit full addres by following formula.
Wherein, H be half adder and (being A XOR B).The block diagram of full adder and internal structure are as shown in Figure 1.Module 1 is for generation of XOR and XNOR function, signal intermediate object program.Module 2 for generation of entirely add and.Module 3 is for generation of the carry result.Adopt multiple static logic circuit, utilize XOR with or the unit realize that the module 1 traditional full adder design in the full adder often has following several situation:
1, the one-bit full addres that forms of a kind of 16 transistors, its XOR with or the unit as shown in Figure 2.Although this XOR is same or circuit has the low-power consumption characteristic, because it designs based on transfer tube, does not have any level Restoration Mechanism, causes the problem of voltage drop, therefore can't provide the full voltage of output to swing.This non-complete level can cause a large amount of quiescent currents to leak, and has increased widely power consumption.
2, a kind of feedback XOR that is consisted of by six transistors with or circuit, it can provide the full voltage of all nodes to swing, as shown in Figure 3, but it still is faced with a voltage steps problem, this will cause the time-delay grown and higher voltage up-down time.
3, as shown in Figure 4, the mode of the third circuit design is to draw PMOS transistor and two pull-down NMOS transistors in two original of structure series connection of Fig. 3.Although solved the problem of above-mentioned two kinds of circuit,, it has greatly increased transistorized number, and this will increase node capacitance, bring sizable power consumption and significant critical path time-delay.
Based on above-mentioned situation as can be known, the at present design of full adder circuit can't be satisfied the requirement that low-power consumption-time-delay is amassed of VSLI system, and full adder how to design low-power consumption, high arithmetic speed characteristic is restricting the realization that numerical calculation is used.
Summary of the invention
In order to solve the problems of the technologies described above, the objective of the invention is: provide a kind of and manage XORs together or the full adder circuit of unit based on 7, it is not enough to overcome the conventional full-adder circuit design, have the full voltage amplitude of oscillation, low-power consumption, the long-pending characteristic of low-power consumption-time-delay, satisfy the requirement of the high-speed low-power-consumption of very lagre scale integrated circuit (VLSIC).
The technical solution adopted in the present invention is: a kind of based on 7 pipe XORs with or the full adder circuit of unit, this circuit include 7 pipe XORs with or the unit, entirely add and module and carry module, described 7 pipe XORs the output same or unit is connected to the input that entirely adds with module, and described 7 pipe XORs the output same or unit is also connected to the input of carry module.
Further, described 7 pipe XORs with or the unit include PMOS pipe, the 2nd PMOS pipe, the 4th PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe and CMOS inverter, the source electrode of a described PMOS pipe is connected with positive source, the drain electrode of a described PMOS pipe is connected with the source electrode of the 2nd PMOS pipe, the grid of a described PMOS pipe respectively with the grid of the 2nd PMOS pipe, the drain electrode of the one NMOS pipe, the grid of the 2nd NMOS pipe connects, the grid of described the 2nd NMOS pipe is managed together or the second input of XOR unit as 7, the drain electrode of described the 2nd PMOS pipe respectively with the source electrode of a NMOS pipe, the source electrode of the 2nd NMOS pipe, the drain electrode of the 4th PMOS pipe is connected input and is connected with the CMOS inverter, the drain electrode of described the 2nd PMOS pipe is managed together or the same or output port of XOR unit output as 7, the grid of a described NMOS pipe is connected with the drain electrode of the 2nd NMOS pipe, the grid of a described NMOS pipe is managed together or the first input end of XOR unit as 7, the source electrode of described the 4th PMOS pipe is connected with positive source, and the grid of described the 4th PMOS pipe is connected to the output of CMOS inverter and manages together or the XOR output port of XOR unit output as 7.
Further, described entirely adding with module, include the first transmission gate and data selector, the input of described the first transmission gate is connected to the control end of data selector and as the carry input that entirely adds with module, described 7 pipes with or the same or output port of XOR unit output be connected first input end with data selector with the second control end of the first transmission gate respectively and be connected, described 7 pipes with or the XOR output port of XOR unit output be connected the second input with data selector with the first control end of the first transmission gate respectively and be connected, the output of described the first transmission gate is connected to the output of data selector and conduct and entirely adds output with module.
Further, described carry module includes the second transmission gate and the 3rd transmission gate, described 7 pipes same or output port same or XOR unit output is connected with the first control end of the second transmission gate and the second control end of the 3rd transmission gate respectively, described 7 pipes XOR output port same or XOR unit output is connected with the second control end of the second transmission gate and the first control end of the 3rd transmission gate respectively, the input of described the second transmission gate is as the carry input of carry module, the input of described the 3rd transmission gate is as the signal input part of carry module, the input signal of the signal input part of described carry module and 7 pipes with or the input signal of the first input end of XOR unit identical, the output of described the second transmission gate is connected to the input of the 3rd transmission gate and as the output of carry module.
Further, described CMOS inverter is comprised of the 3rd PMOS pipe and the 3rd NMOS pipe.
Further, described the first transmission gate is comprised of the 4th NMOS pipe and the 5th PMOS pipe, and the grid of described the 5th PMOS pipe is as the first control end of the first transmission gate, and the grid of described the 4th NMOS pipe is as the second control end of the first transmission gate.
Further, described data selector is comprised of the 5th NMOS pipe and the 6th PMOS pipe, the grid of described the 5th NMOS pipe is connected to the grid of the 6th PMOS pipe and as the control end of data selector, the source electrode of described the 5th NMOS pipe is as the first input end of data selector, the source electrode of described the 6th PMOS pipe is as the second input of data selector, and the drain electrode of described the 5th NMOS pipe is connected to the drain electrode of the 6th PMOS pipe and as the output of data selector.
Further, described the second transmission gate is comprised of the 6th NMOS pipe and the 7th PMOS pipe, and the grid of described the 7th PMOS pipe is as the first control end of the second transmission gate, and the grid of described the 6th NMOS pipe is as the second control end of the second transmission gate; Described the 3rd transmission gate is comprised of the 7th NMOS pipe and the 8th PMOS pipe, and the grid of described the 8th PMOS pipe is as the first control end of the 3rd transmission gate, and the grid of described the 7th NMOS pipe is as the second control end of the 3rd transmission gate.
The invention has the beneficial effects as follows: 7 transistor XORs-with or circuit be to improve on the basis of original circuit design, at the PMOS transistor that the XNOR of non-full voltage amplitude of oscillation circuit base has increased a CMOS inverter and has been used for drawing, the PMOS transistor that CMOS inverter and be used for draws is as the recovery unit of signal level.At first, when output signal was " high level ", it was drawn high signal level as a voltage recovery unit.Secondly, this inverter can be used as the inversion signal of XNOR output, for generation of the XOR signal.Therefore, needn't increase the function that extra transistor just can produce XOR, realize the design of low-power consumption and the full voltage amplitude of oscillation.Further in the design that entirely adds with module and carry module, the present invention adopts the transfer tube and the transmission gate that do not have voltage drop problem to realize, because do not have the transfer tube of voltage drop problem and the power consumption that transmission gate circuit can further reduce whole full adder work, improve the overall performance of full adder.To sum up, the invention provides a kind of based on 7 pipe XORs with or the full adder circuit of unit, it is not enough to overcome the conventional full-adder circuit design, has the full voltage amplitude of oscillation, low-power consumption, the long-pending characteristic of low-power consumption-time-delay, satisfies the requirement of the high-speed low-power-consumption of very lagre scale integrated circuit (VLSIC).
Description of drawings
Fig. 1 is full adder block diagram and internal structure;
Fig. 2 is the same or circuit units of 8 transistorized XORs;
Fig. 3 is the same or circuit units of 6 transistorized XORs;
Fig. 4 is the same or circuit units of 10 transistorized XORs;
Fig. 5 is the same or circuit unit of a kind of XOR that 7 transistors of the present invention consist of;
Fig. 6 manages XORs together or the full adder circuit of circuit unit based on 7 of Fig. 5;
Fig. 7 is the circuit structure that entirely adds with module of the present invention;
Fig. 8 is the circuit structure of carry module of the present invention.
Among the figure: 1, PMOS pipe; 2, NMOS pipe; 3, the 2nd PMOS pipe; 4, the 2nd NMOS pipe; 5, the 3rd PMOS pipe; 6, the 3rd NMOS pipe; 7, the 4th PMOS pipe; 8, the 4th NMOS pipe; 9, the 5th PMOS pipe; 10, the 5th NMOS pipe; 11, the 6th PMOS pipe; 12, the 6th NMOS pipe; 13, the 7th PMOS pipe; 14, the 7th NMOS pipe; 15, the 8th PMOS pipe; 16, CMOS inverter; 17, the first transmission gate; 18, data selector; 19, the second transmission gate; 20, the 3rd transmission gate.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described further:
With reference to Fig. 6, a kind of based on 7 pipe XORs with or the full adder circuit of unit, this circuit include 7 pipe XORs with or the unit, entirely add and module and carry module, described 7 pipe XORs the output same or unit is connected to the input that entirely adds with module, and described 7 pipe XORs the output same or unit is also connected to the input of carry module.
Be further used as preferred embodiment, with reference to Fig. 5, described 7 pipe XORs with or the unit include PMOS pipe 1, the 2nd PMOS pipe 3, the 4th PMOS pipe 7, the one NMOS pipe 2, the 2nd NMOS pipe 4 and CMOS inverter 16, the source electrode of described PMOS pipe 1 is connected with positive source, the drain electrode of described PMOS pipe 1 is connected with the source electrode of the 2nd PMOS pipe 3, the grid of described PMOS pipe 1 is managed respectively 3 grid with the 2nd PMOS, the drain electrode of the one NMOS pipe 2, the grid of the 2nd NMOS pipe 4 connects, the grid of described the 2nd NMOS pipe 4 is managed together or the second input of XOR unit as 7,2 source electrode is managed respectively in the drain electrode of described the 2nd PMOS pipe 3 with a NMOS, the source electrode of the 2nd NMOS pipe 4, the input that the drain electrode of the 4th PMOS pipe 7 is connected with the CMOS inverter connects, the drain electrode of described the 2nd PMOS pipe 3 is managed together or the same or output port of XOR unit output as 7, the grid of described NMOS pipe 2 is connected with the drain electrode of the 2nd NMOS pipe 4, the grid of described NMOS pipe 2 is managed together or the first input end of XOR unit as 7, the source electrode of described the 4th PMOS pipe 7 is connected with positive source, and the grid of described the 4th PMOS pipe 7 is connected to the output of CMOS inverter 16 and manages together or the XOR output port of XOR unit output as 7.
Contrast the course of work of the XNOR circuit of traditional non-full voltage amplitude of oscillation, in the structure of the non-full voltage amplitude of oscillation circuit of Fig. 2, can find out, this XNOR circuit has voltage drop problem: when input AB=11, two NMOS manage equal conducting, this moment, output obtained " high level " level signal, therefore the level of output is not VDD, but the value of VDD deducts threshold values | Vnt|.Non-complete magnitude of voltage can be introduced a large amount of quiescent dissipations at inverter or buffer that output connects.And the PMOS transistor that the present invention has increased a CMOS inverter and has been used for drawing at the feedback loop of XNOR circuit, as the recovery unit of signal level.This unit has two effects.At first, when output signal was " high level ", it was drawn high signal level as a voltage recovery unit.Secondly, this inverter can be used as the inversion signal of XNOR output, for generation of the XOR signal.Therefore, needn't increase the function that extra transistor just can produce XOR.Design like this 7 the pipe XORs with or circuit both had full voltage amplitude of oscillation function, do not increase again extra power consumption.
Be further used as preferred embodiment, with reference to Fig. 7, described entirely adding with module, include the first transmission gate 17 and data selector 18, the input of described the first transmission gate 17 is connected to the control end of data selector 18 and as the carry input that entirely adds with module, described 7 pipes same or output port same or XOR unit output is connected with the first input end that the second control end of the first transmission gate 17 is connected with data selector respectively, described 7 pipes with or the XOR output ports of XOR unit output is connected with the second input that the first control end of the first transmission gate 17 is connected with data selector respectively, the output of described the first transmission gate 17 is connected to the output of data selector 18 and conduct and entirely adds output with module.
Be further used as preferred embodiment, with reference to Fig. 8, described carry module includes the second transmission gate 19 and the 3rd transmission gate 20, described 7 pipes same or output port same or XOR unit output is connected with the first control end of the second transmission gate 19 and the second control end of the 3rd transmission gate 20 respectively, described 7 pipes XOR output port same or XOR unit output is connected with the second control end of the second transmission gate 19 and the first control end of the 3rd transmission gate 20 respectively, the input of described the second transmission gate 19 is as the carry input of carry module, the input of described the 3rd transmission gate 20 is as the signal input part of carry module, the input signal of the signal input part of described carry module and 7 pipes with or the input signal of the first input end of XOR unit identical, the output of described the second transmission gate 19 is connected to the input of the 3rd transmission gate 20 and as the output of carry module.
Based on the above-mentioned same or circuit unit of XOR that is consisted of by 7 transistors, the present invention has further proposed a kind of new full adder that is made of 15 transistors, this full adder adopts novel 7 of foregoing invention to manage XORs together or circuit unit, entirely adding with module and the employing of carry module does not have the transfer tube of voltage drop problem and transmission gate to realize, the overall construction design of this full adder as shown in Figure 6, wherein 7 pipe XORs with or the circuit design of circuit unit as shown in Figure 5, entirely add circuit structure with module and carry module respectively such as Fig. 7, shown in Figure 8.
Be further used as preferred embodiment, with reference to Fig. 5, described CMOS inverter 16 is comprised of the 3rd PMOS pipe the 5 and the 3rd NMOS pipe 6.
Be further used as preferred embodiment, with reference to Fig. 7, described the first transmission gate 17 is comprised of the 4th NMOS pipe the 8 and the 5th PMOS pipe 9, the grid of described the 5th PMOS pipe 9 is as the first control end of the first transmission gate 17, and the grid of described the 4th NMOS pipe 8 is as the second control end of the first transmission gate 17.
Be further used as preferred embodiment, with reference to Fig. 7, described data selector 18 is comprised of the 5th NMOS pipe the 10 and the 6th PMOS pipe 11, the grid of described the 5th NMOS pipe 10 is connected to the grid of the 6th PMOS pipe 11 and as the control end of data selector 18, the source electrode of described the 5th NMOS pipe 10 is as the first input end of data selector 18, the source electrode of described the 6th PMOS pipe 11 is as the second input of data selector 18, and the drain electrode of described the 5th NMOS pipe 10 is connected to the drain electrode of the 6th PMOS pipe 11 and as the output of data selector 18.
Be further used as preferred embodiment, with reference to Fig. 8, described the second transmission gate 19 is comprised of the 6th NMOS pipe the 12 and the 7th PMOS pipe 13, the grid of described the 7th PMOS pipe 13 is as the first control end of the second transmission gate 19, and the grid of described the 6th NMOS pipe 12 is as the second control end of the second transmission gate 19; Described the 3rd transmission gate 20 is comprised of the 7th NMOS pipe the 14 and the 8th PMOS pipe 15, and the grid of described the 8th PMOS pipe 15 is as the first control end of the 3rd transmission gate 20, and the grid of described the 7th NMOS pipe 14 is as the second control end of the 3rd transmission gate 20.
Full adder is because the novel same or circuit unit of 7 pipe XORs that adopts, have full voltage amplitude of oscillation function and low power capabilities, realized by the transfer tube that does not have voltage drop problem and transmission gate that and entirely add with module and carry module this will further improve the low-power consumption of full adder-time-delay and amass performance.So that the full adder circuit of this invention has lower power consumption, the full voltage amplitude of oscillation, higher performances such as speed.
To specific embodiments of the invention, by the HSPICE emulation tool circuit delay under its power consumption and the worst case is carried out emulation, and simultaneously the circuit of Fig. 3, Fig. 4 is carried out emulation, draw emulated data such as table 1.
By simulation result as can be known, the low-power consumption time delay integration of the full adder that the present invention proposes has not reduced by 22.7% and 17.1% than the full adder of Fig. 3 and Fig. 4, and novel full adder of the present invention has better performance at aspects such as low-power consumption, critical path time-delay, low-power consumption time delay amass.
More than be that better enforcement of the present invention is specified, but the invention is not limited to described embodiment, those of ordinary skill in the art can also make all equivalent variations or replacement under the prerequisite of spirit of the present invention, the distortion that these are equal to or replacement all are included in the application's claim limited range.
Claims (8)
- One kind based on 7 pipe XORs with or the full adder circuit of unit, it is characterized in that: this circuit include 7 pipe XORs with or the unit, entirely add and module and carry module, described 7 pipe XORs the output same or unit is connected to the input that entirely adds with module, and described 7 pipe XORs the output same or unit is also connected to the input of carry module.
- According to claim 1 a kind of based on 7 pipe XORs with or the full adder circuit of unit, it is characterized in that: described 7 pipe XORs with or the unit include PMOS pipe (1), the 2nd PMOS manages (3), the 4th PMOS manages (7), the one NMOS manages (2), the 2nd NMOS manages (4) and CMOS inverter (16), the source electrode of described PMOS pipe (1) is connected with positive source, the drain electrode of described PMOS pipe (1) is connected with the source electrode that the 2nd PMOS manages (3), the grid of described PMOS pipe (1) is managed respectively the grid of (3) with the 2nd PMOS, the drain electrode of the one NMOS pipe (2), the grid of the 2nd NMOS pipe (4) connects, the grid of described the 2nd NMOS pipe (4) is managed together or the second input of XOR unit as 7, the source electrode of (2) is managed respectively in the drain electrode of described the 2nd PMOS pipe (3) with a NMOS, the source electrode of the 2nd NMOS pipe (4), the drain electrode of the 4th PMOS pipe (7) is connected 16 with the CMOS inverter) input connect, the drain electrode of described the 2nd PMOS pipe (3) is managed together or the same or output port of XOR unit output as 7, the grid of described NMOS pipe (2) is connected with the drain electrode that the 2nd NMOS manages (4), the grid of described NMOS pipe (2) is managed together or the first input end of XOR unit as 7, the source electrode of described the 4th PMOS pipe (7) is connected with positive source, and the grid of described the 4th PMOS pipe (7) is connected to the output of CMOS inverter (16) and manages together or the XOR output port of XOR unit output as 7.
- According to claim 2 a kind of based on 7 pipe XORs with or the full adder circuit of unit, it is characterized in that: described entirely adding with module, include the first transmission gate (17) and data selector (18), the input of described the first transmission gate (17) is connected to the control end of data selector (18) and as the carry input that entirely adds with module, described 7 pipes with or the same or output ports of XOR unit output be connected 18 with the second control end of the first transmission gate (17) with data selector respectively) first input end be connected, described 7 pipes with or the XOR output ports of XOR unit output be connected 18 with the first control end of the first transmission gate (17) with data selector respectively) the second input is connected, the output of described the first transmission gate (17) is connected to the output of data selector (18) and conduct and entirely adds output with module.
- According to claim 2 a kind of based on 7 pipe XORs with or the full adder circuit of unit, it is characterized in that: described carry module includes the second transmission gate (19) and the 3rd transmission gate (20), described 7 pipes same or output port same or XOR unit output is connected with the first control end of the second transmission gate (19) and the second control end of the 3rd transmission gate (20) respectively, described 7 pipes XOR output port same or XOR unit output is connected with the second control end of the second transmission gate (19) and the first control end of the 3rd transmission gate (20) respectively, the input of described the second transmission gate (19) is as the carry input of carry module, the input of described the 3rd transmission gate (20) is as the signal input part of carry module, the input signal of the signal input part of described carry module and 7 pipes with or the input signal of the first input end of XOR unit identical, the output of described the second transmission gate (19) is connected to the input of the 3rd transmission gate (20) and as the output of carry module.
- According to claim 2 a kind of based on 7 pipe XORs with or the full adder circuit of unit, it is characterized in that: described CMOS inverter (16) is managed (6) by the 3rd PMOS pipe (5) and the 3rd NMOS and is formed.
- According to claim 3 a kind of based on 7 pipe XORs with or the full adder circuit of unit, it is characterized in that: described the first transmission gate (17) is comprised of the 4th NMOS pipe (8) and the 5th PMOS pipe (9), the grid of described the 5th PMOS pipe (9) is as the first control end of the first transmission gate (17), and the grid of described the 4th NMOS pipe (8) is as the second control end of the first transmission gate (17).
- According to claim 3 a kind of based on 7 pipe XORs with or the full adder circuit of unit, it is characterized in that: described data selector (18) is comprised of the 5th NMOS pipe (10) and the 6th PMOS pipe (11), the grid of described the 5th NMOS pipe (10) is connected to the grid of the 6th PMOS pipe (11) and as the control end of data selector (18), the source electrode of described the 5th NMOS pipe (10) is as the first input end of data selector (18), the source electrode of described the 6th PMOS pipe (11) is as the second input of data selector (18), and the drain electrode of described the 5th NMOS pipe (10) is connected to the drain electrode of the 6th PMOS pipe (11) and as the output of data selector (18).
- According to claim 4 a kind of based on 7 pipe XORs with or the full adder circuit of unit, it is characterized in that: described the second transmission gate (19) is comprised of the 6th NMOS pipe (12) and the 7th PMOS pipe (13), the grid of described the 7th PMOS pipe (13) is as the first control end of the second transmission gate (19), and the grid of described the 6th NMOS pipe (12) is as the second control end of the second transmission gate (19); Described the 3rd transmission gate (20) is comprised of the 7th NMOS pipe (14) and the 8th PMOS pipe (15), the grid of described the 8th PMOS pipe (15) is as the first control end of the 3rd transmission gate (20), and the grid of described the 7th NMOS pipe (14) is as the second control end of the 3rd transmission gate (20).
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| CN103368560A (en) * | 2013-06-25 | 2013-10-23 | 浙江大学 | Triple-modular redundancy voter |
| CN105471424A (en) * | 2014-09-25 | 2016-04-06 | 德克萨斯仪器股份有限公司 | Low area full adder with shared transistors |
| CN105471424B (en) * | 2014-09-25 | 2020-11-03 | 德克萨斯仪器股份有限公司 | Low area full adder with shared transistors |
| CN110995246B (en) * | 2019-11-28 | 2022-09-16 | 重庆中易智芯科技有限责任公司 | Low-power-consumption full adder circuit with reset function |
| CN110995246A (en) * | 2019-11-28 | 2020-04-10 | 重庆中易智芯科技有限责任公司 | Low-power-consumption full adder circuit with reset function |
| US11507347B2 (en) | 2020-06-30 | 2022-11-22 | Shenzhen Microbt Electronics Technology Co., Ltd. | Full adder, chip and computing device |
| WO2022001414A1 (en) * | 2020-06-30 | 2022-01-06 | 深圳比特微电子科技有限公司 | Full adder, chip, and computing device |
| WO2022151723A1 (en) * | 2021-01-14 | 2022-07-21 | 长鑫存储技术有限公司 | Comparison system |
| US11599417B2 (en) | 2021-01-14 | 2023-03-07 | Changxin Memory Technologies, Inc. | Error correction system |
| US11791009B2 (en) | 2021-01-14 | 2023-10-17 | Changxin Memory Technologies, Inc. | Error correction system |
| US11886292B2 (en) | 2021-01-14 | 2024-01-30 | Changxin Memory Technologies, Inc. | Memory system |
| US11935616B2 (en) | 2021-01-14 | 2024-03-19 | Changxin Memory Technologies, Inc. | Comparison system |
| CN114710150B (en) * | 2022-05-31 | 2022-08-09 | 中科南京智能技术研究院 | CMOS full adder |
| CN114710150A (en) * | 2022-05-31 | 2022-07-05 | 中科南京智能技术研究院 | CMOS full adder |
| CN116243885A (en) * | 2023-05-12 | 2023-06-09 | 之江实验室 | Full adder circuit and multi-bit full adder |
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