JPH0756713A - Full adder circuit - Google Patents

Abstract

PURPOSE:To provide a full adder circuit capable of improving the delay propagation time of a carry signal from an 1-bit full adder circuit and sharply shortening the addition delay time of many bits. CONSTITUTION:This full adder circuit is constituted of transfer gates 101 to 112 and inverters 113 to 116. Signals Cn, the inverse of Cn, An, the inverse of AYL are connected to the gates 101 to 107 and the gates 101 to 104 are connected to the inverters 113, 114 so the the outputs of the inverters 114, 113 becomes Sn and the inverse of Sn. Gates 105, 106 and 107, 108 are respectively connected to the inverters 115, 116 so that the outputs of the inverters 116, 115 become Cn+1 and the inverse of Cn+1. Signals Bn, the inverse of Bn are connected to the input gates of the gates 109, 112 and 110, 111 whose switching control signal is An or the inverse of An, and the switching control of the gates 101 to 108 is executed by the outputs of the gates 109, 112 and the outputs of the gates 111, 112. Consequently, the inverse of Sn, Sn, the inverse of Cn+1, Cn+1 of respective gates 113 to 115 are respectively outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full adder circuit, and more particularly to a full adder circuit (full adder) constructed by using CMOS transistors.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional full adder circuit. The n-th digit input signal (addition number) A _n , the n-th digit input signal (addend) B _n, and the carry signal C _n from the lower digit to the n-th digit are input, and the addition output signal S _It has a circuit function of outputting _n and a carry signal C _{n + 1} to the upper digit. As shown in FIG. 3, exclusive OR gates 200 and 201 and NAND gates 202 to 204 are connected as shown in the figure. A _n and B _n are exclusive OR gates 2
00 and the input of the NAND gate 203, and C _n is N
They are input to the inputs of the AND gate 202, respectively. Further, S _n is the output of the exclusive OR gate 201, and C _{n + 1} is NA.
It is output from the output of the ND gate 204. If this operation is expressed by a logical expression,

[0003]

[Equation 1]

[0004] Here,

[0005]

[Equation 2]

Indicates an exclusive OR.

FIG. 4 is a circuit diagram of a conventional full adder circuit in which the number of additions and the number of augends are N bits. Here, A ₀ and B ₀ indicate the least significant bits (LSB) of the addition number A and the augend B, and A _N-1 and B _N-1 indicate the most significant bit (MSB), respectively. In this circuit, the output S is N
+1 bit and S ₀ and S _N are LSB and MS respectively
Represents B.

FIG. 5 is a truth diagram showing the logical operation of FIG.
A _n, B _n, in accordance with the truth operation of C _n S _n and C _{n + 1}
Performs a logical operation as shown in the figure. This shows the operation of the full adder circuit.

[0009]

However, in the above-described conventional full adder circuit, when the delay time from A _n , B _n , C _n to S _n , C _{n + 1} is taken into consideration, the exclusive OR is applied to S _n. There are two stages of gates, and for C _{n + 1} there is a propagation delay time of one stage of exclusive OR gate and two stages of NAND gate. Therefore, for example, when considering addition of multiple bits as shown in FIG. 3, there is a problem that the output delay time of C _{n + 1} becomes a critical path and the delay time is accumulated by the number of bits, which is not suitable for high speed operation.

The present invention has been made to solve the above-mentioned problems, and it is possible to improve the delay propagation time of a carry signal of a 1-bit full adder circuit and significantly reduce the multi-bit addition delay time. It is an object to provide a possible full adder circuit.

[0011]

The present invention is based on the n-th digit input signals A _n and B _n and the carry signal C _n , and the addition output signal S _n and the n + 1-digit carry signal C _{n +.} in full adder to create a ₁ and the input terminal to the supply terminal of the signal C _n has a first transfer gate output terminal to the supply terminal of the signal S _n is connected, the input to the supply terminal of the signal -C _n A second transfer gate whose terminal is connected to the output terminal of the signal S _{n, and} whose input terminal is connected to the signal C _n supply terminal, and whose output terminal is connected to the signal -S _n supply terminal Of the transfer gate and the supply terminal of the signal -C _n , the input terminal is connected to the supply terminal of the signal -S _n , and the input terminal is connected to the supply terminal of the signal C _n. fifth Toransufu to C n _{+ 1} output terminals to the supply terminal of is connected And the Geto, signal A _n
The input terminal to the supply terminal, a sixth transfer gate of which the signal C _{n + 1} output terminals to the supply terminal of is connected, the input terminal to the supply terminal of the signal -C _n, supplying signals -C n _{+ 1} The seventh transfer gate whose output terminal is connected to the terminal and the input terminal to the signal -A _n supply terminal are connected to the signal -C _{n + 1.}
An eighth transfer gate whose output terminal is connected to the supply terminal of the signal, a ninth transfer gate whose input terminal is connected to the supply terminal of the signal B _n , and a ninth control gate whose output terminal is connected to the first control output terminal; an input terminal to the supply terminal of the B _n is 10 and transfer gate of which the output terminal to the first control output terminals are connected, the input terminal to the supply terminal of the signal -B _n, output to the second control output terminal 11th terminal is connected
And a twelfth transfer gate having an input terminal connected to the supply terminal of the signal B _n and an output terminal connected to the first control output terminal, from the first and second control output terminals. According to the control output of
It controls the transfer gate of.

[0012]

In the present invention, by adopting the above-mentioned means, the number of gates from the input to the output is the same for all input signals and carry signals. Therefore, the signal propagation delay time from the input to the output is the same, and the number of gate stages is smaller than in the conventional case, so that the output delay time can be reduced.

[0013]

FIG. 1 shows a circuit diagram of an embodiment of the present invention. C _n and its inverted output −C _n are connected to the input terminals of the transfer gates 101, 103 and 105 and the transfer gates 102, 104 and 107, respectively. The signal A _n and its inverted output −A _n
Are connected to the input terminals of the transfer gates 106 and 108, respectively. Transfer gate 101, 1
The output of 02 is connected to the input terminal of the inverter 113,
The outputs of the transfer gates 103 and 104 are connected to the input terminal of the inverter 114. As a result, the outputs of the inverters 114 and 113 become S _n and its inverted output signal −S _n , respectively.

The outputs of the transfer gates 105 and 106 are connected to the input terminal of the inverter 115, and the outputs of the transfer gates 107 and 108 are connected to the input terminal of the inverter 116. The outputs of the inverters 116 and 115 are C _{n + 1} and its inverted signal −C _{n + 1} , respectively.
B _n and its inverted output −B _n are connected to the input terminals of the transfer gates 109 and 112 and the transfer gates 110 and 111 whose switching control signals are A _n or −A _n , respectively. The outputs of the transfer gates 109 and 110 and the outputs of the transfer gates 111 and 112 perform switching control of the transfer gates 101 to 108.
Thus -S _n in the output of the inverter 113, S _n in the output of the inverter 114 is, -C _{n + 1} to the output of the inverter 115 is, C _{n + 1} are output to the output of the inverter 116.

FIG. 2 is a truth diagram showing the logical operation of FIG. The truth value operation is performed as shown in this figure. Therefore, the same operation as the conventional truth diagram shown in FIG. 5 is performed.

As is clear from the circuit configuration of FIG.
A in the light_n, A_n, B_n, B_n, C _n, -C_nFrom
S_n, -S_n, C_n, -C_nDelay time to transfer
Only one gate and one inverter are all the same
Has become. In the conventional circuit, S_nAn exclusive argument for
Two stages of Riwa gate, C_{n + 1}For exclusive OR game
There is a delay time between one stage and two stages of NAND gates.
Was there. Therefore, the delay time is greatly reduced compared to the conventional method.
The same delay time between all inputs and outputs
Becomes

[0017]

As described above in detail with reference to the embodiments, the present invention employs a circuit configuration in which the delay time is determined by one transfer gate stage and one inverter stage. The delay time can be reduced by one stage to two stages. Further, since the delay times from the input signal to the output signal are all the same, when a multi-bit adder circuit is constructed, the critical path of the carry signal can be greatly improved and high speed operation can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a truth diagram showing the logical operation of FIG.

FIG. 3 is a circuit diagram of a conventional full adder circuit.

FIG. 4 is a circuit diagram of a conventional full adder circuit when the number of additions and the number of augends are N bits.

FIG. 5 is a truth diagram showing the logical operation of FIG.

[Explanation of symbols]

A _{n n} th digit input signal (addition number) B _{n n} th digit input signal (addend) C _n n th digit carry signal S _n n th digit addition output signal 101 to 112 Transfer gate 113 to 116 inverter

Claims (1)

[Claims] 1. A full adder circuit for generating an addition output signal S _n and a carry signal C _{n + 1 of the (n +} 1) th digit based on the nth digit input signals A _n , B _n and the carry signal C _n. And a first transfer gate having an input terminal connected to the signal C _n supply terminal and an output terminal connected to the signal S _n supply terminal, and an input terminal connected to the signal -C _n supply terminal supplying the signal S _n a second transfer gate output terminal pin is connected, the input terminal to the supply terminal of the signal C _n has a third transfer gate output terminal to the supply terminal of the signal -S _n are connected, the signal -C _A fourth transfer gate having an input terminal connected to the supply terminal of _n , an output terminal connected to the supply terminal of signal -S _n , an input terminal connected to the supply terminal of signal C _{n, and} a supply terminal connected to signal C _{n + 1.} a transfer gate of the fifth output terminal is connected, the signal a _n An input terminal to the supply terminal, a sixth transfer gate of which the signal C _{n + 1} output terminals to the supply terminal of is connected, the input terminal to the supply terminal of the signal -C _n, supply terminal of the signal -C n _{+ 1} A seventh transfer gate whose output terminal is connected to, an eighth transfer gate whose input terminal is connected to the signal -A _n supply terminal and whose output terminal is connected to the signal -C _{n + 1} supply terminal; an input terminal to the supply terminal of the B _n is a transfer gate of the ninth output terminal to the first control output terminals are connected, the input terminal to the supply terminal of the signal -B _n, output to the first control output terminal A tenth transfer gate to which a terminal is connected, an input terminal to a signal- _Bn supply terminal and an output terminal to a second control output terminal, and a signal _Bn supply terminal Input terminal is the first control output A twelfth transfer gate having an output terminal connected to the terminal, and controlling the first to eighth transfer gates by control outputs from the first and second control output terminals. Full adder circuit.