JP2629737B2 - accumulator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an accumulator, and is particularly suitable for cumulative addition of digital values having a long word length.

[Summary of the Invention]

The present invention relates to an accumulator, in which a supplied value is supplied to a full adder circuit, and an addition output and a carry output from the full adder circuit are fed back via a register to perform cumulative addition. By inputting the upper output to the carry adder circuit to obtain a cumulative output, it is possible to increase the operation speed particularly at the time of cumulative addition.

[Conventional technology]

A conventional accumulator is configured, for example, as shown in FIG. In the figure, a sequentially supplied value X is input to an n-bit carry adder (7), and the added output is also input to an n-bit register (8), and the output of the register (8) is added to the adder. Returned to (7).

That is, in this device, the previous addition value stored in the register (8) is fed back to the addition circuit (7) and added to the newly supplied value X, and the added output is stored again in the register (8). This is repeated to perform cumulative addition. The clear signal CLR is supplied to the register (8) immediately before the start of the desired cumulative addition period, and the cumulative addition is performed from the time when the content stored in the register (8) is reset to "0". Register (8) at the end
By extracting the stored contents of, the accumulated value ΣX can be obtained.

[Problems to be solved by the invention]

However, in the above device, the carry adder circuit (31) and the register (32) are specifically configured as shown in FIG. The figure shows the case where n = 4 bits.

In the figure, four bits LSB to MSB of the value X are supplied to one input terminal A of the full adders (FA) (71) to (74), respectively, and the addition output terminals of the circuits (71) to (74) are provided. The signal from S is supplied to the registers (R) (81) to (84), respectively. Further, signals from the registers (81) to (84) are supplied to the other input terminals B of the circuits (71) to (74), respectively, and from the carry output terminals CO of the circuits (71) to (73). Are supplied to the carry input terminals CI of the circuits (72) to (74) one bit higher.

In this device, each full adder circuit (71) to (74)
When signals are supplied to the input terminals A and B, the addition operation is first performed in the circuit (71) on the LSB side, the added output formed here is taken out, and the carry output is higher by one bit. The signal is supplied to the circuit (72) and the addition operation is performed in the next circuit (72). Therefore, since each carry output is sequentially propagated and the operation is performed, the entire operation time is extremely long.

For this reason, when the value of n becomes large, the delay time due to this operation limits the cycle time of the processing, and there has been a problem that the cumulative addition cannot be performed on the high-speed signal.

On the other hand, the operation speed can be increased by using a so-called carry look-ahead addition circuit (CLA). However, as the value of n increases, the operation speed of the CLA is limited, and C
LA generally had a problem that the amount of hardware became extremely large.

[Means for solving the problem]

According to the present invention, in an accumulator for cumulatively adding a plurality of values X sequentially supplied, the supplied value is input to a full adder circuit (1), and an addition output and a carry output of the full adder circuit are respectively output to a first adder. Input to the first and second registers (2) and (3), and output the outputs of the first and second registers, which are the previous inputs, to the full adder circuit with respect to the supplied value, which is the current input. The accumulator is configured to perform cumulative addition, and to input the addition output and the carry output to the carry addition circuit (6) to obtain a cumulative addition output ΣX.

[Action]

According to this, in the cumulative addition period, addition is performed using the full addition circuit, and carry-over is performed only when the cumulative value is obtained. Therefore, the operation speed at the time of cumulative addition is increased, and the cycle time of processing is reduced. Since the length is shortened, the cumulative addition for the high-speed signal can be easily realized.

〔Example〕

 FIG. 1 shows a configuration for one bit.

In this figure, an arbitrary bit of a value X sequentially supplied is supplied to one input terminal A of a full adder (1). Signals from the addition output terminal S and the carry output terminal CO of the full addition circuit (1) are supplied to registers (2) and (3), respectively.
The signal from the register (2) is supplied to the other input terminal B of the full adder circuit (1), and the signal from the register (3) is sent one bit higher, and the signal from the one bit lower is fully input. It is supplied to the carry input terminal CI of the adder circuit (1). Further, the signals from the registers (2) and (3) are transmitted to the register (4).
(5), and the signals from these registers (4) and (5) are supplied to the carry adder circuit (6).

FIG. 2 shows a specific circuit when n = 4 bits, for example. In this figure, four bits LSB to MSB of the value X are supplied to one input terminal A of the full adder circuits (FA) (11) to (14), respectively, and the addition output terminals of the circuits (11) to (14) are provided. The signals from S are respectively the registers (R) (21) to (2)
4) and the signals from the carry output terminals CO of the circuits (11) to (13) are supplied to the registers (31) to (33), respectively. The signals from the registers (21) to (24) are supplied to the other input terminals B of the circuits (11) to (14), respectively, and the signals from the registers (31) to (33) are each higher by one bit. Input terminals of circuits (12) to (14)
Supplied to CI.

Further, the signals from the registers (21) to (24) and (31) to (33) are respectively applied to the registers (41) to (44) and (51).
To (53). The signals from the registers (42) to (44) are supplied to one input terminal A of the full adders (62) to (64), respectively, and the registers (51) to (53)
From the circuits (62)-(6)
4), and is supplied to the other input terminal B of this circuit (62) (6).
The signal from the carry output terminal CO of 3) is supplied to the carry input terminal CI of each of the circuits (63) and (64) one bit higher. Then, a 4-bit accumulated value ΣX is taken out from the addition output terminal S of the register (41) and the circuits (62) to (63).

That is, in this device, the clear signal CLR is supplied to the registers (21) to (24) and (31) to (33) immediately before the start of the desired cumulative addition period, and the contents stored in the register are reset to "0". The cumulative addition is performed from the point in time. Then, at the end of the cumulative period, the registers (41) to (44) and (51)
Since the hold signal HLD is supplied to the registers (21) to (24) and (31) to (53) at this time,
The contents stored in (33) are registers (41) to (44) and (51)
(53), and the contents are stored in the full adder circuit (62).
At (64), carry-up is performed to obtain the cumulative addition value ΣX.

Therefore, according to this device, during the cumulative addition period, addition is performed using the full addition circuit, and carry-over is performed only when the cumulative addition value is obtained.
The cycle time of the processing is shortened, and the cumulative addition for the high-speed signal can be easily realized.

That is, in this device, it is possible to realize an accumulator in which the cycle time is the operation time of the 1-bit full adder circuit plus the delay time of the register.

In the above-described apparatus, the number n of operation bits needs to be sufficiently large so as not to cause overflow. In this case, however, the operation speed does not decrease due to the long word length.

Also, if the accumulative addition period is sufficiently long in the above-described device, an extremely slow carry-up circuit (6) can be used. Therefore, the hardware for this can be made very small, and the circuit scale can be made extremely small as compared with the case where CLA is used, for example.

Further, according to the above-described apparatus, the circuit portions such as the full adder circuits (11) to (14) that operate at high speed have a strong regularity, and are extremely advantageous when formed in a VLSI or the like.

〔The invention's effect〕

According to the present invention, in the cumulative addition period, addition is performed using the full addition circuit, and carry-over is performed only when a cumulative value is obtained, so that the operation speed at the time of cumulative addition is increased, and the cycle time of processing is increased. Has been shortened so that cumulative addition for high-speed signals can be easily realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of the present invention, FIG. 2 is a diagram for explaining the same, and FIGS. 3 and 4 are diagrams for explaining a conventional technique. (1) is a full addition circuit, (2) to (5) are registers,
(6) is a carry addition circuit.

Claims (1)

(57) [Claims] 1. An accumulator for accumulating a plurality of values sequentially supplied, wherein said supplied value is inputted to a full adder circuit, and an addition output and a carry output of said full adder circuit are respectively outputted to a first adder circuit.
And to the second register, for the supplied value which is the current input, feeds back the outputs of the first and second registers which are the previous input to the full adder circuit to perform cumulative addition. An accumulator configured to input the addition output and the carry output to a carry addition circuit to obtain a cumulative addition output.