JPH04195423A - Multiplier - Google Patents

Abstract

PURPOSE:To speed up multiplying with an easy operation of only bit shift in a small-scale circuit by converting serial multiplicand data to parallel data and obtaining the product between this data and values in respective digits of parallel multiplier data and counting the number of products '1' and supplying the counted value to an adder and a latch. CONSTITUTION:Serial multiplicand data is converted to parallel data by a shift register 3. A gate group 6 outputs AND between parallel multiplier data and the parallel output of the shift register 3, and a counter 7 obtains a partial sum of multiplication based on the sum of outputs of this gate group. The value of 1/2 of the partial sum before one-bit shift and the present partial sum are added by an adder 8, and the least significant bit is outputted, and the other bits are stored in a storage circuit 9. This operation is continued until the most significant bit of multiplicand data passes the shift register, and thereby, the multiplication result synchronized with bit shift of multiplicand data is outputted with the least significant bit as the first bit. Thus, the operation is quickly performed in the small scale.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial input/serial output type binary multiplier.

[Prior art] A conventional multiplier is P3 of a detailed digital IC circuit (bottom).
As described in pages 04 to 311, ■ a method of adding the same number of multiplicands as the multiplicand Y, ■ a method of sequentially shifting and adding the products of the multiplicand There are known ways to achieve this. FIG. 2 is an actual example of a multiplication device based on the method (■), in which both the multiplicand X and the multiplier Y are 8 digits.
It is equipped with gates A, B, and C. The operation of a conventional multiplier will be explained with reference to FIG. Initially, the multiplier register 14 stores the multiplier Y, and the accumulator 12 is set to O. First, when the output from the right end of the multiplier register 14 that stores the multiplier Y is 1, each bit of the multiplicand register 13 is sequentially passed through the gate A to the adder circuit 1.
At the same time, each bit in the accumulator 12 corresponding to the sum in the middle of the calculation is also added to the adder circuit 1 through the gate 1-B.
Enter 5. The new sum in the middle of the calculation is simultaneously stored from the output J of the adder circuit 15 into the accumulator 12 during the calculation period.

All 8 bits of the contents of begins to shift inward. When the output from the right end of the multiplier register 14 is 0, the gate A is not conductive, and the contents of the multiplicand register 13 are not added to the adder circuit 15. When the addition of all the contents of the multiplier register 14 is completed in this way, the pre-calculation is completed, and the product obtained is stored in the accumulator 12 and the multiplier register 14.

[Problem to be solved by the invention]

The above-mentioned conventional techniques have the problem that methods (1) and (2) are slow in operation, and method (2) is large in scale, making them difficult to use, especially for fade processing and muting processing in digital audio.

The present invention aims to establish a multiplication method that is small-scale and capable of high-speed operation, and further aims to provide a multiplication device according to the method.

[Means for solving the problem] - A shift register that converts serial multiplicand data into parallel data in order to achieve a written record, and calculates the product of each digit of the parallel multiplier data and each pip of the shift register. The circuit is composed of a gate group, a counter that counts the number of items whose product becomes 1 due to the outputs of the gate group, an adder that adds up the outputs from the counter, and a latch.

[Operation] The shift register is first cleared to O, and the serial multiplicand data is input l bit by bit starting from the least significant bit and converted into parallel data.

The gate group outputs the AND of the parallel multiplier data and the parallel output of the shift register. The counter calculates the sum of the outputs of this group of gates. This count value becomes a partial sum in multiplication. The adder adds 1/2 of the partial sum before the 1-bit shift and the current partial sum, outputs the least significant bit, and stores the other bits in the storage circuit. The value stored in this storage circuit corresponds to the carry over of the partial sum, and is ready for addition with the partial sum after the next 1-bit shift.

By continuing the above two operations until the second most significant bit of the multiplicand data passes through the shift register, a multiplier result synchronized with the bit shift of the multiplicand data is output with the least significant bit at the beginning.

[Example] Hereinafter, an example of the present invention will be described with reference to FIG. 1st
The figure shows an example of a multiplication device that multiplies an M-bit multiplicand 2 and an N-bit multiplier 5 to obtain a result 10, including an N-bit shift register 3, a gate group 6, a counter 7, a K-bit adder 8, and (K-) ) It consists of a pit latch 9, a multiplicand input terminal 1, a multiplier horn terminal 4, and a multiplier output terminal 11. Here, M is an integer of 2 or more, N is an integer of 3 or more, and K is l
og.

It is a natural number satisfying N<K<N.

The operation of this multiplier will be explained below with reference to FIG. First, shift register 3 and latch 9 are cleared. The M-bit multiplicand 2 is input from the input terminal 1 to the N-bit shift register 3 as serial data at the head of 173B. The gate group 6 outputs N products of the N parallel outputs of the shift register 3 and the N-bit multiplier 5, which is parallel data. Furthermore, shift register 3
The parallel output horns and the parallel multiplier data 5 are first combined in such a direction that the product of the LSB of the multiplicand 2 and the LSB of the multiplier 5 is obtained. Counter 7 outputs the number of N outputs of gate group 6 that are l, and K
Initially, the LSB is sent to the bit adder 8, and since the shift register 3 and latch 9 are cleared, the LSB is output as it is (M+N) bit operation result serial data 10 to the multiplier output terminal 11, and the other (K- ]) bit is (K-1
) is sent to bit latch 9. Next, the 2nd bit of the multiplicand is input to the shift register 3, and the 2nd bit of the multiplicand is
is input to the adder 8. On the other hand, the previous carry is also input from the latch 9 to the adder 8, and the current number of 1s is added to the carry of the previous number of 1s, and the resultant L
SB is output as the second bit of the operation result 10, and the other bits (K-], ) are sent to the latch 9. The above operation is repeated until the MSB of the multiplicand 2 passes through the shift register 3. As a result, the multiplier output terminal 7 (M1N)
This means that the multiplication result is output as serial data 10 starting with the LSB of the bit.

The following describes how the circuit shown in FIG. 1 can perform multiplication. The multiplicand is X M-I YM-2...X,
X,, multiplier, YN-I YN-2...Y, Y
. Expressed as follows, in hand calculation, the product of the multiplicand X and the multiplier Y by 1 p[. On the other hand, Table 1 shows the output state of the gate group 6 in the circuit of FIG. 1 for each step. Comparing these, it is clear that performing vertical addition in Figure 3 is the same as performing horizontal addition in Table 1. That is, in the circuit of FIG. 1, the horizontal addition of Table 1 is performed by the counter 7, and the addition of digits is performed by the adder 8. Therefore, multiplication can be performed using the circuit shown in FIG.

By the way, if the present invention is not adopted and the gate group 6 and counter 7 are not used, an (M+N) bit adder and
Multiplication is possible by employing a (M+N) pit latch. However, in this case the circuit is large and a high speed adder is required.

In the present invention, the number of bits of the adder 8 is log, N (K
Since it is sufficient to satisfy the following, it becomes smaller than M and N, and the circuit can be made small. Therefore, according to the present invention, multiplication can be performed using a simple bit shift operation in a tJz scale circuit.

Table 1 Figure 4 shows an example of a multiplication device that outputs 16-bit data 25, which is the result of multiplying an 8-bit multiplicand 17 and an 8-bit multiplier 20, and a shift register 18. ．． Kate group 21. Counter 3j422.4 bit adder 23. :3-bit latch 24, multiplicand input terminal 16
．． Multiplier input terminal +9. It is constituted by a multiplier output terminal 26. In the figure, 52 is an 8NIT) line.

Here, a specific example will be shown when the multiplicand is 8 bits and the multiplier is 8 bits. The protrusions of the gate group 21 in FIG. 4 are shown in Table 2. Initially, the contents of shift register 18 are O
, and the LSB of the multiplicand 17 is input at 1 step 1. The output of the gate group 21 at that time is as shown in step 1 of Table 2. Each time one bit of the multiplicand data is input or shifted, the output of the gate group 21 sequentially changes to the one described in the next step. In the multiplication by hand calculation shown in Figure 5,
In Table 2, the operation of adding in the same vertical direction of the digits corresponds to the operation of adding the outputs at each step. Therefore, the multiplier output 26 in FIG.
The multiplication result is output as B first serial data.

Note that the reason why the adder 23 is 4 bits and the latch 24 is 3 bits is because a minimum of 4 digits is required in binary to represent a value from O to 8, and the minimum number of digits is used. teeth,
This is to downsize the circuit. Expressing this as a formula, l
og, 8 (This is the smallest natural number that satisfies K.

Table 2 Multiplicand 10110101 Multiplier 1001.1011 The 6th r1 is a 16-bit multiplicand 28 and a 16-bit multiplier 3
This is an example of a multiplication device that performs multiplication by 1, and includes a 16-bit shift register 29, a gate group 32, and a count 'A:+:33.
．． 5 bits 1 to adder 34.4 bit latch 35, multiplicand input terminal 272 multiplier input terminal 30, multiplier output terminal 37
It is made up of. Here, the number of bits of the adder 34, 5, is determined from the smallest natural number K that satisfies log, I (i). The product of each bit of the 16 parallel outputs and the multiplier 31, which is 16-bit parallel data, is output from the gate group 32. Among the outputs, 1
The counter 33 outputs the number of 5 bits, the adder 34 adds it to the 4 bits of the previous carry output from the latch 35, and the resulting LSB is multiplied and output]
] The other 4 bits are output to the latch 35 at the terminal 37.

By repeating this sequentially, a 32-bit multiplication result is outputted to the multiplier output terminal 37 as the LSB first serial data 36. By the way, as a counter for the number of ], 1. (There are two types of counters: one based on OM and one based on gates. An example of a counter based on gates and having four inputs is shown in FIG. 9, and is equipped with an input terminal 53 and an output terminal 55. Reference numeral 54 in the figure is a FOR gate.With this circuit, the number of 1s among the signals input to the input terminal 53 is obtained at the output terminal 55 as a 3-bit binary number.

FIG. 7 shows an example in which the present invention is adopted in a digital audio signal processing circuit, in which a RAM 38° interpolation circuit 39
1 multiplier, 16. D/A converter 47° multiplier control circuit 45
．． Mute signal input terminal 41° ATT signal input terminal 43
．． It consists of an analog audio output terminal 49, and the multiplier 46 is similar to the multiplier circuit of FIG.

The digital audio data output from the RAM 38 is subjected to processing such as interpolation in an interpolation circuit 39, and then input to a multiplier 46 as LSB leading serial data 40. On the other hand, mute and attenuate signals are sent to terminal 41 or terminal 43.
are input to the multiplier control circuit 45, and a multiplier corresponding to these processes (an 8-bit multiplier is shown in FIG. 7) is input to the multiplier 46. The multiplication result 47 is D
/Δ converter 48 converts it into an analog signal 49 and sends it to output terminal 50. Also, inside the multiplier 46, the LSB leading serial data 40 is input to the shift register 18, and the logical product of the parallel output and the parallel multiplier 20 is obtained by the gate group 21, as described above. Then, the calculator 22 converts the resulting number of 1 into a numerical value, and the adder 23 and latch 24 add the numerical values, and the multiplication result 47 is L
Output as SI3 first serial data. multiplier 2
Since 0 is 8 bits, if the 9th bit from the bottom of the multiplication result 47 is set as LSB and the bits beyond that are used as data, multiplication by a multiplier less than 1 is performed.
Processing such as fade, mute, and attenuation is possible.

FIG. 8 shows how the audio signal changes due to fade and mute processing. The audio signal 51, which was normal data in area a, has already faded in area a.
-, mute processing is performed in area C, fade-in processing is performed in area d, and the data returns to normal data again in area e.

Although not specifically shown in the figure, it is also possible to input a digital video signal as the multiplicand. In this case, fade-outs that increase the brightness of the screen, fade-outs that lower the brightness of the screen, bin spots, blurring by lowering the peripheral brightness, and monochrome are some examples that may be possible depending on the circuit configuration.

[Effects of the Invention] According to the present invention, multiplication can be performed at high speed with a simple operation of bit shifting using a small-scale circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multiplication device according to the present invention, FIG. 2 is a diagram showing a multiplication device based on a conventional method, and FIG. Figure 4 is a block diagram of a multiplication device that performs 8-bit x 8-bit multiplication. Figure 5 is a diagram of the procedure when 8-bit x 8-bit operations are performed by hand. 6
The figure is a block diagram of a multiplication device that performs 16-bit x 16-bit operations, Figure 7 is a diagram of an example of incorporating the present invention into a digital audio signal processing circuit, and Figure 8 is a diagram of analog data processed by fade-out and fade-in processing. FIG. 9 is a diagram showing an example of a counter composed of gates. 3...Shift register, 6...Gate group, 7...Counter, 8...Adder, 9...Latch circuit, 1...
Multiplicand input terminal, 4... Multiplier input terminal, 11... Multiplier output terminal.

Claims (4)

[Claims] 1. A shift register which is a multiplier that multiplies a multiplicand expressed in a binary number by a multiplier expressed in a binary number and which receives the multiplicand data as a serial input, and a logical product of the output of the shift register and the multiplier data. A group of gates to output, a counter that calculates the sum of the outputs of the gate group, an adder that takes the output of the counter as one input, and a memory of the adder other than the least significant bit, and the stored value is 1. A multiplier comprising a storage circuit which serves as the other input of an adder, and outputs a multiplication result bit-serially starting from the least significant bit of the adder. 2. Claim 1, wherein the multiplier multiplies an M-bit (M is a natural number) multiplicand by an N-bit (N is a natural number) multiplier, and receives the multiplicand data as a serial input.
a bit shift register, a gate group that outputs N logical products of the output of the shift register and the N-bit multiplier data; a counter that calculates the sum of the outputs of the gate group; K bits as input (K is lo
(a natural number satisfying g_2N<K<N), and a (K-1) bit storage circuit that stores bits other than the least significant bit of the adder and uses the stored value as the other input of the adder. A multiplier characterized by: 3. 2. The multiplier according to claim 1, comprising a gate group that provides a positive logical product and a counter that counts the number of ones. 4. 2. The multiplier according to claim 1, comprising a gate group that provides a negative logical product and a counter that counts the number of zeros.