JPS6043744A - Division circuit - Google Patents

Abstract

PURPOSE:To obtain a division circuit which divides the binary digital data by ''3'' in a simple constitution. CONSTITUTION:A dividend having three bits is denoted by (a)-(c) in order from high-order bit is divided by 3 to obtain the quotient X of one bit together with the residue of two bits Y and Z in order from high-order bit. When bits (a)-(c) are supplied under such conditions, the bits X-Z are outputted from a logical circuit 1. Then the binary data of N bits is supplied to the circuit 1 by one bit from the most significant bit in the form of the least significant bit (c) of the dividend. The outputs X of this time point are extracted successively as the quotient. At the same time, the outputs Y and Z are fed back to the input side of the circuit 1 in the form of bits (a) and (b) of the next dividend respectively. This action is repeated until the least significant bit of the binary, data of N bits is supplied. Thus both the quotient and the residue are obtained.

Description

[Detailed description of the invention] B. Industrial application fields This invention relates to a division circuit for binary digital data.

1. Background of the invention Recently, audio signals (analog signals) are sampled, pulse code modulated, and recorded, and when played back, gD-A
A recording/playback device using a pulse code modulation method has been proposed, which uses a converter to restore the original audio signal. In this case, if a coding error (for some reason) occurs during recording and reproduction of digital data, the original digital data cannot be reproduced correctly. In this case, in place of the data that was not correctly reproduced, the average value of the data before and after it is interpolated. For example, in FIG. 1, if data (dn-2) and data (dn++) are correctly reproduced, but data (dn-+) and data (dn) are not correctly reproduced, then t/, ( 2dn-2+dn+t)
The data (dn-1) is replaced by JIK, and '15 (dn
−2+Zdn+1) is interpolated in place of the data (dn). Therefore, a circuit that divides digital data by 3 is required. However, it has generally been difficult to construct a circuit that divides binary digital data by three.

Object of the Invention The present invention provides a circuit for dividing binary digital data by 6.
This is intended to be realized with a simple configuration.

two. Structure of the invention Let the 3-bit dividend be the upper bits ')'s bsC, let the 1-bit quotient when the dividend is divided by 3 be X, and let the 2-bit remainder be the upper bits Y12, When aN bl C is input, configures a logic circuit that outputs x, y, and z, outputs N bits of binary data from the most significant bit, and outputs Y as the a bit of the next dividend. is returned to the input side of the logic circuit as the b bit of the next dividend, and the above operation is repeated until the least significant bit of the N-bit binary data is input, thereby calculating the selective quotient and the remainder. It is structured as follows.

E. Embodiment A case in which 5-bit binary data (10110) is divided by 3 will be explained as an example. The appearance of this calculation is shown in Table 1 below.

Table 1 (MSB) (LSB) MSB indicates the most significant bit, and LSB indicates the least significant bit. Also, the underline indicates the remainder.

(Table 1), to perform division, divide the MSB bit by bit, and if a remainder occurs, carry it, add it to the next bit, and then perform the next division. If you do, you'll know what's good.

Now, when binary data is divided by 3, the basic operation is for six types of dividends represented by 6 bits as shown in Table 2 below.

Table 2 In Table 2, among the dividends, (110) and (111
) is not shown, but this is because no remainder is generated in the division process of (011) (it is just divisible), (110)
This is because the situation where calculations of (111) and (111) are performed does not occur.

Now, in Table 2, let the dividend (3 bits) be alb, c from the most significant bits, the quotient (1 bit) be X, and the remainder (2 bits) be Y, Z from the most significant bits, that is, (2Xa+2xb+e) If ÷3=X+(2xY+Z), then X, Y, and Z are the numbers that make up the dividend.
), it can be expressed, for example, by the following logical formula.

X -a + b x c Song... (1) As explained above) It is clear that binary data consisting of N bits is 3
To divide by , create a logic circuit that outputs x, y, and z that satisfy the relationships of equations (1), (2), and (3) above for six human forces (a, b, c), and calculate the dividend. MSB
Apply one bit at a time to this logic circuit, take out the quotient) one by one, and if a remainder (y, z) is generated,
It turns out that it is sufficient to repeat the operation of carrying this and returning it to the input side of the logic circuit.

FIG. 2 shows a division circuit having the above-described logic circuit (1), and the calculation process will be explained in more detail with reference to this figure.

Logic circuit (1) has three input terminals (x1tx2.I3)
and three output terminals (01, 02, 03). The input terminal (I3) is the lowest bit of the dividend (3 bits) (
(The input terminal (I2) is the middle bit 0.
), the input terminal (11) is the topmost pin)
(jL) becomes the input terminal.

The two-manpower of AND gate (2) is (b%), the -manpower of OR gate (3) is the output of this AND gate (2), and the other input is a. That is, AND gate (2) and OR gate (3) also realize the logical formula on the right side of equation (1) above, so the output of OR gate (3) is X (quotient). At the end (01), the quotient X is output.

Similarly, inverter [4] and AND gate (57
Since the inverter (6) and the AND gate (7) realize the second term, the output of the OR gate (8) becomes the upper bit (1) of the remainder. ing. This Y is taken out from the output terminal (o2) and passed through the slip/70 knob to the most significant bit (a
) is input to the input terminal (I1).

Inverter (9), inverter (4), and the AND gate are the first term on the right side of the third equation, and inverter 16)
Since the AND gate αυ realizes the second term, the output of the OR gate 12 is the lower bit of the remainder. This 2 is taken out from the end (o3) and slips.
7 units (middle bit 0 of the next dividend via 211)
The signal is input to the input terminal (I2) as follows.

Now, a clear input is applied to the flip-flop (21 (21)), and its output Q is both 0 and is input to the input terminals (It, 12).In each state, 5-bit data is (1011o) oMSB11# is the input terminal (
I3). That is, in the first division, the dividend (abc) is ``oo1'', so (xyz) is outputted from the output terminals (01, 02, 0!1).

The quotient QQ1o" is taken into the shift register @ in synchronization with the clock, and the remainder 11" is taken into the flip-flop (2B). Therefore, 10 is input to the input terminal (11). (I2) contains the carried remainder, ``dove 1'', and (13) contains the second significant bit 1o of the data.
” is input. That is, in the next division, the dividend is 'oio“.
It is done as.

Below, the same operation is performed on the LSB-Q of data (voiio).
" is input to the input terminal (I3). At this time, the shift register has data (1011
The quotient "00111' when dividing 0) by 6 is taken in, and the remainder 11o# is obtained from the output terminal (yz).

The logical expressions expressing (xyz) using (abc) are not limited to the above-mentioned expressions (1), (2), and (3). For example, the following formula may be used.

X = a x b + b x c +e++++
(4) y=(b■c) x (a + b) ---
---(5) z=(b■c) x c + a x
c-.-(6) Note that ■ is an exclusive OR.

Logic circuit (1) that realizes the above logical formula + 4) (5J (6)
)' to No. 6 1. Effects of the Invention The present invention performs division by configuring a logic circuit that outputs a quotient (g) and a remainder (yz) when a dividend (abc) is input. , the division circuit can be realized with a relatively simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining data interpolation, FIG. 2 is a diagram showing one embodiment of the present invention, and FIG. 3 is a diagram showing another embodiment. 111 (1/ is a logic circuit.

Claims (1)

[Claims] (1) A division circuit that divides binary data of N bits by 3 and calculates the quotient and remainder, and sets the 3-bit dividend to the upper bits pa, b, and e, and divides this dividend by 3. Let the 1-bit quotient be X, and the 2-bit remainder be the upper bit! It has a logic circuit that outputs the x, y, and z when the a, b, and c are input when IY, Z,
The N-bit binary data is input to the logic circuit as the most significant bit (from the most significant bit to the least significant bit of the dividend) (C), and the output bit, and the output 2 is fed back to the input side of the logic circuit as the b bit of the next dividend, and the above operation is repeated until the least significant bit of the N-bit binary data is input. , a quotient, and a remainder.