JPS62184534A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To shorten the arithmetic time by calculating high and low order bits concurrently, performing the arithmetic operation with respect to the presence/absence of carry from the low order bit and selecting the result of the high order bit arithmetic operation according to the carry of the low order bit. CONSTITUTION:Illustration is an embodiment applying the invention to an arithmetic circuit of 16 bits. Bits 0-7, the low order eight bits, are calculated by a whole adder with the technique the same as a conventional one. In terms of the presence or absence of carry from the low order eight bits, 8-15 bits, the high order eight bits, are concurrently operated. After the carry of the low order eight bits is decided, one of arithmetic results of the high order eight bits is selectively outputted according to the decision. In the circuit complying the invention, the arithmetic time is a one obtained by adding the arithmetic time for eight bits to the time required for selective outputting. Namely, the arithmetic time is a little more than half in the arithmetic circuit with conventional technique. It is no wonder that not only vertically bisecting the multibit arithmetic but also its multidivision offers the same effect.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an expanded digital arithmetic circuit, and particularly to an arithmetic circuit that performs high-speed multi-bit addition and subtraction.

[Conventional technology]

Conventionally, multi-bit addition/subtraction arithmetic circuits have been configured with full adders connected in series. The operation and configuration will be described below with reference to the drawings.

The truth table of the full adder is shown in Table 1. FIG. 3 is an example of a full adder. The part within the broken line in the figure is a half adder. FIG. 3 is an example of expression using logic symbols, but it is well known that when realized with a transistor circuit, for example, when using a MO8 transistor, the logic circuit is rewritten as shown in FIG.

Table 1 Now, for example, when performing 16-bit addition, the full adders shown in FIGS. 3 and 4 are connected in series as shown in FIG. 5 to perform the calculation. Inputs to each bit Ai and Bi are input to the full adder at the same time, the least significant bit (0th bit)
Otherwise, the sum (Sum) and carry signal (Cou
t) will be calculated. Therefore, in the case of the full adder shown in Fig. 4, the time required to calculate the upper bits is
This corresponds to a delay of two stages of NOR or NAND gates.

Furthermore, the least significant bit requires a delay time equivalent to four stages of gates.

FIG. 6 shows another full adder circuit in NMO8. In this circuit, A-Bi'+A, B (exclusive OR of A and B)
(transmission game) TR opens and transmits the carry signal from the lower bits to the upper bits. On the other hand, person-B (A, B
In the case of AND), a high level "1" is generated and transmitted to the next stage, and in the case of A+B (NOR of A and B), a low level "0" is generated and transmitted to the next stage. Therefore, the calculation time is maximum when the transmission gate is open for all bits and the carry signal from the least significant bit is transmitted at the most significant bit (1). The calculation time in this case corresponds to the delay required for the carry signal to pass through the transmission gate (and the sum of the time required to generate the exclusive OR of A and H), but generally it is shown in Fig. 4. It has a smaller delay than the one shown and is often used. However, in both cases of FIG. 4 and FIG. 6, the propagation time of the carry signal from the least significant bit to the most significant bit determines the calculation time. That is, the calculation time is proportional to the number of bits or approximately proportional to the square of the number of bits. (It is well known that the delay time of an n-stage transmission gate is roughly proportional to n8.) [Problem to be solved by the invention] In the above-mentioned conventional multi-bit arithmetic circuit, the carry signal starts from the least significant bit. Since the propagation is carried out sequentially and the operation result and carry are determined starting from the lower bit, there is a drawback that the operation takes a long time.

[Means for solving problems]

The arithmetic circuit of the present invention performs the upper multiple bit operations in parallel for both the presence and absence of carry from the lower multiple bits to the upper multiple bits during the same period as the lower multiple bit operations, and after the upper and lower multiple bit operations are completed. The result of the upper multiple bit operation is selected according to the presence or absence of a carry from the lower multiple bits.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment in which the present invention is applied to a 16-bit arithmetic circuit. The operation of the lower 8 bits from 0 to 7 bits uses the same full adder as in the prior art described above, but the operation for the upper 8 bits from 8 to 15 bits is performed in parallel depending on whether there is a carry from the lower 8 bits. After the carry of the lower 8 bits is confirmed, one of the operation results of the upper 8 bits is selectively outputted accordingly.

The arithmetic circuit for each upper bit is shown in FIG. 2(a) or (b). FIG. 2(a) is an example of an enlarged NMO8 circuit, and corresponds to the prior art example shown in FIG. 6, and FIG. 2(Φ) corresponds to FIG. 4. In the circuit according to the present invention, the calculation time is the calculation time for 8 bits plus the time required for selective output. In other words, the calculation time is just over half that of the calculation circuit according to the prior art.

Although this example has been shown with respect to a general full adder or an NMO8 Manchester full adder, it is clear that it can also be applied to a 0M08 circuit. It is also clear that the same effect can be obtained not only by dividing the multi-bit operation into upper and lower parts, but also by dividing it into multiple parts.

〔Effect of the invention〕

As explained above, in the present invention, in multi-bit addition/subtraction, the upper bits and lower bits are operated in parallel, and the operation is performed for both the presence and absence of carry from the lower bits, and after the upper and lower bits are completed, the lower bits are Since the carry selects the result of the upper bit operation according to the result, it has the effect of significantly shortening the operation time compared to the conventional technique in which the operation is carried out from the lower to the upper.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2(a) is a full adder circuit diagram of the upper bit part in FIG.
) is a full adder block diagram of another configuration example of the upper bit part of FIG. 1, FIG. 3 is a full adder logic circuit diagram, FIG. 4 is a full adder circuit diagram in the case of transistor configuration, and FIG. 5 is a block diagram of a multi-bit arithmetic circuit in the prior art, and FIG.
It is a transistor circuit diagram of the full adder in MO8. Bowl St St 1,000 figures (b)

Claims (1)

[Claims] During the same period as the lower multiple bit operation, perform upper multiple bit operations in parallel for both whether or not there is a carry from the lower multiple bits, and after the operation of the upper and lower multiple bits is completed, depending on whether there is a carry from the lower multiple bits. An arithmetic circuit characterized in that it is configured to select an upper multiple bit arithmetic result.