JPH11353156A - Carry signal generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an adder fast by shortening the total carry signal generation time including precedent and trailing stages as to a precedent-stage circuit and a trailing-stage circuit which constitute the carry signal generating circuit by precedently processing part of logical operation of the trailing-stage circuit by the precedent-stage circuit. SOLUTION: When carry signals for 4-bit binary data a0 a1 a2 a3 and binary data b0 b1 b2 b3 are generated, a signal p0 represented as p0 =a0 +b0 , a signal Hi ,i+1 represented as Hi ,i+1 =ai .bi +ai+1 (i=0, 2), and a signal I1.2 represented as I1 ,2 =(a1 +b1 ).(a2 +b2 ) are generated. Their signal processings can be carried out in parallel. Then those signals p0 , Hi ,i+1 , and I1 ,2 are used to generate a 4-bit carry signal C<4bit> represented as C<4bit> =p0 .(H0 ,1 +I1 ,2 +H2 ,3 ). Consequently, the number of NMOS transistors which are stacked and connected longitudinally is decreased to shorten the circuit operation time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit for performing carry look-ahead of a data signal adder, and more particularly to a CMOS logic circuit suitable for speeding up the generation of a carry signal.

[0002]

2. Description of the Related Art An adder is one of the most basic components among logic circuits used in information processing devices such as a microprocessor and a digital signal processor. In many cases, the adder determines the operation speed of the information processing device, and therefore, it is strongly required to increase the operation speed.

The signal processing speed of a multi-bit adder greatly depends on the time for generating a carry signal, and the carry signal generation circuit is an important controlling factor for determining the processing speed of the entire adder. For this reason, techniques for increasing the speed of the carry signal generation circuit have been conventionally studied.

[0004] Conventional techniques for increasing the speed of the carry signal generation circuit include N.E.E.WESTE and K.E.S.R. Co., pp. 526-531, 1993 (NHE Westeand
K. Eshraghian, Principles of CMOS VLSI Design-AS
ystems Perspective, second edition, Addison-Wesle
y, pp. 526-531, 1993), there is a CMOS logic circuit using a dynamic circuit (domino circuit). Domino logic circuits are generally widely known as high-speed circuit technology.

[0005] the above-described conventional art, when adding a binary 4-bit data _{a 0 a 1 a 2 a 3} b 0 b 1 b 2 b 3, first, a Boolean equation (1) below formula (2) As shown in (1), the generation signal g _j is generated from the logical product of the j-th bit data a _j and b _j , and the propagation signal p _j is generated from the logical sum of a _j and b _j . Next, as shown in Expression (3), a 4-bit carry signal C ^4bit is generated using the generated signal g _j and the propagation signal p _j .

G _j = a _j · b _j (j = 0,1,2,3) (1) p _j = a _j + b _j (j = 0,1,2,3) (2) C ^4bit _{= g 0 + p 0 g 1} + p 0 p 1 g 2 + p 0 p 1 p 2 g 3 = g 0 + p 0 · (g 1 + p 1 · (g 2 + p 2 · g 3)) ... (3) prior art ^{Speeding up} is ^achieved by generating these signals g _j , p _j , and C ^{4 bits} using a domino logic circuit.

FIG. 9 shows a domino circuit for generating a generation signal g _j , FIG. 10 shows a domino circuit for generating a propagation signal p _j , and FIG.
^{Reference numeral} 1 denotes a domino circuit that generates a carry signal C ^{4 bits} .

In FIG. 9, reference numeral 301 denotes a clock signal CK.
, A precharging PMOS transistor 304
Is a CMOS inverter. NMOS transistor 3
Data a _j and b _j are input to 02 and 303. When the clock signal CK has a logical value of 1, a generation signal g _j that is a logical product of the data a _j and b _j is output via the inverter 304. For example, when both a _j and b _j have a logical value of 1, the transistors 301 and 302 conduct, the input of the inverter 304 has a logical value of 0, and the carry generation signal g _j has a logical value of 1. Become.

In the propagation signal generation circuit of FIG. 10, 311 is a precharge PMOS to which a clock signal CK is input.
The transistor 314 is a CMOS inverter. NM
Data a _j and b _j are input to the OS transistors 312 and 313. When the clock signal CK has the logical value 1,
Propagation signal p _j, which is the logical sum of data a _j and b _j , is output via inverter 314.

In the 4-bit carry signal generating circuit shown in FIG. 11, a generated signal g generated by the circuits shown in FIGS.
_{0 to} g ₃ and the propagation signals p _{0 to} p ₃ are input to the corresponding transistors 323 to 328, respectively. When the clock signal CK input to the PMOS transistor 321 for precharge has a logical value of 1, the logical operation represented by the above equation (3) is executed, and the carry signal C as a result is obtained.
^{4 bits} are output from the inverter 329.

[0011]

In the above-mentioned prior art, the signal processing time until the 4-bit carry signal C ^{4 bit} is generated from the data a _j and b _j is determined by the NMOS transistors 302 and 303 and the inverter shown in FIG. 304 operating time;
The NMOS transistors 322, 324, 32 of FIG.
6, 328 and the operation time of the inverter 329. That is, the signal processing speed is reduced by NMOS connected in vertical stack.
It is governed by the operating time of 2 + 4 transistors and 2 inverters.

A main object of the present invention is to further speed up a carry signal generation circuit. The logical aim is to reduce the number of NMOS transistors connected in cascade compared to the prior art and to shorten the circuit operation time.

[0013]

According to a first aspect of the present invention, a four-bit binary data a is provided.
₀ a ₁ a ₂ a ₃ a Taking as an example the case of generating the carry signal of the binary data _{b 0 b 1 b 2 b 3} , first with Formula signal p ₀ the formula represented by (4) (5) The expressed signals _Hi , _{i + 1} and equation (6)
To generate a signal I _1,2 represented by Next, a 4-bit carry signal C ^4bit represented by equation (7) is generated using these signals p ₀ , _{Hi, i + 1} , and I _1,2 .

P ₀ = a ₀ + b ₀ (4) _Hi , _{i + 1} = a _i · b _i + a _{i + 1} · b _{i + 1} (i = 0, 2) (5) I _1,2 = (A ₁ + b ₁ ) · (a ₂ + b ₂ ) (6) C ^4bit = p ₀ (H _0,1 + I _1,2 · H _2,3 ) (7) Equations (4) to ( When 7) is configured by a domino logic circuit,
Equation (4) shows that one vertically stacked NMOS transistor and one inverter
Circuits, Equations (5) and (6) are vertically stacked transistors 2
Equation (7) is composed of three vertically stacked transistors and one inverter. Since the signal processing of Expressions (4) to (6) can be performed in parallel, the signal processing time required to generate the carry signal C ^{4 bits} from the data a _j and b _j is the processing of Expression (5) or Expression (6). It depends on the time and the processing time of equation (7). Accordingly, time for generating the carry signal C ^4bit the string-effect NMOS transistor 2+
It is determined by the operation time of three inverters and two inverters, and the number of vertically stacked transistors can be reduced by one as compared with the prior art.

According to the second means of the present invention, data a ₀ a ₁
a ₂ a ₃ and inverted signal of b ₀ b ₁ b ₂ b ₃ a ₀ B a ₁ B a ₂
First, using Ba ₃ B and b ₀ B b ₁ B b ₂ B b ₃ B, the signal p ₀ B represented by the equation (8) and the signal _{Hi, i + 1} represented by the equation (9) are used. B and a signal I _1,2 B represented by equation (10). Next, these signals p ₀ B, H _{i, i + 1} B, I _1,2
Using B, an inverted signal C ^4bit B of a 4-bit carry signal represented by the equation (11) is generated.

P ₀ B = a ₀ B · b ₀ B (8) _Hi , _{i + 1} B = (a _i B + b _i B) · (a _{i + 1} B + b _{i + 1} B) (i = 0, 2) (9) I _1,2 B = a ₁ B · b ₁ B + a ₂ B · b ₂ B (10) C ^4bit B = p ₀ B + H _0,1 B · (I _1,2 B + H _2,3 B) ... (11) When Expressions (8) to (11) are configured by domino logic circuits, Expressions (8) to (11) are all circuits in which the number of vertically stacked NMOS transistors is two and the inverter is one. become. Therefore, the inverted signal C of the carry signal is obtained from the data a _j and b _j.
Signal processing time required to generate a ^4bit B is determined by the string-effect transistor 2 + 2 and two inverters operating time,
Compared to the first means, the number of vertically stacked transistors can be further reduced by one.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of a 4-bit carry signal generation circuit according to the present invention will be described with reference to FIGS. 1 to 4 show domino circuits that perform logical operations corresponding to the equations (4) to (7), respectively.

FIG. 1 shows a circuit for generating a logical sum of data a ₀ and b ₀ of the 0th bit from the upper bit of 4-bit binary data, that is, a propagation signal p ₀ . This circuit includes a PMOS transistor 101 to the clock signal CK is input, the NMOS transistor 102 to the data a ₀ is input, the NMOS transistor 103 to the data b ₀ is input, C
It comprises a MOS inverter 104. PMOS
The upper node of transistor 101 is connected to the power supply, and the lower nodes of NMOS transistors 102 and 103 are connected to ground.

When the clock signal CK has a logical value of 0, the domino circuit is in a precharge period. During this period, a ₀ and b
The logical operation of ₀ is not performed, and the output of the inverter 104 becomes the logical value 0. When CK becomes a logical value 1, the domino circuit enters an evaluation period, and a corresponding to equation (4)
The logical sum of ₀ and b ₀ is calculated. When one of the data a ₀ and b ₀ has a logical value of 1, the input signal of the inverter 104 has a logical value of 0, and the output signal, that is, the propagation signal p ₀ has a logical value of 1. The signal processing time of this circuit is the sum of the time during which the charge of the dynamic node (node between PMOS and NMOS) is pulled out by the transistor 102 or 103 and the time during which the signal transition of the dynamic node is output via the inverter 104. become.

FIG. 2 shows the _i - _th bit ( _i.
= 0 or generates a logical product i.e. generation signal g _i of the data a _i and b _i 2), the logical product i.e. generation signal g _{i + 1} of the data a _{i + 1} and b _{i + 1} of the i + 1 th bit Generate g _i
A circuit for generating a g _{i + 1} of the logical OR signal H _i, a i _{+ 1.}
A precharging PMOS transistor 111, and NMOS transistors 112, 113, 114, and 115 of data a _i, b _i, is _{a i + 1, b i +} 1 is input, the inverter 1
16.

When the clock signal CK becomes the logical value 1 and the domino circuit enters the evaluation period, the logical sum operation of the generated signal g _i and the generated signal g _{i + 1} corresponding to the equation (5) is performed. The operating speed of this circuit is determined by the pair of NMOS transistors 112 and 113 vertically connected in series or 114
And 115 are determined by the time for discharging the dynamic node and the time for the inverter 116 to switch.

FIG. 3 shows a logical sum of data a ₁ and b ₁ of the first bit from the upper four bits, ie, a propagation signal p ₁ , and a logical sum of data a ₂ and b ₂ of the second bit, ie, a propagation signal It generates p _2, is a circuit that generates a logical product signal I _{1, 2} of p ₁ and p _2. A precharging PMOS transistor 121, NMOS transistors 122, 123, 124 and 125 of data _{a 1, b 1, a 2} , b 2 are input
And an inverter 126.

When this circuit enters the evaluation period, the AND signal I _1,2 corresponding to the equation (6) is output. During the precharge period, the signal I _1,2 has a logical value 0. NMOS transistor 1 during the evaluation period
When at least one of 22 and 123 and at least one of 124 and 125 are turned on, the logical value of the signal I _1,2 switches from 0 to 1. The signal processing time is 2 vertical
It is determined by the sum of the time during which the NMOS transistors that are simultaneously turned on discharge the dynamic node and the time during which the inverter 126 operates.

FIG. 4 shows the propagation signal p ₀ output from FIG.
And the signals H _0,1 , H _2,3 output from FIG. ₂ and the signals I _1,2 output from FIG. 3, perform a logical operation corresponding to equation (7), and carry four bits. This is a circuit for generating a signal C ^4bit . The logical product of the signal I _1,2 and the signal H _2,3 is taken, the logical product of this signal and the signal H _0,1 is taken, and the logical product of this logical sum and the propagation signal p ₀ is taken. Signal C ^4bit
Generate This circuit includes a PMOS transistor 131 for precharge and NMOS transistors 132, 133, and 13 to which signals p ₀ , H _0,1 , H _2,3 , and I _1,2 are inputted.
4, 135 and an inverter 136.

During the evaluation period, the time during which the carry signal C ^{4 bit} is generated by the circuit of FIG. 4 is determined by the three vertically arranged NMOS transistors 132, 133 and 13.
4 time to discharge the dynamic node,
It depends on the sum of the time when the inverter 136 operates.

Although the circuit operations of FIGS. 1 to 4 have been individually described above, the signal processing time until the 4-bit carry signal C ^4bit is generated from the data a _j and b _j will be described in the preceding figure. 1 to 3 and the subsequent circuit operation time of FIG. 4. Comparing the operation speeds of the circuits of FIGS. 1 to 3 at the preceding stage, as described above, the circuit of FIG. 1 has one vertically stacked NMOS transistor, and the circuits of FIGS. Is two, so
2 or 3 operates slower than the circuit of FIG. Therefore, the overall carry signal generation time of the first embodiment is determined by one of the circuits in FIG. 2 or 3 and the operation time of the circuit in FIG. That is, the carry signal C ^4bit
Is the sum of the operation time of the vertically stacked NMOS transistors 2 + 3 and the operation time of the two inverters.

Comparing the circuit configuration of the first embodiment of the present invention with the circuit configuration of the conventional example, the conventional example generates the generation signal g _j and the propagation signal p _j by the circuit of FIG. 9 and FIG. and generating a carry signal C ^4bit from the signal g _j and p _j in circuit 11. On the other hand, in the present embodiment, a logical product or a logical sum of the generated signal g _j and the propagated signal p _j is calculated in advance by the circuits of FIG. 2 and FIG. Signal C
^4bit is generated. In other words, in the present embodiment, a part of the logical operation shown in FIG. 11 at the latter stage of the conventional example is advanced by the circuits shown in FIGS. 2 and 3 at the former stage. As a result, in the first embodiment, the number of the NMOS transistors in the post-stage circuit is reduced from the conventional four to three in the post-stage circuit as compared with the conventional example.
We were able to reduce to pieces.

2 and 3 of the present embodiment is more complicated than the prior-art circuit of FIG. 9 of the prior art.
Since the number of S transistors is maintained at the same two, there is no significant difference between the circuit operation time of FIG. 9 and the circuit operation time of FIG. 2 or FIG. Therefore, comparing the total carry signal generation time of the former stage and the latter stage, the present embodiment can be shortened by about 15% as compared with the conventional example, and the speeding up of the adder can be realized.

The reduction in the number of vertically stacked transistors according to the present invention, that is, the reduction in logical operation processing, is essentially effective for speeding up a logic circuit regardless of the circuit system. In the first embodiment, a general CMOS domino circuit is employed as a high-speed CMOS circuit. However, it is apparent that the present invention is also effective in static CMOS circuits, BiCMOS circuits, and bipolar ECL circuits.

Also, in this embodiment, a 4-bit carry signal generation circuit has been described as an example, but it is needless to say that the present invention can be applied to a multi-bit carry signal generation circuit. n
When extending to a carry signal generation circuit of bits (n is an integer of 4 or more), binary data a ₀ a ₁ a ₂ a ₃ ... _An and b according to the equations (5) and (6) ₀ b ₁ b ₂ b ₃ ... B _n , the signals _Hi , _{i + 1} shown in equation (12) and the signal I shown in equation (13)
_It is sufficient to generate _{k and k + 1} , perform a logical operation according to equation (7) using these signals, and generate a carry signal C ^nbit .

H _{i, i + 1} = a _i · b _i + a _{i + 1} · b _{i + 1} (i = 0,2,..., N−2) (12) I _{k, k + 1} = (a _k + b _k ) · (a _{k + 1} + b _{k + 1} ) (k = 1, 3,..., n−3) (13) Next, the second of the 4-bit carry signal generation circuit according to the present invention.
Will be described with reference to FIGS. 5 to 8
Each shows a domino circuit that performs a logical operation corresponding to Expressions (8) to (11). In the second embodiment, binary data a ₀ for 4 bits, as in the first embodiment a ₁ a ₂ a ₃ a b ₀ b ₁
Instead of performing the logical operation of b ₂ b ₃ as it is, inverted data signals a ₀ Ba ₁ Ba ₂ Ba ₃ B and b ₀ B b ₁ B b ₂
A logical operation of B b ₃ B is performed.

The circuit of FIG. 5 receives a ₀ B and b ₀ B to generate an inverted signal p ₀ B of the propagation signal p ₀ (inverted signal of the output of FIG. 1), and the circuit of FIG. 6 a ₀ B _{, b 0 B, a 2 B} , b 2 B receiving the signal H _{i, i + 1} of the inverted signal H _{i, i + 1} B circuit for generating an (inverted signal of the output of FIG. 2), the circuit of FIG. 7 Is a ₁ B, b
₁ B, a ₂ B, the inversion signal I _{1, 2} of the signal I _{1, 2} receives a b ₂ B
B (an inverted signal of the output of FIG. 3), and FIG. 8 shows the carry signal C in response to the signals p ₀ B, H _{i, i + 1} B, and I _1,2 B.
^This circuit generates a 4- ^bit inverted signal C ^4bit B (an inverted signal of the output in FIG. 4).

The circuits shown in FIG. 5 to FIG.
The precharge PMOS transistors 201, 211,
221, 231 and inverted signals a ₀ B, b ₀ B, a ₁ B, b ₁
B, a ₂ B, b ₂ B, p ₀ B, H _0,1 B, H _2,3 B, I _1,2 B
Are input to the NMOS transistors 202, 203, and 2
12 to 215, 222 to 225, 232 to 235, and inverters 204, 216, 226, and 236.

The circuit operation of FIG. 5 is the same as the circuit operation of FIG. 9 except that the input signal and the output signal are different, as is apparent from the drawing. Similarly, FIG. 6 performs the same circuit operation as FIG. 3 and FIG. 7 performs the same circuit operation as FIG.

In the circuit of FIG. 8, the signal p ₀ B from FIG. 5, the signals H _0,1 B, H _2,3 B from FIG. 6 and the signal I ₀ from FIG.
_1,2 B is input and the signal H _2,3 B
And the signal I _1,2 B, and the logical sum and the signal H _0,1
By taking the logical product of B and the logical sum of this logical product and the signal p ₀ B, an inverted signal C ^4bit B of the carry signal is generated. In the evaluation period, the circuit operation time in FIG. 8 is the time during which at least one of the NMOS transistors 234 and 235 and the NMOS transistor 232 discharges the dynamic node, and the time during which the inverter 2 operates.
36 is determined by the sum of the switching time. That is, FIG.
The number of vertically stacked NMOS transistors, which is a dominant factor in the circuit operation time, is two.

In this embodiment, the inverted data signal a _j
Inverted signal C ^4bit of carry signal of 4 bits from B and b _j B
The total signal processing time until B is generated is the sum of the circuit operation time of the preceding stage in FIGS. 5 to 7 and the circuit operation time of the subsequent stage in FIG. FIG. 6 or FIG.
Two vertically stacked transistors and determined by one inverter, the operating time of the subsequent circuit is determined by one of two vertically stacked transistors and the inverter of FIG. 8, the signal C ^4bit of
The total generation time of B is the vertically stacked NMOS transistor 2 + 2
And the operation time of the two inverters.
Therefore, the number of vertically stacked transistors in the present embodiment is reduced by two compared to the conventional example and by one compared to the first embodiment.

In this embodiment, by rearranging the positive logic of FIG. 4 of the first embodiment by inversion logic, the vertically connected NMOS transistors are rearranged horizontally and the number of vertically stacked transistors is reduced. Could be reduced. This example data a ₀ a ₁ a ₂ a ₃ a b ₀ b ₁ b ₂ b ₃ of the inverted signal _{a 0 B a 1 B a 2} B a 3 B and _{b 0 B b 1 B b 2} Bb
Requires a ₃ B, if these data inversion signal is previously generated at a portion other than the carry signal generation circuit of the adder, the data just before the preceding circuit shown in FIGS. 5 to 7 It is not necessary to add a new circuit for inversion. Also, Kume a logic circuit which receives the output C ^4bit B in the subsequent stage circuit shown in FIG. 8 with inverted logic, C ^4bit inverts the C ^4bit B
There is no need to provide a separate circuit for returning to. Therefore, the overall signal processing time of the carry signal generation circuit according to the second embodiment may be determined in consideration of the circuit operation time shown in FIGS. As a result, the processing time of this embodiment is reduced by about 25% as compared with the conventional example and by about 14% as compared with the first embodiment, and the speed of the adder is further increased as compared with the first embodiment. Can proceed.

Finally, a third embodiment of the 16-bit carry signal generation circuit according to the present invention will be described with reference to FIG. In this embodiment, a 16-bit carry signal generation circuit is configured based on the 4-bit carry signal generation circuit shown in the first embodiment. The carry signal is output every four bits in consideration of the balance with the logical configuration of the portion other than the carry signal generation of the adder.

In this embodiment, the logical operation corresponding to the equation (2), the equations (12) and (13) described at the end of the description of the first embodiment, and the following equations (14) to (20) are performed. I do.

C ^4bit _{i, i + 3} = p _i · (H _{i, i + 1} + I _{i + 1, i + 2} · H _{i + 2, i + 3} ) (i = 0,4,8,12) .. (14) P ^4bit _{j, j + 3} = p _j · I _{j + 1, j + 2} · p _{j + 3} (j = 0,4,8) (15) H ^8bit _{k, k + 4} = C ^4bit _{k, k + 3} + C ^4bit _{k + 4, k + 7} (k = 0,8) (16) I ^8bit _4,8 = P ^4bit _4,7 · P ^4bit _8,11 (17) C ^16bit _{0 ^{, 15 = P 4bit 0,3 · (}} H 8bit 0,4 + I 4bit 4,8 · H 8bit 8,12) ... (18) C 12bit 4,15 = C 4bit 4,7 + I 8bit 4,8 · H 8bit _8,12 ... (19) C ^8bit _8,15 = P ^4bit _8,11 · H ^8bit _8,12 ... (20) The 16-bit carry signal generation circuit shown in FIG. The logic block includes logic blocks 1101 to 1104 for generating carry signals, and a logic block 1201 for combining signals output from these logic blocks to generate a 16-bit carry signal.

The logical block 1101 stores data a ₀ a ₁ a ₂ a of the 0th bit to the 3rd bit of the 16 bits.
₃ and b ₀ b ₁ b ₂ b ₃ are input. Logical block 110
1 include domino circuits (similar to FIG. 2) for performing the operation of equation (12), and circuits 1003 and 1002.
005 is a circuit that performs the operation of Expression (2) (similar to FIG. 1), and a circuit 1004 is a circuit that performs the operation of Expression (13) (similar to FIG. 3)
It is. The circuit 1011 receives the output H _0,1 of the circuit 1001, the output H _{2,3 of the} circuit 1002, the output p _{0 of the} circuit 1003, and the output I _{1,2 of the} circuit 1004, and performs an operation of Expression (14). 4 bits carry signal C of 0th to 3rd bits
^This circuit outputs ^{4 bits} ₀ and ₃ (similar to FIG. 4). Circuit 1
012 receives the output p ₀ of the circuit 1003, the output I _{1,2 of the} circuit 1004, and the output p _{3 of the} circuit 1005, and calculates
This is a circuit that performs the operation of 5) and outputs the signal P ^4bit _0,3 (a circuit diagram is not shown, but a person skilled in the art can easily configure a domino circuit).

The circuit configuration of the logic blocks 1102 and 1103 is the same as that of the logic block 1101. Logic block 1102 receives data a ₄ 4-7 bit a ₅ a ₆ a ₇ a _{b 4 b 5 b 6 b 7} , the 4-bit carry signal C
^4bit _4,7 and the signal P ^4bit _4,7 are output. Logical block 11
03 is the data of the _{8th to} 11th bits a ₈ a ₉ a ₁₀ a ₁₁ and b
Receiving ₈ b ₉ b ₁₀ b _11, and outputs a carry signal C ^4bit _{8, 11} and the signal P ^4bit _{8, 11.} The circuit configuration of the logic block 1104 is as follows.
It is the same as that except for 012. Logical block 110
4 12-15 bit data a ₁₂ a ₁₃ a ₁₄ a ₁₅
And b ₁₂ b ₁₃ b ₁₄ b ₁₅ and carry signal C ^4bit
Outputs _12,15 .

The logic block 1201 includes circuits 1021 to 1
023 and circuits 1031 to 1033. Circuit 102
1 receives the signals C ^4bit _0,3 and C ^4bit _4,7 output from the logic blocks 1101 and 1102, performs a logical sum operation shown in Expression (16), and outputs a signal H ^8bit _0,4 . Circuit 1023
Similarly to the circuit 1021, the signals C ^4bit _8,11 and C ^4bit
_In response to the signal _12,15 , the signal H ^8bit _8,12 is output. Circuit 102
2 receives the signals P ^4bit _4,7 and P ^4bit _8,11 output from the logic blocks 1102 and 1103, performs the operation of the equation (17), and outputs the signal I ^8bit _4,8 .

The circuit 1031, the signal H ^8bit _{0, 4} output from the signal P ^4bit _{0, 3} and circuit 1021 to 1023 output from the circuit 1012, H ^8bit _8,12, receives the I ^8bit _{4, 8} 16 _This is a circuit for generating a carry signal C ^16bit _0,15 of the entire bit, and the circuit diagram is the same as that of FIG. Circuit 1032
The signal H ^8bit _8,12 outputted from the signal C ^4bit _{4, 7} and circuit 1022 output from the circuit 1102, I
^This circuit generates a carry signal ^{C12bit4,12 for} ₁₂ bits of the _4th to 15th bits in response to 8bit4,8. Circuit 10
33 receives the signal P ^4bit _8,11 output from the circuit 1103 and the signal H ^8bit _8,12 output from the circuit 1023,
The carry signal C for ⁸ bits of the 15th bit C ^8bit _8,12
Is a circuit that generates.

[0045] As described above, in this embodiment, the carry signal C ^16bit _{0, 15} and C ^12bit _{4, 15} and C ^8bit _{8, 15} and C ^4bit was divided from the logical blocks 1201 for each 4 bits _{12 and 15}
Is output.

According to the third embodiment, each logical block 1101 to 1104 achieves the same high speed as described in the first embodiment. Vertically stacked NMO in each element circuit
Since the number of S transistors is suppressed to three or less, high-speed operation of the domino circuit is possible. In the third embodiment, the total signal processing time from generation of 16-bit data to generation of the carry signal C ^16bit _0,15 can be reduced by about 15% compared to the circuit configuration according to the conventional technology.

Although the third embodiment is based on the positive logic circuit of the first embodiment, it is apparent that the third embodiment can also be configured with a negative logic circuit using an inverted signal as shown in the second embodiment. is there. In the case of a negative logic circuit, the third embodiment _reduces the total signal processing time from generation of 16-bit data to generation of the carry signal C ^16bit _0,15 by about 23%, as compared with the conventional circuit configuration. Can be shortened. Further, in the third embodiment, an example of the 16-bit carry signal generation circuit is shown, but it goes without saying that the logic circuit configuration according to the present invention can be extended to 32 bits or 64 bits. The advance processing of the logical operation and the reduction in the number of vertically stacked transistors according to the present invention can be widely used for speeding up various carry signal generation circuits.

[0048]

According to the present invention, the former stage circuit and the latter stage circuit constituting the carry signal generating circuit perform the arithmetic operation of the former stage circuit by pre-processing part of the logical operation of the latter stage circuit by the former stage circuit. The number of vertically stacked transistors can be reduced without increasing the number of vertically stacked NMOS transistors. Therefore, the overall carry signal generation time for the front and rear stages can be reduced, and the adder in the information processing device can be speeded up.

According to the present invention, the carry signal generation circuit is constituted by a negative logic circuit (logic circuit based on an inverted signal), so that the vertically stacked NMOS transistors in the subsequent circuit can be rearranged horizontally. Therefore, there is an effect that the number of vertically stacked transistors, which is a dominant factor in the operation time of the subsequent circuit, can be reduced, and the speed of the carry signal generation circuit and thus the adder can be increased.

The reduction of the number of vertically stacked transistors according to the present invention, that is, the reduction of logical operation processing, is essentially effective for speeding up the logic circuit regardless of the circuit system. Very effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a circuit that generates a propagation signal p _{0 according} to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a circuit for generating a signal _{Hi, i + 1} in the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a circuit for generating signals I ₁ , ₂ in the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a circuit for generating a 4-bit carry signal in the first embodiment of the present invention.

FIG. 5 is a circuit diagram of a circuit that generates an inverted signal P ₀ B of a propagation signal p _{0 in} a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a circuit that generates a signal _{Hi, i +} 1B in a second embodiment of the present invention.

FIG. 7 is a circuit diagram of a circuit that generates signals I _1,2 B in a second embodiment of the present invention.

FIG. 8 is a circuit diagram of a circuit that generates a 4-bit carry signal inverted signal in the second embodiment of the present invention.

Figure 9 is a circuit diagram of a circuit for generating the generation signal g _i in the prior art.

FIG. 10 is a circuit diagram of a circuit that generates a propagation signal p _{i in the related} art.

FIG. 11 is a circuit diagram of a circuit that generates a 4-bit carry signal in the related art.

FIG. 12 is a logic diagram of a 16-bit carry signal generation circuit according to a third embodiment of the present invention.

[Explanation of symbols]

101,111,121,131,201,211,2
21, 231, 301, 311, 321... PMOS transistors for precharge, 102, 103, 112-1
15, 122-125, 132-135, 202, 20
3,212-215, 222-225, 232-23
5,302,303,312,313,322-328
... NMOS transistors, 104, 116, 126, 1
36,204,216,226,236,304,31
4,329 ... CMOS inverter, 1001 to 100
5,1011,1012,1021 to 1023,103
1 to 1033 ... circuit, 1101 to 1104, 1201 ...
Logical block.

Claims (4)

[Claims] 1. A carry signal generation circuit of the adder binary 4-bit data a ₀ a ₁ a ₂ a ₃ and binary data _{b 0 b 1 b 2 b 3} , a Boolean algebra expressions a ₀ + b ₀ A circuit for generating a signal p ₀ represented by a Boolean expression a _i · b _i + a _{i + 1}
· B _i + 1 signal H _i represented by (i = 0,2), and a circuit for generating a _{i + 1,} the signal represented by the Boolean equation _{(a 1 + b 1) ·} (a 2 + b 2) I A circuit for generating ₁ , ₂ and a Boolean expression p ₀
And a circuit for generating a 4-bit carry signal represented by (H _0,1 + I _1,2 · H _2,3 ). 2. A carry signal generation circuit of the adder binary 4-bit data a ₀ a ₁ a ₂ a ₃ and binary data _{b 0 b 1 b 2 b 3} , the inverted signal a ₀ of the data B b ₁ B b
A circuit for generating a signal p ₀ B represented by a Boolean equation a ₀ B · b ₀ B using ₂ Bb ₃ B and b ₀ B b ₁ B b ₂ B b ₃ B; and a Boolean equation (a _i B + bi ₎ B) ・ (a _{i + 1} B + b
_{i + 1 B) (i =} 0,2 and a circuit for generating a signal H _{i, i +} 1 B represented by), Boolean equation _{a 1 B · b 1 B +} a 2 B · b 2
A circuit for generating a signal I _1,2 B represented by B and inversion of a 4-bit carry signal represented by a Boolean expression p ₀ B + H _0,1 B · (I _1,2 B + H _2,3 B) And a circuit for generating a signal. 3. A carry signal generating circuit according to claim 1, wherein said circuit represented by said Boolean expression is constituted by a CMOS domino logic circuit. 4. A binary data a n-bit (n is an integer of 4 or more) ₀ a ₁ a ₂ a ₃ ... a _n and binary data b ₀ b ₁ b ₂ b ₃
A carry signal generation circuit of an adder for b _n , wherein the carry signal generation circuit is configured based on the 4-bit carry signal generation circuit according to claim 1 or 2. Generation circuit.