JPH0561645A - Binary adder - Google Patents

Abstract

PURPOSE:To increase the propagation velocity of a carry signal by constituting a binary adder of transmission gates shortened at their delays and reducing the number of pass gates. CONSTITUTION:The adder is constituted of transmission gates 21, 22 controlled by either one of two binary adding inputs (x), (y), selecting either one of the one adding input and its inverted value and outputting the selected value as an intermediate sum value, transmission gates 23, 24 controlled by the intermediate sum value, selecting either one of a carry input C-IN and one adding input and outputting the selected value as a carry output C-OUT and transmission gates 25, 26 controlled by the intermediate sum value, selecting either one of the carry input C-IN and its inverted value and outputting the selected value as an added output SUM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a multiplier and an ALU.
The present invention relates to a binary adder composed of a semiconductor logic circuit capable of performing addition operation in the addition portion such as.

[0002]

2. Description of the Related Art An adder circuit is a basic circuit used in many semiconductor logic circuits. As shown in FIG. 2, the conventional adder circuit is composed of exclusive OR gates 1, 5, AND gates 2, 4 and OR gates 3. Then, the input signals from the terminals a, b and c are output to the terminals A and B through the respective gates 1, 2, ...
Here, a carry signal is output from the terminal A. However, the carry signal cannot be determined unless it passes through three gates in the order of gate 1, gate 2, and gate 3 before reaching the terminal A that outputs the carry signal. Note that a and b are addition inputs, c is a carry input, and the addition output is output to the terminal B.

[0003]

The conventional adder circuit has a problem that the carry signal has a large propagation delay because the carry signal is determined by passing through the three stages of gates as described above. That is, the propagation delay of the carry signal hinders the speedup of the adder circuit when they are connected in series and used.

The present invention has been made in view of the above problems, and an object thereof is to configure a circuit with a transmission gate having a small delay and to increase the propagation speed of a carry signal by reducing the number of passing gate stages. To do.

[0005]

SUMMARY OF THE INVENTION The present invention is a binary adder for deriving an addition output based on two addition inputs and a carry input of a binary number, and its inversion with one of two addition input values. A transmission gate that selects one of the values and derives it as an intermediate sum value, and is controlled by the intermediate sum value to select one of the carry input value and the addition input value and carry it. And a transmission gate derived as an output value.

Further, a binary adder according to another feature of the present invention is controlled by one of two binary addition input values, and one of the addition input value and its inverted value. , And a transmission gate that is controlled by the intermediate sum value and that selects one of the carry input value and the addition input to derive the carry output value. When,
A transmission gate controlled by the intermediate sum value to select one of the carry-in value and its inverted value and derive it as an added output value.

[0007]

The operation of the present invention will be described with reference to Table 1.
In Table 1, x and y are two data input values in the adder of the semiconductor logic circuit, and node 1, SUM, C
-IN and C-OUT are the intermediate sum output taking the exclusive OR of x and y respectively, the addition output signal of three input signals, the carry input signal from the lower digit, and the carry output signal to the upper digit. is there. First, when both x and y are high or low, that is, when the node 1 is low, x or y is output to C-OUT and C-IN is output to SUM. Also, x, y
C takes different values, that is, when the node is high, C
C-IN is output to -OUT, and an inverted signal of C-IN is output to SUM. By configuring the circuit only with the transmission gate and the inverter based on the above algorithm, the power consumption can be reduced and the propagation speed of the carry signal can be increased.

[0008]

[Table 1]

[0009]

FIG. 1 shows an adder circuit according to an embodiment of the present invention.
In FIG. 1, 16 and 17 are input terminals for binary inputs x and y, and an input terminal 18 and an output terminal 19 are a carry input C-IN from a lower digit and a carry output C-OUT to an upper digit, respectively. Is the terminal. Further, 20 is an output terminal of the addition output SUM. 11 to 15 are inverters, 21
26 are transmission gates.

The transmission gates 21 and 22 are
Opening / closing is controlled by the value of one of the addition inputs x and y (for example, y), and either one of the addition inputs (for example, x) and the value obtained by inverting the value by the inverter 11 are selected to output the intermediate sum output. Is output to the node 1. The inverter 12 is for complementary driving of the transmission gates 21 and 22.

The transmission gates 23 and 24 are
Opening and closing are controlled by the intermediate sum value of the node 1, one of the addition inputs (for example, y) and the carry input C-IN of the terminal 18.
And one of them is output to the terminal 19 as a carry output C-OUT. The inverter 13 is for complementary driving of the transmission gates 23, 24, 25 and 26.

The transmission gates 25 and 26 are
Opening and closing are controlled by the intermediate sum value of node 1, and terminal 1
8 carry input C-IN or one of the values obtained by inverting the carry input C-IN by the inverter 14 to select the addition output SU.
It is output to the terminal 20 via the inverter 15 as M.

The operation of the adder shown in FIG. 1 will be described. When the input signal y is low for the input signals x and y given to the input terminals 16 and 17, the transmission gate 21 is opened by the input signal y and the input signal x becomes The value as it is is sent to the node 1. When the input signal y is high, the input signal y opens the transmission gate 22 and the inverter 11 sends the inverted value of the input signal x to the node 1. By this operation, two one-bit sum signals are output to the node 1 as an intermediate sum.

Next, when the input signals x and y both have the same value, the signal output to the intermediate node 1 is low,
The transmission gate 23 is opened by this intermediate sum signal, and the input signal y is output to the output terminal 19 as a carry signal. When the intermediate sum node 1 is high, the transmission gate 24 is opened and the carry input signal C-IN supplied to the input terminal 18 is changed to the carry output signal C-O.
It is output to the output terminal 19 as UT. This establishes the final carry signal.

Further, in order to obtain the sum of the sum signal from the intermediate sum node 1 and the carry input signal C-INT, the input signal x,
The final sum signal SUM is determined by using the same circuit (comprising the inverter 14 and the transmission gates 25, 26) as the circuit from y to the intermediate sum node 1. With this configuration, a 3-input 2-output adder can be obtained.

Since the transmission gate is used in this circuit, the power consumption is considerably reduced. Further, the carry input signal C-IN can be output to the carry output terminal 19 only by passing through one transmission gate if the output to the intermediate sum node 1 is confirmed.

When this circuit is used by connecting a plurality of carry output signals C-OUT and carry input signals C-IN in series with each other, from Table 1, when the intermediate sum node 1 is low, Irrespective of the value of the carry input signal of the lower bit, the input signal x or y of that bit corresponds to the carry output signal C-OUT of that bit. In this case, the higher-order addition can be performed without waiting for the input of the carry signal from the lower-order. Further, when the intermediate sum node 1 is high, the carry input signal C-IN of the lower bit becomes the carry output signal C-OUT as it is and propagates to the upper bit. Therefore, the circuit configuration of that part has one transmission gate. With this simple structure, the propagation speed of the carry signal can be increased.

The present invention is shown in FIG.
Not only the CMOS circuit configuration as described above, but also a circuit having only NMOS can be configured.

[0019]

As described above, according to the present invention, 2
When the sum of the three signals from the three terminals for inputting the signal expressed in binary is output to the first output terminal (addition output) and the second output terminal (carry output) separately, output to the first output terminal Of the carry output to the second output terminal by the intermediate sum signal, which is the sum of the signals from the two fixed input terminals of the three input terminals, before the addition output signal of Since the propagation speed of the carry signal can be improved, the logical operation speed can be remarkably improved.

Further, according to the present invention, since the full adder can be constituted by the inverter and the transmission gate, the operation speed can be increased and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a binary full adder showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional binary adder.

[Explanation of symbols]

 11-15 Inverter 21-26 Transmission gate 16-18 Input terminal 19, 20 Output terminal

Claims (2)

[Claims] 1. A binary adder for deriving an addition output based on two addition inputs of binary numbers and a carry input, and selects either one of the two addition input values and its inverted value. And a transmission gate that is controlled by the above intermediate sum value and that selects one of the carry input value and one of the addition input values and derives it as the carry output value. A binary adder characterized by comprising. 2. A transmission gate which is controlled by one of two addition input values in binary number and which selects one of the addition input value and its inverted value to derive it as an intermediate sum value. A transmission gate controlled by the intermediate sum value to select one of the carry input value and the addition input value and derive as a carry output value; and a transmission gate controlled by the intermediate sum value, A binary adder, comprising: a transmission gate that selects one of a carry input value and its inverted value and derives it as an addition output value.