JPH08212057A - Full adder - Google Patents

Abstract

PURPOSE: To provide a full adder which consists of a small number of transistors. CONSTITUTION: A full adder consists of an XNOR circuit 1 which inputs an augend signal An and an addend signal Bn and obtains an inverted signal of an exclusive OR, an XOR circuit 2 which inputs the signals An and Bn and obtains an exclusive OR, the 1st and 2nd switch circuits S1 and S2 which output the signal An or a carry signal Cn-1 of the immediate lower digit to the next digit as a carry signal Cn in response to the output signals of the circuits 1 and 2, and the 3rd and 4th switch circuits S3 and S4 which output the signal Cn-1 or the signal obtained by inverting the signal Cn-1 by an inverting circuit 3 as a sum output signal Sn in response to the output signals of the circuits 1 nd 2. In such a constitution, a logic circuit consisting of many transistors can be replaced with a switch circuit. Thereby, the total number of MOS transistors can be extremely decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full adder.

[0002]

2. Description of the Related Art In a circuit for obtaining a logical value of a digital signal, a full adder is used as a logical circuit for adding two or more digits.

FIG. 5 shows a configuration example of a conventional full adder. As is clear from FIG. 5, the conventional full adder is composed of two half adders 51 and 52 and one OR (logical sum) circuit 53. Of the two half adders, the first half adder 51 is composed of one XOR (exclusive OR) circuit 54 and one AND (logical product) circuit 55. Similarly, the second half adder 52 is also composed of one XOR circuit 56 and one AND circuit 57.

In the full adder having such a configuration, when the sum add input A _n and the addend input B _n and the carry input C _n-1 from the digit immediately below are used to perform full addition (n Indicates that the two numbers A and B are numbers in the nth digit), first, 2
The two logic signals A _n and B _n are given by XO of the first half adder 51.
It is inputted to the R circuit 54 and the AND circuit 55, respectively.
Then, the XOR circuit 54 obtains the exclusive OR S _{n ′ of the} input logic signals A _n and B _n , and
The AND circuit 55 determines the first carry C _{n ′} .

The exclusive OR S _{n ′} obtained by the XOR circuit 56 is the XOR circuit 56 of the second half adder 52.
And the AND circuit 57, respectively. The carry input C from the digit immediately below is input to the other input terminal of the XOR circuit 56 and the AND circuit 57.
_n-1 is input respectively. Then, by the XOR circuit 56 and the AND circuit 57, similarly to the above-mentioned first half adder 51, the input exclusive OR S _{n ′ is} inputted.
Then, the binary addition with the carry input C _n-1 from the digit immediately below is performed, and the sum output S _n and the second carry C _{n ″} are obtained.

The second obtained by the AND circuit 57
C _{n ″} of the above is input to the OR circuit 53 together with the first carry C _{n ′} obtained by the AND circuit 55, and the logical sum is obtained here. one is output as the carry output C _n to digit on. also, the sum output S _n obtained by the XOR circuit 56, augend input a _n, addend input B _n and a three input The result is output as the final addition result of the carry input C _{n-1 In} this way, full addition based on the truth table as shown in Table 1 is performed.

[0007]

[Table 1]

[0008]

Generally, an XOR circuit,
The inverting circuit (NOT circuit), the NOR circuit, and the NAND circuit are configured as shown in (b), (c), (d), and (e) of FIG. 2, respectively. That is, the XOR circuit has two MOs.
It is composed of S-transistor, and the inverting circuit has two MO
The NOR circuit is composed of four M
The NAND circuit is composed of four MOS transistors.

Here, in the XOR circuit of FIG. 2B, in order to obtain the inverted signal X bar of the input X, an inverting circuit for inverting the value of the input X is required. Then, this inverting circuit is configured as shown in FIG. Further, as shown in FIG. 5, two XOR circuits 54 and 56 are provided.
Are connected in series, and the values input to each are different. Therefore, the inverting circuit described above is equivalent to the XOR circuit 5 of FIG.
You will need one for each of 4, 56. Therefore, each of the XOR circuits 54 and 56 requires four MOS transistors.

Further, the OR circuit 53 shown in FIG.
Since it is configured by providing the inverting circuit of FIG. 2C in the subsequent stage of the NOR circuit of FIG.
An S transistor is needed. Further, since the AND circuits 55 and 57 of FIG. 5 are each configured by providing the inverting circuit of FIG. 2C in the subsequent stage of the NAND circuit of FIG. Will be required.

Therefore, in order to configure the full adder as shown in FIG. 5, it is necessary to provide a total of 26 MOS transistors. As described above, the conventional full adder requires a large number of transistors, which complicates the circuit, resulting in a large circuit area.

The present invention has been made to solve such a problem, and an object thereof is to make it possible to configure a full adder with a small number of transistors.

[0013]

A full adder according to the present invention has three augend input terminals, an addend input terminal and a carry input terminal as input terminals, and a sum output terminal and a digit as output terminals. In a full adder having two raising output terminals, an XNOR circuit for inputting the augend signal and the augend signal from the augend input terminal and the augend input terminal to obtain an inverted signal of exclusive OR From the augend input terminal and the XOR circuit for calculating the exclusive OR by inputting the augend signal and the addend signal from the addend input terminal, and the digit immediately below the input from the carry input terminal. An inverting circuit that obtains an inverted signal of the carry signal of
An input terminal is connected to one of the augend input terminal or the addend input terminal, a control terminal is connected to an output terminal of the XNOR circuit, and an output terminal is connected to the carry output terminal. A first switch circuit that conducts between the input terminal and the output terminal in accordance with an output signal of the XNOR circuit given to the control terminal, and an input terminal connected to the carry input terminal, and the XOR circuit. Has a control terminal connected to the output terminal thereof and an output terminal connected to the carry output terminal, and connects between the input terminal and the output terminal in accordance with the output signal of the XOR circuit given to the control terminal. An input terminal is connected to the carry switch and a carry input terminal, a control terminal is connected to the output terminal of the XNOR circuit, and an output terminal is connected to the sum output terminal. A third switch circuit, which conducts between the input terminal and the output terminal according to an output signal of the XNOR circuit given to a child, and an input terminal connected to the output terminal of the inverting circuit, A control terminal is connected to the output terminal, an output terminal is connected to the sum output terminal, and conduction is established between the input terminal and the output terminal according to the output signal of the XOR circuit given to the control terminal. And a fourth switch circuit.

Another feature of the present invention is that the above X
The NOR circuit and the XOR circuit are provided in parallel so that the augend signal and the addend signal are simultaneously input.

Another feature of the present invention is that it has three augend input terminals, an addend input terminal and a carry input terminal as input terminals, and a sum output terminal and a carry output terminal as output terminals. In the full adder having the two, an XOR circuit for inputting the augend signal and the augend signal from the augend input terminal and the augend input terminal to obtain an exclusive OR, and the XOR circuit
A first inversion circuit for obtaining an inversion signal of the exclusive OR obtained by the OR circuit, and a second inversion circuit for obtaining an inversion signal of the carry signal from the digit immediately below that input from the carry input terminal.
Input circuit is connected to one of the augend input terminal and the addend input terminal, the control terminal is connected to the output terminal of the first inverting circuit, and the carry output terminal is connected to the carry output terminal. A first switch circuit having an output terminal connected thereto, which conducts between the input terminal and the output terminal in accordance with an output signal of the first inverting circuit given to the control terminal, and the carry input. The input terminal is connected to the end, and the XO
A control terminal is connected to the output terminal of the R circuit, an output terminal is connected to the carry output terminal, and the input terminal and the output terminal are connected in accordance with the output signal of the XOR circuit given to the control terminal. A second switch circuit that conducts between the second switch circuit and an input terminal is connected to the carry input terminal.
A control terminal is connected to the output terminal of the inverting circuit of the above, and an output terminal is connected to the sum output terminal, and the input terminal and the output are output according to the output signal of the first inverting circuit given to the control terminal. An input terminal is connected to an output terminal of the second inverting circuit, a control terminal is connected to an output terminal of the XOR circuit, and an output terminal is connected to the sum output terminal. Are connected to each other, and are configured by a fourth switch circuit that conducts between the input terminal and the output terminal in accordance with the output signal of the XOR circuit given to the control terminal. It is a thing.

[0016]

Since the present invention comprises the above technical means, for example,
There are 4 switch circuits consisting of one MOS transistor.
By appropriately arranging each of them, it is possible to realize the same function as that of the conventional full adder using a large number of logic circuits composed of a large number of MOS transistors with four switch circuits and a small number of logic circuits. As a result, the logic circuit in the conventional full adder can be largely replaced with a switch circuit to configure the full adder.

According to another feature of the invention, the XNO
Since the same signal is input to both the R circuit and the XOR circuit,
The inverting circuit required to be provided in the input stage is provided with the XNO
It can be shared by the R circuit and the XOR circuit.

[0018]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of the full adder of this embodiment. This full adder has an addend input terminal 4 and an addend input terminal 5
And the addend signal A from the three input terminals of the carry input terminal 6
_n , the addend signal B _n, and the carry signal (carry) C _n-1 from the digit immediately below are input to perform a predetermined operation, and the carry output terminal 7 and the sum output terminal 8 output from two output terminals. The carry signal (carry) C _n to the next digit and the sum output signal S _n are output as the calculation result of full addition.

As shown in FIG. 1, the full adder of the present embodiment has first to fourth switch circuits S1 to S1 each composed of an XNOR circuit 1, an XOR circuit 2, an inverting circuit 3 and one MOS transistor. The configuration of S4 is as follows.

That is, in the full adder of the present embodiment, first, the XNOR circuit 1 for inputting the augend signal A _n and the addend signal B _n to obtain the inverted signal of the exclusive OR, and the augend as well. An XOR circuit 2 for inputting the signal A _n and the addend signal B _n to obtain an exclusive OR is provided in parallel.

The input terminal of the first switch circuit S1 is connected to the augend input terminal 4, the control terminal is connected to the output terminal of the XNOR circuit 1, and the output terminal is the carry output terminal. 7 and is turned on in response to a signal output from the XNOR circuit 1. The input terminal of the second switch circuit S2 is connected to the carry input terminal 6, and the control terminal of the second switch circuit S2 is the X terminal.
It is connected to the output terminal of the OR circuit 2, the output terminal is connected to the carry output terminal 7, and is turned on in accordance with the signal output from the XOR circuit 2.

As a result, the augend signal A _n input to the first switch circuit S1 and the second switch circuit S2 are input.
The carry signals C _n-1 input to the both are output as carry signals C _n to the next carry when the respective switch circuits are in the ON state. That is, either the first switch circuit S1 or the second switch circuit S2 is turned on according to the augend signal A _n and the addend signal B _n input to the full adder of the present embodiment. As a result, either the augend signal A _n input to the first switch circuit S1 or the second switch circuit S2 or the carry signal C _n-1 from the digit immediately below is sent to the next digit. It is output as a carry signal C _n .

The input terminal of the third switch circuit S3 is connected to the carry input terminal 6, the control terminal is connected to the output terminal of the XNOR circuit 1, and the output terminal is connected to the sum output terminal 8. They are connected and are turned on in response to a signal output from the XNOR circuit 1. The input terminal of the fourth switch circuit S4 is connected to the output terminal of the inverting circuit 3, and the control terminal thereof is the above-mentioned XO.
It is connected to the output terminal of the R circuit 2, the output terminal is connected to the sum output terminal 8, and is turned on in response to the signal output from the XOR circuit 2. Here, the inverting circuit 3 obtains an inversion signal of the carry signal C _n-1 from the digit immediately below, which is input from the carry input terminal 6.

As a result, the carry signal C _n-1 from the digit immediately below and the fourth signal inputted to the third switch circuit S3 and the fourth signal
The inverted signals of the carry signal C _n-1 input to the switch circuit S4 of the above are both the augend signal A _n , the addend signal B _n, and the carry signal C _n- when the respective switch circuits are in the ON state. ₁
Is output as a sum output signal S _n which is the final addition result of

That is, either the third switch circuit S3 or the fourth switch circuit S4 is turned on according to the augend signal A _n and the addend signal B _n input to the full adder. As a result, either the carry signal C _n-1 or its inverted signal from the digit immediately below that is input to the third switch circuit S3 or the fourth switch circuit S4 is output as the sum output signal S _n. It

By configuring the full adder of this embodiment as described above, the same result as in Table 1 can be obtained. This means that the three inputs, the augend signals A _n ,
Addend signal B _n and carry signal C from the digit immediately below
_This can be confirmed by applying a value of “0” or “1” to _n−1 , but in the following, a part of the eight combinations shown in Table 1 will be described as an example.

For example, it is assumed that the values of the augend signal A _n , the addend signal B _n and the carry signal C _n-1 are all "0".
In this case, in the XNOR circuit 1, the output value of the XNOR circuit 1 becomes "1" because the exclusive OR of the augend signal A _n and the addend signal B _n is inverted. Also, X
In the OR circuit 2, the output value of the XOR circuit 2 becomes "0" by taking the exclusive OR of the augend signal A _n and the addend signal B _n . Therefore, the first switch circuit S
1 and the third switch circuit S3 are turned on, and the second switch circuit S2 and the fourth switch circuit S4 are turned off.

At this time, since the augend signal A _n is input to the first switch circuit S1, the value "0" of the augend signal A _n is the carry signal C to the next digit. Output as _n . Further, since the carry signal C _n-1 from the immediately lower carry is input to the third switch circuit S3, the value "0" of the carry signal C _n-1 is the sum output signal S. _n
Is output as

The values of the augend signal A _n , the addend signal B _n, and the carry signal C _n-1 are "0", "1", and "0", respectively.
Suppose In this case, in the XNOR circuit 1, the output value of the XNOR circuit 1 becomes "0" because the exclusive OR of the augend signal A _n and the addend signal B _n is inverted. In addition, in the XOR circuit 2, the exclusive OR of the augend signal A _n and the addend signal B _n is taken, so that the XOR
The output value of the circuit 2 becomes "1". Therefore, the first switch circuit S1 and the third switch circuit S3 are turned off, and the second switch circuit S2 and the fourth switch circuit S4.
And turn on.

At this time, since the carry signal C _n-1 from the digit immediately below is input to the second switch circuit S2, the value "0" of the carry signal C _n-1 is obtained. It is output as a carry signal C _n to the next digit. Further, since the inverted signal of the carry signal C _n-1 is input to the fourth switch circuit S4, the value "1" of the inverted signal of the carry signal C _n-1 is the sum output signal. It is output as S _n .

It is also assumed that the values of the augend signal A _n , the addend signal B _n and the carry signal C _n-1 are all "1". In this case, in the XNOR circuit 1, the exclusive OR of the augend signal A _n and the addend signal B _n is inverted,
The output value of the XNOR circuit 1 becomes "1". Also, XOR
In the circuit 2, the exclusive OR of the addend signal A _n and the addend signal B _n is taken, so that the output value of the XOR circuit 2 becomes “0”. Therefore, the first switch circuit S1 and the third switch circuit S3 are turned on, and the second switch circuit S2 and the fourth switch circuit S4 are turned off.

At this time, since the augend signal A _n is input to the first switch circuit S1, the value "1" of the augend signal A _n is the carry signal C to the next digit. Output as _n . Further, since the carry signal C _n-1 from the digit immediately below is input to the third switch circuit S3, the value "1" of the carry signal C _n-1 is the sum output signal S. _n
Is output as

[0033] In the configuration shown in FIG. 1, but that you enter the augend signal A _n to the first switch circuit S1, the addend signal B _n in place of the augend signal A _n The same result can be obtained by inputting to the first switch circuit S1.

By the way, the XNOR circuit 1 shown in FIG.
The XOR circuit 2 and the inverting circuit 3 are configured as shown in (a), (b) and (c) of FIG. 2, respectively. Further, as described above, the four switch circuits S1 to S4
Are each composed of one MOS transistor.

As described in the conventional example, the inverted signal X of the input X in the circuit shown in FIGS.
To obtain the bar, a circuit for inverting the value of the input X is required, but in the present embodiment, the XNOR circuit 1 and the XOR circuit 2 are provided in parallel and the same augend signal A is obtained.
_{Since n} and the addend signal B _n are input, the circuit for obtaining the inverted signal X _n bar of the input X _n can be shared by the XNOR circuit 1 and the XOR circuit 2.

Therefore, the full adder as shown in FIG. 1 can be actually composed of a total of 12 MOS transistors as shown in FIG. As described above, in the past, a total of 26 MOS transistors were required to form a full adder, whereas according to the present embodiment, 12 MOS transistors are required.
A full adder can be configured by using individual MOS transistors, and the number of transistors used can be reduced.

Further, as can be seen from FIG. 3, since the full adder of this embodiment has excellent vertical symmetry, each transistor can be easily arranged, which facilitates wiring. You can also Therefore, the circuit configuration can be simplified and the circuit area can be reduced.

Further, in the conventional full adder shown in FIG. 5, there are three stages of the logical operation by the first half adder 51, the logical operation by the second half adder 52 and the logical operation by the OR circuit 53. The total addition is done separately. On the contrary,
In this embodiment, the logical operation and XOR by the XNOR circuit 1
The logical operation by the circuit 2 and the logical operation by the inverting circuit 3 are performed in parallel, and then the first to fourth switch circuits S1 are performed.
The full addition is performed by a two-step process of selecting an appropriate signal through S4. Moreover, the signal can be selected by simply turning on / off each of the switch circuits S1 and S2, so that the calculation speed of full addition can be improved.

In the above embodiment, the XNOR circuit 1
The XOR circuit 2 obtains the exclusive OR of the augend signal A _n and the addend signal B _n and its inverted signal. On the other hand, as shown in FIG. 4, the XOR circuit 2 and the inverting circuit 9 are connected in series so that the XOR circuit 2 obtains an exclusive OR, and the inverting circuit 9 obtains its inverted signal. Good.

Also in this case, the number of transistors used to form the full adder is 12, and the number of transistors used can be reduced as compared with the conventional 26 transistors. Therefore, even when the full adder is configured as shown in FIG. 4, the circuit configuration can be simplified and the circuit area can be reduced.

[0041]

As described above, according to the present invention, the four switch circuits are appropriately arranged to provide one XNOR circuit, one XOR circuit, and one XOR circuit. Since the full adder is composed of the four inverting circuits and the four switch circuits, the number of logic circuits composed of a large number of transistors can be reduced as compared with the conventional one, and the full adder can be formed. The number of transistors used can be significantly reduced. Therefore, the circuit area of the full adder can be reduced and the wiring can be facilitated.

According to the invention described in claim 2, X
Since the NOR circuit and the XOR circuit are provided in parallel so that the augend signal and the addend signal are simultaneously input to the respective circuits, it is necessary to provide the NOR circuit and the XOR circuit at the input stage of the XNOR circuit and the XOR circuit. Inversion circuits can be shared, and the number of transistors used can be further reduced.

According to the invention described in claim 3, 4
By appropriately arranging the switch circuits, a full adder is configured by one XOR circuit, two inverting circuits, and the above four switch circuits. The number of transistors used can be reduced as compared with the conventional one, and the number of transistors used to form a full adder can be significantly reduced. Therefore, the circuit area of the full adder can be reduced and the wiring can be facilitated.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a full adder that is an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration of each circuit shown in FIGS. 1 and 5;

FIG. 3 is a diagram showing a configuration when the full adder shown in FIG. 1 is expressed by using MOS transistors.

FIG. 4 is a diagram showing the configuration of a full adder that is another embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional full adder.

[Explanation of symbols]

 1 XNOR circuit 2 XOR circuit 3 Inversion circuit 4 Addend input end 5 Addend input end 6 Carry input end 7 Carry output end 8 Sum output end 9 Inversion circuit S1-S4 switch circuit

Claims (3)

[Claims] 1. A full adder having three addend input terminals, an addend input terminal and a carry input terminal as input terminals, and two sum output terminals and carry output terminals as output terminals. An XNOR circuit for inputting the addend signal and the addend signal from the addend input terminal and the addend input terminal to obtain an inverted signal of an exclusive OR, and the addend input terminal and the addend input XOR for inputting the augend signal and the addend signal from the end and obtaining the exclusive OR
A circuit, an inverting circuit that obtains an inverted signal of the carry signal from the digit immediately below that is input from the carry input terminal, and an input terminal at one of the augend input terminal or the addend input terminal. A control terminal is connected to the output terminal of the XNOR circuit, an output terminal is connected to the carry output terminal, and the input terminal and the output terminal of the XNOR circuit are connected according to the output signal of the XNOR circuit given to the control terminal. A first switch circuit conducting between the output terminal and the carry input terminal is connected to the input terminal, the output terminal of the XOR circuit is connected to the control terminal, and the carry output terminal is connected to the output terminal. And a second switch circuit for electrically connecting between the input terminal and the output terminal according to an output signal of the XOR circuit given to the control terminal, and an input terminal connected to the carry input terminal. , XNOR above
A control terminal is connected to the output terminal of the circuit, an output terminal is connected to the sum output terminal, and the output terminal of the XNOR circuit is connected between the input terminal and the output terminal according to the output signal of the XNOR circuit applied to the control terminal. An input terminal is connected to the output terminal of the inverting circuit and a third switch circuit that conducts, and
A control terminal is connected to the output terminal of the OR circuit, an output terminal is connected to the sum output terminal, and between the input terminal and the output terminal according to the output signal of the XOR circuit given to the control terminal. And a fourth switch circuit that conducts the. 2. The XNOR circuit and the XOR circuit are arranged in parallel so that the augend signal and the augend signal are input at the same time. Adder. 3. A full adder having three addend inputs, an addend input end, and a carry input end as input ends, and two sum output ends and carry output ends as output ends. XOR for calculating exclusive OR by inputting the augend signal and the addend signal from the addend input terminal and the addend input terminal
A circuit, a first inverting circuit for obtaining an inverted signal of the exclusive OR obtained by the XOR circuit, and a first inverting circuit for obtaining an inverted signal of the carry signal from the digit immediately below that input from the carry input terminal. An input terminal is connected to one of the augend input terminal and the addend input terminal, and a control terminal is connected to the output terminal of the first inverter circuit; An output terminal is connected to the first switch circuit, the first switch circuit electrically connecting between the input terminal and the output terminal according to the output signal of the first inverting circuit given to the control terminal, and the carry. The input terminal is connected to the input terminal, the control terminal is connected to the output terminal of the XOR circuit, the output terminal is connected to the carry output terminal, and the output signal of the XOR circuit is given to the control terminal. And the above input terminal A second switch circuit conducting between the output terminal and the input terminal is connected to the carry input terminal, a control terminal is connected to the output terminal of the first inverting circuit, and an output is output to the sum output terminal. A third switch circuit having terminals connected to each other, which electrically connects between the input terminal and the output terminal according to an output signal of the first inverting circuit given to the control terminal; and a second inverting circuit. The input terminal is connected to the output terminal of the circuit,
A control terminal is connected to the output terminal of the XOR circuit, an output terminal is connected to the sum output terminal, and the input terminal and the output terminal are connected in accordance with the output signal of the XOR circuit given to the control terminal. A full adder characterized by being constituted by a fourth switch circuit which conducts between them.